KR19990005482A - Method for forming charge storage electrode of semiconductor device - Google Patents
Method for forming charge storage electrode of semiconductor device Download PDFInfo
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- KR19990005482A KR19990005482A KR1019970029680A KR19970029680A KR19990005482A KR 19990005482 A KR19990005482 A KR 19990005482A KR 1019970029680 A KR1019970029680 A KR 1019970029680A KR 19970029680 A KR19970029680 A KR 19970029680A KR 19990005482 A KR19990005482 A KR 19990005482A
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- 238000000034 method Methods 0.000 title claims abstract description 34
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims description 19
- 239000007789 gas Substances 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 235000013399 edible fruits Nutrition 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 claims 1
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 239000011259 mixed solution Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000635 electron micrograph Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 제조 분야에 관한 것임.The present invention relates to the field of semiconductor manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 단차를 유발을 억제하여 후속 공정을 용이하게 하는 반도체 장치의 전하저장 전극 형성방법을 제공하고자 함.An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device which suppresses the generation of steps to facilitate subsequent processes.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 통상적인 경사 식각 공정 및 도핑 및 비도핑 산화막의 높은 식각 선택비를 갖는 등방성 식각 공정을 실시하여 자기정렬 콘택을 이루며, 전하저장 전극에 의한 단차를 높이지 않으면서 충분한 정전용량을 갖는 전하저장 전극을 형성함.The present invention forms a self-aligned contact by performing a conventional gradient etching process and an isotropic etching process having a high etching selectivity of the doped and undoped oxide film, and has a sufficient capacitance without increasing the step by the charge storage electrode. Forming a storage electrode.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 메모리 장치 제조에 이용됨.Used to manufacture semiconductor memory devices.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 메모리 장치의 캐패시터 제조 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a capacitor manufacturing process of a semiconductor memory device.
반도체 장치의 집적도가 증가함에 따라 반도체 장치의 리프레시(refresh) 특성이 큰 문제로 부각되었으며, 이를 해결하는 하나의 방안으로서 캐패시터의 하부 전극인 전하저장 전극의 높이를 올려 정전용량을 증가시키는 기술에 대한 많은 연구·개발이 진행되어 왔다.As the degree of integration of semiconductor devices has increased, the refresh characteristics of semiconductor devices have emerged as a big problem. As a solution to this problem, a technique for increasing capacitance by increasing the height of a charge storage electrode, which is a lower electrode of a capacitor, has been described. Many research and developments have been conducted.
그러나, 이러한 전하저장 전극 높이의 증가는 전하저장 전극이 있는 지역(셀지역)과 없는 지역(주변회로 지역)간의 단차를 만들어, 후속 금속 배선 형성 공정에서 브릿지(bridge)를 유발하는 원인으로 작용하며, 이러한 브릿지는 반도체 장치의 신뢰도 및 수율을 저하시키는 요인이 된다. 때문에, 전하저장 전극의 높이를 증가시키는 방법에는 한계가 있다고 할 수 있다.However, this increase in charge storage electrode height creates a step between the region where the charge storage electrode is located (cell region) and the region where there is no (circuit circuit region), which causes a bridge in the subsequent metallization process. This bridge becomes a factor of lowering the reliability and yield of the semiconductor device. Therefore, it can be said that there is a limit to the method of increasing the height of the charge storage electrode.
본 발명은 단차를 유발을 억제하여 후속 공정을 용이하게 하는 반도체 장치의 전하저장 전극 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device which suppresses the generation of steps to facilitate subsequent processing.
도 1a 내지 도 1e는 본 발명의 일실시예에 따른 전하저장 전극 형성 공정도.1A to 1E are diagrams illustrating a process of forming a charge storage electrode according to an exemplary embodiment of the present invention.
도 2a는 도 1c의 전자 현미경 사진.2A is an electron micrograph of FIG. 1C.
도 2b는 도 1d의 전자 현미경 사진.2b is an electron micrograph of FIG. 1d.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 11 : 게이트 산화막10 silicon substrate 11 gate oxide film
12 : 게이트 전극 13 : 마스크 산화막12 gate electrode 13 mask oxide film
14 : 스페이서 산화막 15 : 층간 절연막14 spacer oxide film 15 interlayer insulating film
16 : 산화막 17 : 포토레지스트 패턴16 oxide film 17 photoresist pattern
18 :전하저장 전극18: charge storage electrode
상기 목적을 달성하기 위하여 본 발명의 전하저장 전극 형성방법은 반도체 기판 상에 게이트 산화막과, 마스크 산화막 및 스페이서 절연막으로 절연된 게이트 전극을 형성하는 제1 단계; 전체구조 상부에 제1 층간 절연막 및 제2 층간 절연막을 차례로 형성하는 제2 단계; 전하저장 전극 콘택홀 형성을 위한 마스크를 사용하여 상기 제2 층간 절연막 및 상기 제1 층간 절연막을 차례로 선택적으로 경사 식각하는 제3 단계: 상기 제1 층간 절연막의 등방성 식각을 실시하여 상기 제2 층간절연막 하부에 언더컷 부위를 형성하는 제4 단계; 및 전체구조 상부에 전하저장 전극 형성을 위한 전도막을 형성하는 제5 단계를 포함하여 이루어진다.In order to achieve the above object, the charge storage electrode forming method of the present invention includes a first step of forming a gate oxide film, a gate oxide insulated with a mask oxide film and a spacer insulating film on a semiconductor substrate; A second step of sequentially forming a first interlayer insulating film and a second interlayer insulating film over the entire structure; A third step of selectively obliquely etching the second interlayer insulating layer and the first interlayer insulating layer using a mask for forming a charge storage electrode contact hole: isotropic etching of the first interlayer insulating layer to perform the second interlayer insulating layer A fourth step of forming an undercut portion in the lower portion; And a fifth step of forming a conductive film for forming a charge storage electrode on the entire structure.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 일실시예에 따른 전하저장 전극 형성 공정도이다.1A to 1E are flowcharts of forming a charge storage electrode according to an exemplary embodiment of the present invention.
우선 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 게이트 산화막(11)과, 스페이서 절연막(14) 및 마스크 산화막(13)으로 절연된 게이트 전극(12)를 형성한다. 이때 스페이서 절연막(14) 및 마스크 산화막(13)은 TEOS(TetraEthy Osso Silicate)계 산화막, LTO(Low Temperature Oxide), MTO(Medium Temperature Oxide), HTO(High Temperature Oxide) 등의 비도핑 산화막(undoped oxide)을 사용하여 형성하며, 그 형성 공정은 통상적인 방식을 사용한다.First, as shown in FIG. 1A, a gate oxide film 11 and a gate electrode 12 insulated from the spacer insulating film 14 and the mask oxide film 13 are formed on the silicon substrate 10. In this case, the spacer insulating layer 14 and the mask oxide layer 13 are undoped oxides such as a TEOS (TetraEthy Osso Silicate) oxide layer, a low temperature oxide (LTO), a medium temperature oxide (MTO), and a high temperature oxide (HTO). ), And the forming process uses a conventional method.
다음으로 도 1b에 도시된 바와 같이 소정의 층간 절연막(15) 및 산화막(16)을 차례로 증착하고, 그 상부에 전하저장 전극 콘택홀 형성을 위한 포토레지스트 패턴(17)을 형성한다. 이때 층간 절연막(15)로서 BSG(Boro Silicate Glass)막, PSG(Phospho Silicate Glass)막, BPSG(BoroPhospho Silicate Glass)막 등의 도핑 산화막(doped oxide)을 사용하며, 산화막(16)으로서 비도핑 산화막을 사용한다.Next, as shown in FIG. 1B, a predetermined interlayer insulating film 15 and an oxide film 16 are sequentially deposited, and a photoresist pattern 17 for forming a charge storage electrode contact hole is formed thereon. In this case, a doped oxide film such as a BSG (Boro Silicate Glass) film, a PSG (Phospho Silicate Glass) film, or a BPSG (BoroPhospho Silicate Glass) film is used as the interlayer insulating film 15, and the undoped oxide film is used as the oxide film 16. Use
계속하여, 도 1c에 도시된 바와 같이 포토레지스트 패턴(17)을 식각 장벽으로하여 산화막(16) 및 층간 절연막(15)를 건식 식각하여 일차적인 전하저장 전극 콘택홀을 형성하고, 포토레지스트 패턴(17)을 제거한다.Subsequently, as illustrated in FIG. 1C, the oxide layer 16 and the interlayer insulating layer 15 are dry-etched using the photoresist pattern 17 as an etch barrier to form a primary charge storage electrode contact hole, and the photoresist pattern ( 17) Remove.
여기서 건식 식각은 하부의 게이트 전극(12)과 콘택간의 단락(short)을 방지할 수 있도록 콘택홀과 게이트 전극(12)과의 중첩 정확도(overlay accuracy)까지 고려하여 최종적인 CD(Critical Dimension)가 작아지도록 즉, DICD(Develop Inspection Critical Dimension)와 FICD(Final Inspection Critical Dimension)의 비가 2 : 1 이상이 되도록 경사 정도를 크게 한다.In this case, dry etching may be performed in consideration of the overlay accuracy of the contact hole and the gate electrode 12 to prevent short between the gate electrode 12 and the contact at the bottom. The degree of inclination is increased so that the ratio becomes smaller, that is, the ratio of the development inspection critical dimension (DICD) and the final inspection critical dimension (FICD) is 2: 1 or more.
경사 식각 방식은 통상적인 방식을 사용하며 그 세부 공정 조건을 살펴보면, 가열 실리콘 루프(heated silicon roof)가 장착된 ICP(Induced coupled plasma) 방식의 고밀도 플라즈마 방식의 건식 식각 챔버를 사용하며, C3F8가스 및 CO 가스를 사용하되, 총 가스유량을 30∼150 sccm로 하고, C3F8가스와 CO 가스의 플로우 비를 1 : 0.5∼5로 한다. 여기서 C3F8가스는 CF4, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2가스 등의 CF 계열 가스로 대체하여 사용할 수 있다. 또한 220℃∼290℃ 범위의 실리콘 루프 온도와, 1600 W∼2800 W 범위의 ICP RF 전력 및 600 W∼1800 W 범위의 바아어스(bias) RF 전력을 사용한다. 또한, 경사 식각은 CF4, NF3, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2가스 등의 F기를 포함하는 가스를 주 반응 가스로 하는 플라즈마 식각 방식을 사용할 수도 있으며, NH3가스를 주 반응 가스로 하는 플라즈마 식각 방식을 사용할 수도 있다. 도 2a에 경사 식각 후의 전자 현미경 사진을 도시하였다.The gradient etching method uses a conventional method, and the detailed process conditions include a dry etch chamber of a high density plasma method of an induced coupled plasma (ICP) method with a heated silicon roof, and C 3 F 8 gas and CO gas are used, the total gas flow rate is 30-150 sccm, and the flow ratio of C 3 F 8 gas and CO gas is 1: 0.5-5. The C 3 F 8 gas may be replaced with CF-based gas such as CF 4 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , CH 2 F 2 gas. Silicon loop temperatures in the range of 220 ° C. to 290 ° C., ICP RF power in the 1600 W to 2800 W range and bias RF power in the 600 W to 1800 W range are also used. Incidentally, the gradient etching is performed using a gas containing F groups such as CF 4 , NF 3 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , and CH 2 F 2 gas as the main reaction gas. A plasma etching method may be used, and a plasma etching method using NH 3 gas as a main reaction gas may be used. 2A shows an electron micrograph after oblique etching.
이어서, 도 1d에 도시된 바와 같이 산화막(16), 마스크 산화막(13) 및 스페이서 절연막(14)에 대한 층간 절연막(10)의 높은 식각 선택비를 갖는 등방성 식각 공정을 실시한다. 이때 등방성 식각은 인산(H3PO4)을 주 식각제로 하고, NH4OH와 과수 및 순수의 혼합비를 적절히 조절하여 사용할 수 있다. 그리고 통상적인 건식 식각 및 습식 세정 공정을 진행할 수도 있다. 도 2b에 등방성 식각 후의 전자 현미경 사진을 도시하였다.Next, as shown in FIG. 1D, an isotropic etching process having a high etching selectivity of the interlayer insulating film 10 with respect to the oxide film 16, the mask oxide film 13, and the spacer insulating film 14 is performed. In this case, the isotropic etching may be used by using phosphoric acid (H 3 PO 4 ) as the main etchant and by appropriately adjusting the mixing ratio of NH 4 OH, fruit water and pure water. In addition, conventional dry etching and wet cleaning processes may be performed. 2B shows an electron micrograph after isotropic etching.
다음으로, 도 1e에 도시된 바와 같이 폴리실리콘막, 금속산화물 등의 전도막을 증착하고, 전하저장 전극 형성을 위한 마스크를 사용하여 전도막을 선택적 식각함으로써 전하저장 전극(18)을 디파인한다.Next, as illustrated in FIG. 1E, a conductive film such as a polysilicon film or a metal oxide is deposited, and the charge storage electrode 18 is defined by selectively etching the conductive film using a mask for forming the charge storage electrode.
상기한 실시예에 나타난 바와 같이 본 발명은 통상적인 경사 식각 공정 및 도핑 및 비도핑 산화막의 높은 식각 선택비를 갖는 등방성 식각 공정을 실시하여 자기정렬 콘택을 이루며, 전하저장 전극에 의한 단차를 높이지 않으면서 충분한 정전용량을 갖는 전하저장 전극을 형성할 수 있다.As shown in the above embodiment, the present invention performs self-aligned contact by performing a conventional oblique etching process and an isotropic etching process having a high etching selectivity of doped and undoped oxide films, thereby increasing the step by the charge storage electrode. It is possible to form a charge storage electrode having a sufficient capacitance without.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 비교적 간단한 공정을 통해 단차를 유발하지 않으면서 큰 전하보존용량을 가지는 전하저장 전극을 형성할 수 있다.As described above, the present invention can form a charge storage electrode having a large charge storage capacity without causing a step through a relatively simple process.
또한, 통상적으로 사용되는 질화막 식각장벽을 이용한 자기 정렬 콘택홀 공정보다 용이하게 자기 정렬 효과를 얻을 수 있다.In addition, the self-aligning effect may be more easily obtained than a self-aligning contact hole process using a nitride film etching barrier.
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| KR100403328B1 (en) * | 1999-11-03 | 2003-10-30 | 주식회사 하이닉스반도체 | Forming method for self aligned contact of semiconductor device |
| KR100603929B1 (en) * | 2002-03-04 | 2006-07-24 | 삼성전자주식회사 | Cylindrical capacitors having a stepped sidewall and methods for fabricating the same |
| KR100604555B1 (en) * | 2001-06-21 | 2006-07-28 | 주식회사 하이닉스반도체 | Method of forming a capacitor in a semiconductor device |
| KR100625624B1 (en) * | 1999-01-22 | 2006-09-20 | 후지쯔 가부시끼가이샤 | Semiconductor device and method for fabricating the same |
| KR100753122B1 (en) * | 2002-06-29 | 2007-08-29 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
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| KR100507863B1 (en) * | 1998-06-30 | 2005-11-16 | 주식회사 하이닉스반도체 | Method for forming contact hole in semiconductor device |
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| JP3020257B2 (en) * | 1989-09-13 | 2000-03-15 | 沖電気工業株式会社 | Method for manufacturing semiconductor memory device |
| JPH05283643A (en) * | 1992-03-31 | 1993-10-29 | Sanyo Electric Co Ltd | Manufacture of semiconductor element |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100625624B1 (en) * | 1999-01-22 | 2006-09-20 | 후지쯔 가부시끼가이샤 | Semiconductor device and method for fabricating the same |
| KR100403328B1 (en) * | 1999-11-03 | 2003-10-30 | 주식회사 하이닉스반도체 | Forming method for self aligned contact of semiconductor device |
| KR100604555B1 (en) * | 2001-06-21 | 2006-07-28 | 주식회사 하이닉스반도체 | Method of forming a capacitor in a semiconductor device |
| KR100603929B1 (en) * | 2002-03-04 | 2006-07-24 | 삼성전자주식회사 | Cylindrical capacitors having a stepped sidewall and methods for fabricating the same |
| KR100753122B1 (en) * | 2002-06-29 | 2007-08-29 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
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