JPH10341005A - Interconnection of high-density integrated circuit, and formation method for conductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a conductor and the interconnection of a high-density integrated circuit where resist processes are reduced, by forming the second insulating wall spacer at the first sidewall of the first opening, and stopping the first opening with an upper electrode plug, and electrically connecting the lower electrode with a source region. SOLUTION: A second insulating cap film 28 and a dielectric film 26 made on a semiconductor substrate 2 are selectively etched to cover a source 16, and then a lower electrode plug 30A and a drain contact 30B to a drain 14 are made. Next, a second wall spacer 34 is made at the first sidewall of the first opening. Then, storage electrodes 30A and 36 are made by stopping the first opening with an upper electrode plug 36 and connecting it with the lower electrode plug 30A. Next, a capacitor dielectric film 38 is made to cover the upper electrode plug 36. Then, after formation of an upper electrode 40 on the capacitor dielectric film 38, an upper insulating film 50 and a metal film 52 are made on the upper electrode film 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a high-density semiconductor circuit, and more particularly to a method for forming interconnections and conductors of a high-density integrated circuit.

[0002]

2. Description of the Related Art In semiconductor technology, the circuit density on a chip has increased dramatically, and the fine elements inside and on the surface of a semiconductor substrate have become very close together.
The degree of integration has also significantly increased. Recent developments in lithography techniques, such as phase shift masks and self-alignment processes, have significant effects on device scale-down and increased circuit density, with very large submicron transistors and more than one million transistors. The emergence of integrated circuits has led some circuit elements to face the problem of limited electrical properties due to scale-down.

[0003] One such circuit element is a storage cell on a dynamic random access memory chip, and the storage cell of each dynamic random access memory is typically a metal oxide field effect transistor and a capacitor. And is widely used for storing data in the electronics industry. A single dynamic random access memory stores one bit of data in the form of a charge on a capacitor. Metallization (metallization) for contact with a semiconductor substrate is called contact metallization, and the polysilicon film of a MOS device is metallized to form a gate electrode and an interconnection inside the MOS device. If the metallization and the first layer interconnections (ie the MOS on the substrate) cannot be reduced, the DRAM and other components such as M
It is a major obstacle in scaling down the OS and bipolar devices. It is a serious obstacle that the surface area of the memory decreases and the performance of the cell decreases as the integration density of the dynamic random access memory increases. Therefore, in order to achieve high integration of a semiconductor memory, it is an object of the present invention to solve the problem of forming the miniaturized first layer contacts and the first layer interconnections, and the problem of the reduced cell performance. It becomes.

[0004] The manufacturing process described in the following documents is described. (1) “CVD SiNx Anti-Reflective Coating for Sub-
0.5μm Lithography ”, TPOng et al., 1995 Symposiu
m on VLSI Thechnology Digest of Technicalpaper, (0-
7803-2602-4 / 95) p.73-74. (2) “Selective dry etching in a high density pl
asma for 0.5 complementary metal-oxide-semiconduc
tor thechnology ”, by Givens et al., Vac.Sci. Tech
nol. B12 (1), Jan / Feb 1994, p.427-432. (3) “High Selectivity Silicon Nitride Etch for
Sub-Half Micron Devices ”, by Karen Reinhard et a
l., Lam Reserch Corp., Taiwan Technical Symposium,
November 15, 1994.

[0005]

However, many prior arts require many manufacturing steps or planarization structures, making the steps complicated and costly. Other manufacturing methods have also relied on etching techniques and methods for setting the etching depth in advance, but this type of control has been quite difficult at the manufacturing site. For example, substantial or apparent gas leakage in the plasma etching process, residual vapor due to pump and load effects, etc., change the chemical etching atmosphere in the vacuum chamber, making it difficult to control the etching time. I was Therefore, it has been a problem to provide an etching technique that has a simple manufacturing process and does not require detection of the end point depth.

Accordingly, there is a need to develop interconnections and conductors that reduce manufacturing costs and improve device yield, and in particular, reduce photoresist steps, maximize yields, and maximize There is a need to achieve a limited manufacturing process tolerance. The process of forming a conductor interconnection in a bit line and a contact hole by a conventional manufacturing process requires two steps of photoresist and etching, and the conductor contact and the electrode contact are not self-aligned. The miniaturization was hindered, and the contact hole penetrating the thick insulating film had a high aspect ratio (greater than 3), making it difficult to etch the contact. These are the problems to be solved by the present invention, and there is a need to develop a scaled-down interconnection manufacturing process that can overcome lithography technology.

It is a primary object of the present invention to provide a method for forming interconnections and conductors in high density integrated circuits which overcomes the critical scale of lithography technology and reduces the number of resist steps.

Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit in which high-density contact holes and interconnections are formed.

It is another object of the present invention to provide a method for manufacturing a dynamic random access memory device having a capacitor having a large manufacturing opening which is easy to manufacture at high density, low cost and low cost.

[0010]

SUMMARY OF THE INVENTION In order to solve the above problems and to achieve the above object, the present invention provides a conductor integrated circuit having a high-density first-layer contact and a first-layer interconnection. Providing a method of manufacturing,
This is achieved by the following means. (1) An insulating cap film is formed on the uppermost surface to form a gate electrode having an antireflection function and an interconnection of a first layer. (2) pattern the insulating cap film by high selective silicon nitride etching; (3) First and second layer substrate contacts are formed by self-alignment using the gate electrode and the insulating spacer on the first insulating film.

To explain these means further, a method for forming an interconnection on a semiconductor substrate on which an active region and a wall spacer insulating region are formed is as follows.
It consists of the following steps. That is, a gate electrode provided with a wall spacer is provided in an active region, and a conductive structure is provided on an insulating region. After forming a first insulating cap film made of an anti-reflective silicon nitride film on the uppermost surface of the gate electrode and the conductive structure, a first insulating wall spacer made of silicon nitride is formed on the side wall of the gate electrode and the side wall of the conductive structure. I do. An upper insulating film is formed to cover the first insulating cap film on the gate electrode, and then the first polysilicon film 30, the dielectric film 26 (see FIG. 4) and the second insulating cap film are formed on the substrate. A first opening having a first side wall is formed by patterning and etching the upper portion of the first polysilicon film between the second insulating film, the dielectric film, and the gate electrode using a resist. A second insulating wall spacer is formed on the first side wall of the first opening, and the first opening is filled with the upper electrode plug to form a lower electrode plug, thereby completing an interconnection for electrical connection with the source region.

The manufacturing process of the present invention has many advantages over the prior art. First, the self-alignment process of the present invention is relatively wide utilizing two sets of sidewall spacers. Since the contact opening is realized, it is advantageous for forming the contact hole. Second, since the insulating wall spacer has a small aspect ratio with respect to the contact hole,
Cell formation is less limited by lithographic techniques. Further, since the first and second insulating cap films improve the lithography function by the anti-reflection coating, a further downsized contact hole can be patterned. Third, according to the method of the present invention, the source region and the drain region can be simultaneously patterned by the same resist process, so that the number of resist processes can be reduced. Fourth, dimensional accuracy of contact holes and storage cells can be improved by high selectivity and high density plasma etching.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings. First, an outline of the present invention will be described. The present invention provides a method for forming a reduced interconnection and a method for forming a small-sized, high-performance, and easy-to-manufacture capacitor memory cell. To provide. First, a field oxide film and a field effect transistor structure are formed, but only a brief description will be given to the extent that the understanding of the present invention is assisted. Next, as described later, an interconnection is patterned using two sets of wall spacers and an anti-reflection type silicon nitride cap film.
In addition, the meaning of “the surface of the substrate” refers to the surface of each film or the surface of the structure formed on the semiconductor substrate.

In FIG. 1, first, a transistor element (not shown) is provided in a semiconductor substrate 2, and a capacitor is formed in an active region surrounded by an insulating region 4. This insulating region 4 is a field oxide film. , Semiconductor substrate 2
An active region and an insulating region are formed thereon to separate the active region and the insulating region. A preferred substrate is P-type single crystal silicon having a crystal orientation of (100), and an insulating region 4 which is a sufficiently thick field oxide film is formed around the active region to be electrically isolated. The insulating region 4 is formed by depositing a thick silicon oxide film (oxide pad) and a thicker silicon nitride film as a barrier against oxidation in the active region and performing oxidation after using the mask as a mask.
Desirably, it is 00 °.

After removing the silicon nitride film barrier and the oxide pad by known wet etching, a semiconductor element is formed in the active region. MOSFETs can be used as elements of the most frequently used dynamic random access memory.
First, a thin gate oxide film 3 is formed on the active region by thermal oxidation.
And the thickness is desirably 70 to 90 °.

Conductive film 6 which is a doped polysilicon film
And a gate dielectric film 10 is deposited on the semiconductor substrate 2. The conductive film 6 can be used as a gate electrode and polycide. The gate dielectric film 10 is formed of silicon oxide, and the thickness of the gate dielectric film 10 is reduced. 200 to 10
It can be in the range of 00 °.

Similarly, in FIG. 1, a first insulating cap film 12 is formed on the gate dielectric film 10, and this first insulating cap film 12 has a bonding structure as an upper layer of a gate electrode or as an etching barrier. A first insulating cap film 1 formed of anti-reflection type silicon nitride
It is desirable to improve the resolution of lithography by an anti-reflection function that reduces the reflection due to 2.
The first insulating cap film 12 made of silicon nitride is made of S
LPCVD by iH ₂ Cl ₂ and ammonia reaction
(Decompression chemical vapor deposition), and preferably has a thickness in the range of 200 to 2000 °.
00 is more desirable. The extinction coefficient (k) of the first insulating cap film 12 is in the range of 0.3 to 0.5, and the ratio of SiH ₂ Cl ₂ and ammonia by LPCVD is about 1: 2.
And a range of 1: 4, preferably 1: 3, a reaction pressure of about 100 to 500 × 10 ⁻³ Torr, a pressure of 400 × 10 ⁻³ Torr, and a reaction temperature of 750 to 850 ° C. 780 ° C. is desirable.

The first insulating cap film 12 is also made of TEO
S, the reaction temperature by SiH _4, NH ₃ 750~850
° C and the reaction pressure range is about 100-500 × 10
^-3 Torr as SiOxNy using LPCVD
H can also be deposited. First insulating cap film 1
2 is made of SiOxNyH, its thickness is about 20
The range is 0 to 2000 °.

Next, the gate oxide film 3, the polysilicon film 6, and the gate dielectric film 1 are formed by lithography and etching.
0, the first insulating cap film 12 is formed as a gate electrode and a conductive structure. The outer two conductive structures are connected to the insulating region 4
(Field oxide film) to form a word line, and two inner gate electrodes to be formed on the substrate surface to be a part of a transistor of a DRAM or other element.

A photoresist (not shown) is patterned and etched on the first insulating cap film 12 to form a gate electrode and a conductive structure. Also has high selectivity, the first insulating cap film 12
Used for etching. This highly selective etching includes two steps, main etching and over etching. The main etching pressure is in the range of about 280-320 × 10 ⁻³ Torr, the power is in the range of 250-300 W, and the electrode gap is 0.7.
And the flow rate of SF ₆ is 60 to 80 s.
ccm and the flow rate of CHF ₃ is 9-11 sccm.
And the flow rate of He is in a range of 240 to 260 sccm. In the over-etching step, the pressure is set to about 725 to 755 × 10 ⁻³ Torr, and the power is set to 180.
To 200 W, and the electrode gap is 0.9 to 1.1.
μm, and the flow rate of SF ₆ is 110 to 130 scc.
m, the flow rate of CHF ₃ is in the range of 9-11 sccm, and the flow rate of He is in the range of 18-22 sccm. By this high-selectivity, high-density plasma etching process, the precision of the contact hole can be improved, and a miniaturized interconnection can be formed. The gate dielectric film 10, the conductive film 3, and the gate oxide film 3
The same photomask can be used.

Subsequently, a lightly doped source / drain (not shown) is formed in the N-channel of the MOSFET. N-type ions are implanted. For example, arsenic or phosphorus is added to the conductive film 6 serving as a gate electrode. Inject on both sides,
Form a lightly doped source / drain (not shown). Typical doping uses phosphorus P31,
The dose can be 1E13 to 1E14 atoms / cm ² , and the energy can be 30 to 80 KeV.

In FIG. 2, lightly doped source 1
After the formation of the first, second, and sixth drains 14, the first insulating wall spacers 18 are formed on the side walls of the gate electrodes 3, 6, 10, and 12, respectively.
Is formed by depositing silicon nitride by LPCVD, and has a thickness in the range of 200 to 1000 °.
Desirably, it is 00 °. In addition, the gate electrode 3,
The distance between 6, 10, and 12 is in the range of 0.25 to 0.4 μm, and the distance between the first insulating wall spacers 18 is in the range of 0.2 to 0.35 μm.

The source 16, 16 / drain 14 of the MOSFET is formed by implanting N-type ions, for example, arsenic (As) 75, between the first insulating wall spacers 18, so that the heavily doped sources 16, 16 (source 16 A drain 14 is formed, and this doping step is usually performed through a silicon oxide film having a thickness of 200 to 300 ° to reduce doping to a channel and to reduce metal and other impurities. Pollution is prevented. Typical dose is 2E15-1E16st
oms / cm ^2, and the amount of energy to be implanted is 20 to 7
0 KeV.

As shown in FIG. 3C, an upper insulating film 20 is formed on the upper surfaces of the two middle gate electrodes 3, 6, 10, and 12, and the upper insulating film 20 is formed of two inner gate electrodes. The upper insulating film 2 serves to make the upper surface of the upper insulating film 2 have the same height as the upper surfaces of 3, 6, 10, and 12 and the upper surfaces of the two outer conductive structures 3, 6, 10, and 12 on the insulating region 4 (field oxide film).
0 is preferably in the range of 100 to 1000 ° and formed of silicon oxide.
G and PSG can be used, but it is preferable to use borophosphosilicate glass (BPSG).

In FIG. 3, the upper insulating film 20 is formed by the following steps. As shown in FIG.
After the oxide film 20B is formed by TEOS, the flat film 2
OA covers the entire surface of the substrate. This flat film 20
A is desirably formed of BPSG (borin silicate glass) and has a thickness of 1000 to 5500.
The range of Å. Borosilicate glass is TEO
S (tetraethylorhosilicate) is used as a reactant and formed by low pressure chemical vapor deposition (LPCVD). In the process of forming borophosphosilicate glass, boron and phosphorus are added, and a heat treatment is performed at 850 ° C. for 30 minutes. And reflow to flatten.

3 (b) and 3 (c), the flat film 20A made of BPSG is etched back to reduce its thickness to 3.
It is desirable that the angle be in the range of 500 to 4500 °. Then, a photoresist 21 is patterned on the middle two gate electrodes and the two outer conductive structures to form a flat film 20A.
Then, oxide film 20B is etched to form upper insulating film 20. Also, the upper insulating film 20 may remain on the two outer conductive structures.
0 plays an important role, which is advantageous for achieving planarization and subsequent etching of the polysilicon.

In FIG. 4, on the surface of the semiconductor substrate 2 formed as described above, other film bodies, for example, a second polysilicon film 22, a tungsten silicide film 24, a dielectric film 26, a second insulating cap A film 28 is formed. The second polysilicon film 22 has a thickness of 1000 to 60 after etching.
00 ° is desirable, and 1500 ° is more desirable. The tungsten silicide film 24 is formed on the second polysilicon film 22 to increase the conductivity of the second polysilicon film 22, and is made of SiH ₄ / WF ₆ or SiC.
It is formed by deposition with l ₂ H ₂ / WF ₆ by CVD. The dielectric film 26 preferably has a thickness in the range of 500 to 2000 °, more preferably 1000 °. Then, an oxide process of TEOS, for example, TEOS (tetra
ethylorhosilicate) in a reduced pressure atmosphere at 650-7
It is desirable to form by depositing silicon oxide by chemical vapor deposition at a temperature of 50 ° C. The second insulating cap film 28 is desirably formed of silicon nitride or silicon dioxide, and is formed by depositing an anti-reflection type film by a low pressure chemical vapor deposition method using SiH ₂ Cl ₂ and an ammonia reaction. Cap film 2
8 is in the range of 600 to 1800 °, and the extinction coefficient (k) is in the range of 0.3 to 0.5.

Similarly, in FIG. 4, the second insulating cap film 28 and the dielectric film 26 are selectively etched to cover the source 16 with at least the remaining portion of the second polysilicon film 22. By etching the upper portion of the second polysilicon film 22, a lower electrode plug 30A and a drain contact 30B to the drain 14 are formed. Further, the first opening 3 is simultaneously formed by this etching.
2 and the first side wall 32A (the first opening 3
2 is an interconnection opening). Then, a polysilicon region 30C is formed on the insulating region 4. The second insulating cap film 28 is formed similarly to the first insulating cap film 12 by high-selectivity etching. By this selective etching, an interconnection smaller in size than the conventional silicon nitride manufacturing process can be formed. The dielectric film 26 removes the upper portion of the second polysilicon film 22 covering the source 16 by etching with a known highly selective etching with respect to polysilicon. As a result, the lower electrode plug 30
A is formed, and its thickness is set in the range of 0 to 7000 °.
More preferably, it is set to 000 °.

In FIG. 5, a second insulating wall spacer 34 is formed on the first side wall 32A of the first opening 32. A second insulating film (not shown) is deposited on the surface of the semiconductor substrate 2 of FIG. From anisotropic etching. This second
The insulating wall spacer 34 is formed of silicon oxide by a TEOS process and has a thickness of 200 to 1500 Å.
And 1000 ° is desirable.

In FIG. 6, the upper electrode plug 36 is
The storage electrodes 30A and 36 are formed by filling the opening 32 and connecting to the lower electrode plug 30A. The thickness of the upper electrode plug 36 is in the range of 2000 to 10000 °,
It is desirable to be 7000 °. Upper electrode plug 36
Is formed of doped polysilicon or polycide, such as tungsten silicide,
Impurity concentration of 1E19 to 1E22 atoms / cm ²
And

In FIG. 7, the capacitor dielectric film 38 is formed so as to cover the upper electrode plug 36. The capacitor dielectric film 38 is formed of a material having an arbitrary high dielectric constant, excellent continuity, and no pinhole. Is possible.
This capacitor dielectric film 38 can be formed from silicon nitride, oxide / nitride / oxide (ONO) thin film, silicon oxide or silicon oxide, but is an oxide / nitride / oxide (ONO) thin film. Preferably, the thickness is in the range of 30 to 100 °, and 55 ° is desirable.
Upper electrode plug 3 by carpet type etch back
The capacitor dielectric film 38 between 6 and 36 is removed.

In FIG. 8, an upper electrode film 40 is formed on the capacitor dielectric film 38, and a doped conductive film is deposited and formed on the surface of the semiconductor substrate 2. An appropriately doped polysilicon film is obtained from the doped polysilicon film or the ion-implanted polysilicon film.
A suitable thickness in the range of 500 to 2000, and 1000
Å is desirable. The upper electrode film 40 is desirably polysilicon doped with impurities, and the impurity concentration of the upper electrode film 40 / conductive film is set to 1E19 to 1E22a.
toms / cm ^2, and preferably 1E21 atoms / cm ² .

In FIG. 9, when an upper insulating film 50 and a metal film 52 are formed on the upper electrode film 40, a DRAM cell is completed.

Although the present invention has been disclosed in the preferred embodiments as described above, it is not intended to limit the present invention, but the spirit and scope of the present invention will be understood by those skilled in the art. , Many changes in form and detail can be made,
The scope of the present invention is to be determined based on the claims and the equivalents thereof.

[0035]

According to the structure described above, the method of forming the interconnection and the miniaturized memory cell according to the present invention has many advantages as compared with the prior art. In either case, as shown in FIG.
In addition, a wide process opening is provided by utilizing the two sets of wall spacers 18 and 34 by a self-alignment process, and the insulating wall spacer 34 of the first opening (contact hole) 32 can be formed by etching. The aspect ratio of the hole can be reduced. Second, first opening (contact hole)
Since it is not necessary to use a photoresist and a flat film in forming 32 and it is formed in a self-alignment manner, it is possible to obtain a smaller spectrum ratio by removing the flattened oxide film. Third, since the anti-reflection material is deposited by the special first and second insulating cap films 12 and 28, the lithography performance can be improved and a downsized contact hole can be formed. 4th
In addition, the number of photoresist steps can be reduced,
The lower electrode plug 30 serving as three contacts with the source 16 and the drain 14 by the same three photoresist steps.
A, upper electrode plug 36, drain contact 30B
And can be formed. Fifth, the first opening (contact hole) 32 and the storage electrode 36,
The dimensional accuracy of 30A can be improved. Sixth, first
Since a flat lower surface can be provided by the insulating cap film 20, it is advantageous for the subsequent film formation, and
It also contributes to improving the yield. Therefore, the present invention can improve the integration density and performance of an integrated circuit, reduce the number of steps, reduce the cost by facilitating the manufacturing process, and improve the yield. Is of high use value.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing the formation of a gate electrode according to the present invention.

FIG. 2 is a process sectional view showing the formation of a first insulating wall spacer 18 of the present invention.

FIG. 3 is a process sectional view showing formation of a first insulating cap film 20 according to the present invention.

FIG. 4 is a process cross-sectional view illustrating formation of a first opening 32 according to the present invention.

FIG. 5 is a process sectional view showing the formation of the second insulating wall spacer 34 of the present invention.

FIG. 6 is a process sectional view showing the formation of the lower electrode plug 36 according to the present invention.

FIG. 7 is a process sectional view showing the formation of the capacitor dielectric film 38 according to the present invention.

FIG. 8 is a process sectional view showing the formation of the upper electrode film 40 according to the present invention.

FIG. 9 is a process sectional view showing the completion of the DRAM memory cell according to the present invention.

[Explanation of symbols]

 Reference Signs List 2 semiconductor substrate 3 gate oxide film 4 insulating region (field oxide film) 6 conductive film (first polysilicon film) 10 gate dielectric film 12 first insulating cap film 14 drain 16 source 18 first insulating wall spacer 20 upper insulating film 20A Flat film 20B Oxide film 22 Second polysilicon film 24 Tungsten silicide film 26 Dielectric film 28 Second insulating cap film 30A Lower electrode plug 30B Drain contact 30C Polysilicon region 32 First opening 32A First side wall 34 Second insulating wall Spacer 36 Upper electrode plug 38 Capacitor dielectric film 40 Upper electrode film 50 Upper insulating film 52 Metal film

Claims (14)

[Claims] 1. A method for forming an interconnection on a semiconductor substrate having an insulating region having an active region and a wall spacer, comprising: a) providing a gate electrode in the active region and providing a conductive structure in the insulating region. Forming a first insulating cap film made of an anti-reflection type silicon nitride thin film on the gate electrode and the conductive structure to form an upper surface, and providing a sidewall on the gate electrode and the conductive structure; b) nitriding Providing a first insulating wall spacer of silicon on the gate electrode and sidewalls of the conductive structure; c) forming an upper insulating film to cover the gate electrode having the first insulating cap film; d. A) forming a second polysilicon film, a dielectric film, and a second insulating cap film to form a semiconductor; E) patterning a photoresist and removing the second insulating cap film and a dielectric film between the gate electrode and the conductive structure by a highly selective etching, and e. Forming a first opening having sidewalls and etching an upper portion of a second polysilicon film between the gate electrode and the conductive structure to form a lower electrode plug; f) a second insulating wall spacer Forming on the first side wall of the first opening; g) forming an upper electrode plug to fill the first opening and connect to the lower electrode plug to form the interconnection of the semiconductor substrate. A method for forming interconnections and conductors of a high-density integrated circuit, comprising: 2. The method according to claim 1, wherein the gate electrode and the conductive structure are:
(1) a gate oxide film, (2) a conductive film, (3) a gate dielectric film, and (4) a first insulating cap film, and the first insulating cap film is formed by depositing an anti-reflective silicon nitride. Then, the ratio of SiH ₂ Cl ₂ , which is a reactant by reduced pressure chemical vapor deposition, to ammonia is set to 2 to 4, the pressure is set to 100 to 500 × 10 ⁻³ Torr, and the temperature is set to 750 to 850. ° C, the thickness of the first insulating cap film is in the range of 200 to 2000 °,
2. The method according to claim 1, wherein the extinction coefficient is 0.3 to 0.5 (k). 3. The method according to claim 1, wherein the first insulating cap film is formed of silicon dioxide and covers the silicon nitride film, and the thickness of the silicon nitride film is about 400 to 2000 Å.
And the thickness of the silicon dioxide film is 200 to 1
2. The method for forming interconnections and conductors of a high-density integrated circuit according to claim 1, wherein the thickness is in the range of 000 °. 4. The method according to claim 1, wherein the second insulating cap film is made of silicon nitride having an antireflection coating, and is made of SiH ₂ C.
l ₂ and ammonia as reactants, formed by a reduced pressure chemical vapor deposition method, the thickness of the second insulating cap film is in the range of 600 to 1800 °, and the extinction coefficient is 0.3 to 0.5. 2. The method for forming interconnections and conductors of a high-density integrated circuit according to claim 1, wherein: 5. A method for forming a capacitor on a semiconductor substrate having an insulating region having an active region and a wall spacer, comprising: a) forming a gate oxide film to cover the semiconductor substrate and the insulating region. B) forming a first conductive layer to cover the gate oxide film; c) forming a gate dielectric film to cover the first conductive layer; d) forming a first insulating cap film. Forming and covering said gate dielectric film, wherein said first insulating cap film is formed of anti-reflective silicon nitride; and e) said gate oxide film, said first conductive film and said gate dielectric film. Patterning a film and the first insulating cap film to form a gate electrode covering the active region and a conductive structure covering the insulating region; f) be one of the first insulating wall spacers are formed on sidewalls of the gate electrode and the conductive structure, the first
Forming an insulating wall spacer of silicon nitride; g) implanting impurity ions into the semiconductor substrate using the gate electrode and the first insulating wall spacer as a mask to form a heavily doped source and drain; h. Forming an upper insulating film to cover the first insulating cap film, wherein the first insulating cap film covers the gate electrode, wherein the upper insulating film is formed of silicon dioxide; i) forming a second polysilicon film, a dielectric film, and a second insulating cap film to cover the surface of the semiconductor substrate formed up to the previous step, wherein the second insulating cap film is formed of an anti-reflection type; Forming from silicon nitride; j) the second insulating cap film on the source and the silicon Masking the dielectric film on the source, performing selective etching to form a first opening having a first side wall, and etching an upper portion of the second polysilicon film on the source to form a lower electrode plug. Forming a drain contact connecting to the heavily doped drain; and k) forming a second insulating wall spacer on a first side wall of the first opening, the second insulating wall being formed. Forming a spacer of silicon dioxide; l) forming an upper electrode plug to fill the first opening and form an electrical connection to the lower electrode plug to form an interconnection to the source; m Forming a capacitor dielectric film and an upper electrode film to cover the interconnection to form a capacitor; Interconnection and conductors forming method for high density integrated circuit, characterized by comprising the step of completing fabrication of the memory cell with. 6. The selective etching for the second insulating cap film is a high selective etching for silicon nitride, the high selective etching includes a main etching step and an over etching step, and the pressure in the main etching step is high. From 280 to 320 × 1
0 ^-3 in the range of Torr, a power in the range of 250～300W, the electrode gap in the range of 0.7～0.9Myuemu, the flow rate of SF ₆ in the range of 60～80Sccm,
The flow rate of CHF ₃ is in the range of 9 to 11 sccm, the flow rate of He is in the range of 240 to 260 sccm, and the pressure of the over-etching step is 725 to 755 ×.
The power is in the range of 10 ^-3 Torr and the power is 180 to 200 W
, The electrode gap is in the range of 0.9 to 1.1 μm, the flow rate of SF ₆ is in the range of 110 to 130 sccm, the flow rate of CHF ₃ is in the range of 9 to 11 sccm, and H
6. The method according to claim 1, wherein the flow rate of e is in the range of 18 to 22 sccm. 7. A method of forming an interconnection on a semiconductor substrate having an insulating region having an active region and a wall spacer, comprising: a) forming a gate oxide film to cover the semiconductor substrate and the insulating region. B) forming a first conductive film and covering the gate oxide film; c) forming a gate dielectric film and covering the first conductive film, wherein the gate dielectric film is D) forming a first insulating cap film to cover the gate dielectric film, wherein the first insulating cap film is formed of anti-reflective silicon nitride; A) a gate electrode covering the active region by patterning the gate oxide film, the first conductive film, the gate dielectric film, and the first insulating film; And forming a conductive structure covering the insulating region; f) forming a first insulating wall spacer on the side wall of the gate electrode and the conductive structure, forming the first insulating wall spacer from silicon nitride; Forming a first insulating cap film to cover the surface of the semiconductor substrate and anisotropically etching the first insulating cap film by high-selectivity etching, wherein the high-selectivity etching is a main etching step; And an over-etching step, the pressure in the main etching step is in the range of 280 to 3200 × 10 ⁻³ Torr, the power is in the range of 250 to 300 W, the electrode gap is in the range of 0.7 to 0.9 μm, and the SF is ₆ to 60 ~
The flow rate of CHF ₃ is set to 9 to 11 s in the range of 80 sccm.
ccm range, and the He flow rate is 240 to 260 scc.
m, the pressure of the over-etching step is in the range of 725 to 755 × 10 ⁻³ Torr, the power is in the range of 180 to 200 W, the electrode gap is in the range of 0.9 to 1.1 μm, SF ₆ flow rate 110
And the flow rate of CHF ₃ is 9-1.
The flow rate of He is set to 18 to 22 scc.
m) implanting impurity ions into the semiconductor substrate using the gate electrode and the first insulating wall spacer as a mask to form heavily doped sources and drains; h) upper insulating film Forming the first insulating cap film covering the gate electrode, wherein the upper insulating film is formed of anti-reflective silicon dioxide; and i) a first polysilicon film. And forming a dielectric film and a second insulating cap film to cover the surface of the semiconductor substrate formed up to the previous step, wherein the second insulating cap film is formed of silicon nitride; Masking and selectively etching the second insulating cap film on the source and the dielectric film on the source electrode; Forming a first opening having one side wall, etching the upper portion of the first polysilicon film on the source to form a lower electrode plug, and forming a drain contact to the heavily doped drain; Connecting) k) forming a second insulating wall spacer on the first side wall of the first opening, the second insulating wall spacer being formed of borophosphosilicate glass; and 1) upper electrode plug Filling the first opening to form an electrical connection to the lower electrode plug, and forming an interconnection to the source. Forming method. 8. The method of claim 1, further comprising forming a capacitor dielectric film and an upper electrode film to cover the interconnection, thereby completing the formation of the capacitor and the fabrication of the memory cell. 8. The method for forming interconnections and conductors of a high-density integrated circuit according to claim 7. 9. The high-density integrated circuit according to claim 1, wherein said first polysilicon film has a thickness in a range of about 1000 to 6000 °. Interconnection and conductor formation methods. 10. The first insulating wall spacer is made of silicon nitride and has a thickness of about 200 to 2000 Å.
The method for forming interconnections and conductors of a high-density integrated circuit according to any one of claims 1, 5 and 7, wherein: 11. A method according to claim 1, wherein said dielectric film has a thickness of 500-2.
2,000Å, TEOS (tetra ethylorhosilica)
8. The high-density integrated circuit interposer according to claim 1, comprising silicon nitride formed by a low pressure chemical vapor deposition (LPCVD) process utilizing te). How to form connections and conductors. 12. The method according to claim 1, wherein the first insulating cap film and the second insulating cap film are formed of an anti-reflection type silicon nitride, and the ratio is determined by utilizing a reaction between SiH ₂ Cl ₂ and ammonia. Deposited by low pressure chemical vapor deposition (LPCVD) in the range of 2 to 4;
The reaction pressure is in the range of 100 to 500 × 10 ⁻³ Torr, the reaction temperature is in the range of 750 to 850 ° C., the thickness is in the range of 200 to 2000 °, and the extinction coefficient (k) is 0.3 to 0.5. 8. The method according to claim 5, wherein:
A method for forming interconnections and conductors of the high-density integrated circuit according to the above. 13. The distance between said gate electrodes is 0.25.
8. The method according to claim 1, wherein the distance between the first insulating wall spacers is in a range from 0.2 to 0.35 μm. 9. Of high-density integrated circuits and methods of forming conductors. 14. The method according to claim 1, wherein the upper insulating film is made of borosilicate glass and has a thickness of about 1000
2. The method according to claim 1, wherein the angle is in the range of ５5500 °.
8. The method for forming interconnections and conductors of a high-density integrated circuit according to any one of 5 and 7.