KR100265359B1 - A method for forming storage node in semiconductor memory device - Google Patents
A method for forming storage node in semiconductor memory device Download PDFInfo
- Publication number
- KR100265359B1 KR100265359B1 KR1019970029680A KR19970029680A KR100265359B1 KR 100265359 B1 KR100265359 B1 KR 100265359B1 KR 1019970029680 A KR1019970029680 A KR 1019970029680A KR 19970029680 A KR19970029680 A KR 19970029680A KR 100265359 B1 KR100265359 B1 KR 100265359B1
- Authority
- KR
- South Korea
- Prior art keywords
- storage electrode
- etching
- charge storage
- forming
- oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000003860 storage Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 19
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 235000013399 edible fruits Nutrition 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 3
- 239000011737 fluorine Substances 0.000 claims 3
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 claims 1
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 claims 1
- 239000011259 mixed solution Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 125000006850 spacer group Chemical group 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 메모리 소자의 캐패시터 하부전극인 전하저장 전극 형성 공정에 관한 것이다.BACKGROUND OF THE
반도체 메모리 소자의 집적도가 증가함에 따라 소자의 리프레시(refresh) 특성이 큰 문제로 부각되었으며, 이를 해결하는 하나의 방안으로서 캐패시터의 하부 전극인 전하저장 전극의 높이 증가를 통한 표면적 확보를 통해 정전용량을 증가시키는 기술에 대한 많은 연구·개발이 진행되어 왔다.As the degree of integration of semiconductor memory devices has increased, the refresh characteristics of the devices have emerged as a big problem. As a solution to this problem, the capacitance is increased by securing the surface area by increasing the height of the charge storage electrode, which is the lower electrode of the capacitor. Much research and development has been conducted on increasing technology.
그러나, 이러한 전하저장 전극 높이의 증가는 전하저장 전극이 있는 지역(셀 지역)과 없는 지역(주변회로 지역)간의 단차를 만들어, 후속 금속배선 형성 공정에서 브리지(bridge)를 유발하는 원인으로 작용하며, 이러한 브리지는 소자의 신뢰도 및 수율을 저하시키는 요인이 된다. 때문에, 전하저장 전극의 높이를 증가시켜 정전용량을 확보하는데는 한계가 있다.However, this increase in charge storage electrode height creates a step between the region where the charge storage electrode is located (cell region) and the region where there is no (circuit circuit region), which causes a bridge in subsequent metallization process. This bridge becomes a factor of lowering the reliability and yield of the device. Therefore, there is a limit in securing the capacitance by increasing the height of the charge storage electrode.
본 발명은 단차 유발을 억제하면서 그 표면적을 증가시킬 수 있는 반도체 메모리 소자의 전하저장 전극 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor memory device which can increase the surface area while suppressing step generation.
도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 전하저장 전극 형성 공정도.1A to 1E are diagrams illustrating a process of forming a charge storage electrode according to an exemplary embodiment of the present invention.
도 2a는 도 1c의 주사전자현미경(SEM) 사진.Figure 2a is a scanning electron microscope (SEM) picture of Figure 1c.
도 2b는 도 1d의 주사전자현미경(SEM) 사진.Figure 2b is a scanning electron microscope (SEM) picture of Figure 1d.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 11 : 게이트 산화막10
12 : 게이트 전극 13 : 마스크 산화막12
14 : 스페이서 산화막 15 : 층간절연막14
16 : 산화막 17 : 포토레지스트 패턴16
18 : 전하저장 전극18: charge storage electrode
상기의 기술적 과제를 달성하기 위한 본 발명의 반도체 메모리 소자의 전하저장 전극 형성방법은, 반도체 기판 상에 게이트 절연막과, 그 상부 및 측벽이 절연된 게이트 전극을 형성하는 제1 단계; 상기 제1 단계를 마친 전체 구조 상부에 불순물을 포함하는 제1 산화막 및 불순물을 포함하지 않은 제2 산화막을 차례로 형성하는 제2 단계; 상기 제2 산화막 및 상기 제1 산화막을 선택 식각하여 전하저장 전극 콘택홀을 형성하되, 적어도 상기 제2 산화막의 식각 프로파일이 포지티브 경사를 이루도록 하는 제3 단계: 상기 제1 및 제2 산화막의 식각 선택비를 이용하여 상기 제2 산화막의 등방성 식각을 실시하되, 상기 제2 산화막 하부에 언더컷 영역이 형성되도록 하는 제4 단계; 및 상기 제4 단계를 마친 전체 구조 표면을 따라 전하저장 전극용 전도막을 형성하는 제5 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a charge storage electrode of a semiconductor memory device, the method including: forming a gate insulating film and a gate electrode having an upper sidewall and an insulating side thereof formed on a semiconductor substrate; A second step of sequentially forming a first oxide film including an impurity and a second oxide film not including an impurity on the entire structure after the first step; Selecting and etching the second oxide layer and the first oxide layer to form a charge storage electrode contact hole, wherein at least an etching profile of the second oxide layer forms a positive slope: etching selection of the first and second oxide layers Performing an isotropic etching of the second oxide film using a ratio, wherein an undercut region is formed under the second oxide film; And a fifth step of forming a conductive film for a charge storage electrode along the entire structure surface of the fourth step.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 전하저장 전극 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1E illustrate a process of forming a charge storage electrode according to an exemplary embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따른 전하저장 전극 형성 공정은, 우선 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 게이트 산화막(11)과, 스페이서 절연막(14) 및 마스크 산화막(13)으로 절연된 게이트 전극(12)을 형성한다. 이때, 스페이서 절연막(14) 및 마스크 산화막(13)으로는 TEOS(TetraEthylOthoSilicate)계 산화막, LTO(Low Temperature Oxide), MTO(Medium Temperature Oxide), HTO(High Temperature Oxide) 등의 비도핑 산화막(undoped oxide)을 사용하며, 그 형성 공정은 통상적인 방식에 따른다.In the process of forming a charge storage electrode according to the present embodiment, first, as shown in FIG. 1A, a gate electrode insulated from the
다음으로, 도 1b에 도시된 바와 같이 소정의 층간절연막(15) 및 산화막(16)을 차례로 증착하고, 그 상부에 전하저장 전극 콘택홀 형성을 위한 포토레지스트 패턴(17)을 형성한다. 이때 층간절연막(15)으로 BSG(Boro Silicate Glass)막, PSG(Phospho Silicate Glass)막, BPSG(BoroPhospho Silicate Glass)막 등의 도핑 산화막(doped oxide)을 사용하며, 산화막(16)으로서 비도핑 산화막을 사용한다.Next, as shown in FIG. 1B, a predetermined
계속하여, 도 1c에 도시된 바와 같이 포토레지스트 패턴(17)을 식각 장벽으로 하여 산화막(16) 및 층간절연막(15)을 건식 식각함으로써 일차적인 전하저장 전극 콘택홀을 형성하고, 포토레지스트 패턴(17)을 제거한다.Subsequently, as shown in FIG. 1C, dry etching of the
이때, 건식 식각은 하부의 게이트 전극(12)과 콘택간의 단락(short)을 방지할 수 있도록 콘택홀과 게이트 전극(12)과의 중첩 정확도(overlay accuracy)까지 고려하여 최종적인 CD(Critical Dimension)가 작아지도록 즉, DICD(Develop Inspection Critical Dimension)와 FICD(Final Inspection Critical Dimension)의 비가 2 : 1 이상이 되도록 경사 정도를 크게 한다.In this case, dry etching may be performed in consideration of an overlay accuracy between the contact hole and the
이러한 경사 식각 방식의 세부 공정 조건을 살펴보면, 가열 실리콘 루프(heated silicon roof)가 장착된 ICP(Induced coupled plasma) 방식의 고밀도 플라즈마 방식의 건식 식각 챔버를 사용하며, C3F8가스 및 CO 가스를 사용하되, 총 가스유량을 30∼150 sccm으로 하고, C3F8가스와 CO 가스의 유량비를 1 : 0.5∼5로 한다. 여기서 C3F8가스는 CF4, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2가스 등의 CF 계열 가스로 대체하여 사용할 수 있다. 또한 220℃∼290℃ 범위의 실리콘 루프 온도와, 1600 W∼2800 W 범위의 ICP RF 전력 및 600 W∼1800 W 범위의 바이어스(bias) RF 전력을 사용한다. 또한, 경사 식각은 NF3가스와 같이 F기를 포함하는 가스를 주 반응 가스로 하는 플라즈마 식각 방식을 사용할 수도 있으며, NH3가스를 주 반응 가스로 하는 플라즈마 식각 방식을 사용할 수도 있다. 도 2a에 경사 식각 후의 전자 현미경 사진을 도시하였다.The detailed process conditions of the inclined etching method include a dry etch chamber of a high density plasma method of an induced coupled plasma (ICP) method equipped with a heated silicon roof, and a C 3 F 8 gas and a CO gas. The total gas flow rate is 30 to 150 sccm, and the flow rate ratio of C 3 F 8 gas and CO gas is 1: 0.5 to 5. The C 3 F 8 gas may be replaced with CF-based gas such as CF 4 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , CH 2 F 2 gas. Silicon loop temperatures in the range 220 ° C. to 290 ° C., ICP RF power in the 1600 W to 2800 W range and bias RF power in the 600 W to 1800 W range are also used. In addition, the gradient etching may use a plasma etching method using a gas containing F group as a main reaction gas, such as NF 3 gas, or may use a plasma etching method using NH 3 gas as a main reaction gas. 2A shows an electron micrograph after oblique etching.
이어서, 도 1d에 도시된 바와 같이 산화막(16), 마스크 산화막(13) 및 스페이서 절연막(14)에 대한 층간절연막(10)의 높은 식각 선택비를 갖는 등방성 식각 공정을 실시한다. 이때 등방성 식각은 인산(H3PO4)을 주 식각제로 하고, NH4OH와 과수 및 순수의 혼합비를 적절히 조절하여 사용할 수 있다. 그리고 통상적인 건식 식각 및 습식 세정 공정을 진행할 수도 있다. 도 2b에 등방성 식각 후의 전자 현미경 사진을 도시하였다.Next, as shown in FIG. 1D, an isotropic etching process having a high etching selectivity of the
다음으로, 도 1e에 도시된 바와 같이 폴리실리콘막, 금속산화물 등의 전도막을 증착하고, 전하저장 전극 형성을 위한 마스크를 사용하여 전도막을 선택 식각함으로써 전하저장 전극(18)을 디파인한다.Next, as illustrated in FIG. 1E, a conductive film such as a polysilicon film or a metal oxide is deposited, and the
상기한 실시예에 나타난 바와 같이 본 발명은 경사 식각 공정 및 도핑 산화막과 및 비도핑 산화막의 높은 식각 선택비를 갖는 등방성 식각 공정을 실시하여 자기정렬 콘택을 이루며, 전하저장 전극에 의한 단차를 높이지 않으면서 충분한 전하저장 전극의 표면적을 확보할 수 있다.As shown in the above embodiment, the present invention forms a self-aligned contact by performing an inclined etching process and an isotropic etching process having a high etching selectivity of the doped oxide film and the undoped oxide film, thereby increasing the step by the charge storage electrode. It is possible to secure a sufficient surface area of the charge storage electrode without.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 비교적 간단한 공정을 통해 단차를 유발하지 않으면서 큰 정전용량을 가지는 캐패시터를 제조할 수 있으며, 통상적으로 사용되는 질화막 식각장벽을 이용한 자기 정렬 콘택홀 공정보다 용이하게 자기 정렬 효과를 얻을 수 있다.As described above, the present invention can manufacture a capacitor having a large capacitance without causing a step through a relatively simple process, and the self-aligning effect is easier than a self-aligned contact hole process using a nitride film etching barrier that is commonly used. Can be obtained.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029680A KR100265359B1 (en) | 1997-06-30 | 1997-06-30 | A method for forming storage node in semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029680A KR100265359B1 (en) | 1997-06-30 | 1997-06-30 | A method for forming storage node in semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990005482A KR19990005482A (en) | 1999-01-25 |
| KR100265359B1 true KR100265359B1 (en) | 2000-10-02 |
Family
ID=19512634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970029680A KR100265359B1 (en) | 1997-06-30 | 1997-06-30 | A method for forming storage node in semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100265359B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100507863B1 (en) * | 1998-06-30 | 2005-11-16 | 주식회사 하이닉스반도체 | Method for forming contact hole in semiconductor device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4070919B2 (en) * | 1999-01-22 | 2008-04-02 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| KR100403328B1 (en) * | 1999-11-03 | 2003-10-30 | 주식회사 하이닉스반도체 | Forming method for self aligned contact of semiconductor device |
| KR100604555B1 (en) * | 2001-06-21 | 2006-07-28 | 주식회사 하이닉스반도체 | Method of forming a capacitor in a semiconductor device |
| KR100603929B1 (en) * | 2002-03-04 | 2006-07-24 | 삼성전자주식회사 | Cylindrical capacitors having a stepped sidewall and methods for fabricating the same |
| KR100753122B1 (en) * | 2002-06-29 | 2007-08-29 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03174767A (en) * | 1989-09-13 | 1991-07-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor memory device |
| JPH05283643A (en) * | 1992-03-31 | 1993-10-29 | Sanyo Electric Co Ltd | Manufacture of semiconductor element |
-
1997
- 1997-06-30 KR KR1019970029680A patent/KR100265359B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03174767A (en) * | 1989-09-13 | 1991-07-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor memory device |
| JPH05283643A (en) * | 1992-03-31 | 1993-10-29 | Sanyo Electric Co Ltd | Manufacture of semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100507863B1 (en) * | 1998-06-30 | 2005-11-16 | 주식회사 하이닉스반도체 | Method for forming contact hole in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990005482A (en) | 1999-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100553839B1 (en) | Capacitor, Method for manufacturing the capacitor, Semiconductor device including the capacitor, and Method for manufacturing the semiconductor device | |
| JP2765478B2 (en) | Semiconductor device and manufacturing method thereof | |
| US7875547B2 (en) | Contact hole structures and contact structures and fabrication methods thereof | |
| US6432765B1 (en) | Funnel shaped structure in polysilicon and method of making | |
| US6093943A (en) | Semiconductor device and method of producing the same | |
| KR100360739B1 (en) | Dram capacitor strap | |
| KR100302930B1 (en) | etching method | |
| US5668039A (en) | Method for forming crown-shape capacitor node with tapered etching | |
| US6083845A (en) | Etching method | |
| KR100265359B1 (en) | A method for forming storage node in semiconductor memory device | |
| KR100252039B1 (en) | Method for forming a self-aligned contact hole | |
| KR100536042B1 (en) | Method for forming recess gate electrode in semiconductor process | |
| KR100513051B1 (en) | Method for forming gate electrode of semiconductor device_ | |
| US6238970B1 (en) | Method for fabricating a DRAM cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern | |
| KR100458296B1 (en) | Method for forming contact hole of semiconductor device to easily form self-aligned contact pattern and enlarge desired plug size | |
| KR100691484B1 (en) | Method for fabricating plug in semiconductor device | |
| KR100507863B1 (en) | Method for forming contact hole in semiconductor device | |
| KR100652361B1 (en) | Method for fabricating a semiconductor device using self aligned contact | |
| KR100681209B1 (en) | Method for forming a deep contact hole in semiconductor device | |
| KR19990005143A (en) | Contact hole formation method of semiconductor device | |
| KR100695417B1 (en) | Method for fabrication of semiconductor device capable of forming fine pattern | |
| KR19990021371A (en) | Method of manufacturing fine contact of semiconductor device | |
| JP2652985B2 (en) | Method for manufacturing semiconductor memory device | |
| KR20040007112A (en) | Method for forming plug of semiconductor device | |
| KR19990021368A (en) | Method of manufacturing fine contact of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080527 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |