JP2652985B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a U-shaped capacitor electrode made of polycrystalline silicon in a dynamic random access memory (hereinafter referred to as DRAM). To a method of forming

[Conventional technology]

Conventionally, when forming a polycrystalline silicon capacitor electrode of a DRAM, a polycrystalline silicon film is grown over the entire surface and then patterned by photolithography.

In recent years, along with the large-scale integration of DRAM, a device for increasing the surface area of a polycrystalline silicon capacitor electrode has been devised for the purpose of securing a capacity. As a method of increasing the surface area, a method of forming a three-dimensional electrode structure is being studied. As a method of forming a three-dimensional capacitor electrode, a method of forming a trench in a substrate and using the side wall as an electrode (trench capacity)
And a method of stacking a polycrystalline silicon film for an electrode in the upward direction of the device (stack capacitance).

[Problems to be solved by the invention]

Stack capacitance is advantageous in that processing on the substrate is not required, but in order to form a stack capacitance electrode,
It is necessary to grow a polycrystalline silicon film in a state where the element is formed and the surface flatness is reduced, and then pattern the polycrystalline silicon film. Therefore, the patterning of the polycrystalline silicon film has the following problems.

First, in a lithography process, an increase in surface steps causes a shift in focus between an upper portion and a lower portion of the steps, making it difficult to pattern fine dimensions.

Second, during etching of the polycrystalline silicon film, an etching residue occurs in a portion with a large step, causing a problem that an electrode is short-circuited, lowering the yield, and further performing over-etching or etching performed to suppress this short-circuit. The isotropic etching causes a side etching of the polycrystalline silicon film during the etching, thereby impairing the continuity of the wiring, thereby lowering the yield as described above.

An object of the present invention is to solve these problems and to provide a method of forming a U-shaped capacitor electrode which is less affected by surface irregularities among stack capacitors.

[Means for solving the problem]

According to the method of manufacturing a semiconductor memory device of the present invention, a step of forming a first interlayer oxide film having a required thickness on a semiconductor substrate on which a semiconductor memory element is formed and a step of forming an electrode of the first interlayer oxide film Forming a groove exposing the surface of the semiconductor substrate, forming a first polycrystalline silicon film in a region including the groove, and forming a second interlayer oxide film on the surface of the first polycrystalline silicon film Forming a second layer having a higher etching rate than that of the first polycrystalline silicon film so as to be buried in a recess formed in the first polycrystalline silicon film on the second interlayer oxide film. A step of forming a polycrystalline silicon film, and etching back the second polycrystalline silicon film, the second interlayer oxide film, and the first polycrystalline silicon film to form a groove in the groove of the first interlayer oxide film. Only these second polycrystalline silicon films, Leaving a second polycrystalline silicon film and a second polycrystalline silicon film in the groove, selectively etching and removing the second polycrystalline silicon film and the second polycrystalline silicon film in the trench; Removing the oxide film.

In this case, an insulating film is formed on a semiconductor substrate on which a semiconductor memory element is to be formed, an opening is provided in the insulating film to expose the semiconductor substrate, and a base polycrystalline silicon film is formed in a region including the opening. Selectively forming, and
Then, the above steps may be performed.

[Action]

According to the method of the present invention, the formed capacitor electrode is configured to extend in a U-shape toward the upper side of the semiconductor substrate, and it is possible to obtain a large electrode area as compared with the occupied plane area to increase the capacity. It becomes possible.

In the method of the present invention, a polycrystalline silicon film is buried in a groove of the thick first interlayer oxide film provided on the semiconductor substrate,
In addition, since this is an etching back method, even if the surface of the semiconductor substrate has irregularities, it is hardly affected by the irregularities in processes such as film formation, patterning and etching.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1I are sectional views for explaining a first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1 (a), after an element isolation oxide film 2 is formed on a silicon substrate 1 by a selective oxidation method (LOCOS), a gate polycrystalline silicon film 3 doped with phosphorus and having a thickness of 2500.degree.
Is grown, and an oxide film 4 is formed by a CVD (Chemical Vapor Deposition) method, and these films are patterned by a RIE (Reactive Ion Etching) method to form a gate with a polycrystalline silicon film.

Next, as shown in FIG.
The oxide film 5 of 成膜 is formed, and this etching back is performed by RIE to leave it as a sidewall on the side surface of the gate. Hereinafter, the oxide films 4 and 5 are shown as a representative example of the oxide film 5.

Next, as shown in FIG.
A first interlayer oxide film 6 having a film thickness of 12000 ° corresponding to the height of the V-shaped capacitance electrode and doped with boron and phosphorus is formed on the entire surface;
Reflow by heat treatment. Thereafter, as shown in FIG. 1 (d), a portion of the first interlayer oxide film 6 where an electrode is to be formed is selectively etched and removed by a lithography process and an RIE process to form a groove 7 for exposing the surface of the silicon substrate 1. Form.

Next, as shown in FIG. 1 (e), a first polycrystalline silicon film 8 having a thickness of 2000 .ANG.
Is oxidized in an oxidizing atmosphere to grow a second interlayer oxide film 9 having a thickness of about 200.degree.

Then, as shown in FIG. 1 (f), a second polycrystalline silicon film 10 doped with phosphorus over the entire surface including the concave portion formed in the first polycrystalline silicon film 8 in the trench 7 is formed to a thickness of 5000 .ANG.
Grow to a degree. Thereby, trench 7 formed in first interlayer oxide film 6 is completely buried with these polycrystalline silicon films.

Next, as shown in FIG. 1 (g), the second polycrystalline silicon film 10 doped with phosphorus is etched by RIE using chlorine gas or a mixed gas containing chlorine as a constituent element. Here, RIE excited by high-frequency power 13.56 MH ₂ was used, using chlorine (Cl ₂ ) as a reaction gas. As etching conditions, the flow rate of Cl ₂ was 20 cc / min, and the pressure was 400 T.
set to orr. Here, input 200W high frequency power,
Etching was performed for 5 minutes. The etching rate obtained at this time is 1500 ° / min for the phosphorus-doped polycrystalline silicon film.

Subsequent to this etching step, the second interlayer oxide film 9 is etched, and further the first polycrystalline silicon film 8 is etched. The etching of the second interlayer oxide film 9
This is performed by wet etching using diluted hydrofluoric acid (HF). For the etching of the first polycrystalline silicon film 8, sulfur hexafluoride (SF ₆ ) is used as a reaction gas, and high frequency power 13.
Using RIE excited by 56MH _z. As the etching conditions, the flow rate of SF ₆ to 50 cc / min, the pressure was set to 200 mTorr. Here, 300 W of high frequency power was input, and etching was performed for 1 minute. The etching rate obtained at this time was 3500 ° / min. As a result, the first polysilicon film 8 is left in a U-shape in the groove 7 of the first interlayer oxide film 6, and the second interlayer oxide film is formed in the concave portion of the first polysilicon film 8. 9 and a part of the second polycrystalline silicon film 10 are left.

Next, as shown in FIG. 1 (h), an RIE method using chlorine gas or a mixed gas containing chlorine as a constituent element,
Using chlorine (Cl ₂ ) as reaction gas, high frequency power 13.56MHZ
Etching back of the second polycrystalline silicon film 10 is performed using RIE excited by _z . As etching conditions, the flow rate of Cl ₂ was set to 20 cc / min, and the pressure was set to 400 mTorr. Here, high-frequency power of 200 W was input and etching was performed for 5 minutes. The etching rate obtained at this time is
A non-doped polycrystalline silicon film gives 300 ° / min, a phosphorus-doped polycrystalline silicon film gives 1500 ° / min, and a selectivity of 5 is obtained. By this etching back step, the second polycrystalline silicon film 10 existing in the first polycrystalline silicon film 8 is selectively removed.

Next, as shown in FIG. 1 (i), the first interlayer oxide film 6 is etched by about 8000 ° by wet etching using diluted hydrofluoric acid to form a first polycrystalline silicon film. 8 is exposed. By this etching back step, a U-shaped polycrystalline silicon electrode 8A composed of the first polycrystalline silicon film 8 is obtained, and a capacitor electrode is formed by vapor diffusion of phosphorus to this electrode.

Thereafter, a capacitor is formed by growing a dielectric film and forming a counter electrode, but the description is omitted.

The capacitor electrode 8A formed in this manner is connected to the silicon substrate 1
, A large electrode area can be obtained compared to the occupied plane area, and the capacitance can be increased. In forming this capacitor electrode, a groove 7 is formed in the thick first interlayer oxide film 6 provided on the silicon substrate 1 and polycrystalline silicon films 8 and 10 are formed in the groove 7. Because
Even when the surface of the silicon substrate 1 has irregularities, it is hardly affected by the irregularities, enables fine patterning, and does not cause problems such as residual etching and over-etching.

2 (a) to 2 (g) are sectional views for explaining a second embodiment of the present invention in the order of steps. The same parts as those in the first embodiment are denoted by the same reference numerals.

First, as shown in FIG. 2A, an element isolation oxide film 2 is formed on a silicon substrate 1 by a selective oxidation method,
A phosphorus-added polycrystalline silicon film 3 and an oxide film 4 are formed with a thickness of 00 °, and these films are patterned by RIE to form a gate. Then, an oxide film 5 'having a thickness of 2000 ° is formed thereon by the CVD method.

Next, as shown in FIG. 2 (b), a resist mask 11 having an opening 12 at a portion where the electrode is connected is formed, and the oxide film 5 'is etched by RIE using this. As a result, the surface of the silicon substrate 1 is exposed at the electrode connection portion of the oxide film 5 '.

Next, as shown in FIG. 2 (c), a non-doped underlying polycrystalline silicon film 13 is formed to a thickness of 2000.degree., And a resist mask 14 is formed to cover a region including an electrode connection portion. The underlying polycrystalline silicon film 13 is etched by the method.

Next, as shown in FIG. 2 (d), after removing the resist mask 14, a boron- and phosphorus-containing first film having a film thickness of 12000 ° corresponding to the thickness of the U-shaped electrode to be formed is added.
An interlayer oxide film 6 is formed, and heat treatment for reflow is performed.

Thereafter, as shown in FIG. 2 (e), a groove 7 is formed in the first interlayer oxide film 6 by the same process as in the first embodiment, and a first polysilicon layer having a thickness of 2000 .ANG. A polycrystalline silicon film 8 is grown, and the polycrystalline silicon film 8 is oxidized in an oxidizing atmosphere at 900 ° C. to form a second interlayer oxide film 9 having a thickness of about 200 °, and a second polycrystalline silicon doped with phosphorus. The film 10 is formed on the entire surface of the first polycrystalline silicon film 8 including the recesses.
Grow about 5000Å.

Next, as shown in FIG. 2 (f), the second polycrystalline silicon layer 10 doped with phosphorus is etched back. here,
Using chlorine (Cl ₂ ) as reaction gas, high frequency power 13.56MHZ
_The RIE method excited by _z was used. As the etching conditions, the flow rate of Cl ₂ was set at 20 cc / min, and the pressure was set at 400 mTorr. Here, high-frequency power of 200 W was input and etching was performed for 5 minutes. The etching rate obtained at this time is 1500 ° / min for the phosphorus-doped polycrystalline silicon film. Next, the second interlayer oxide film 9 is etched, and subsequently, the first polycrystalline silicon film 8 is etched back. The etching of the second interlayer oxide film 9 is performed by wet etching using dilute hydrofluoric acid (HF). First
For the etching back of the polycrystalline silicon film 8, sulfur hexafluoride (SF ₆ ) was used as a reaction gas,
To use the RIE method, which is excited by the MH _z. As the etching conditions, the flow rate of SF ₆ to 50 cc / min, the pressure was set to 200 mTorr. Here, 300 W of high frequency power was input, and etching was performed for 1 minute. The etching rate obtained at this time was 3500 ° / min.

Next, as shown in FIG. 2 (g), a second polycrystalline silicon film buried in the concave portion of the first polycrystalline silicon film 8 is formed.
10 and the first interlayer oxide film 9 are removed by etching. At this time, in order to etch back the second polycrystalline silicon film 10 doped with phosphorus with respect to the first non-doped polycrystalline silicon film 8 at a high rate, a chlorine gas or a mixed gas containing chlorine as a constituent element is used. The RIE method used is used. here,
Using chlorine (Cl ₂ ) as reaction gas, high frequency power 13.56MHZ
_The RIE method excited by _z was used. As the etching conditions, the flow rate of Cl ₂ was set at 20 cc / min, and the pressure was set at 400 mTorr. Here, high-frequency power of 200 W was input and etching was performed for 5 minutes. The etching rate obtained at this time is
300 ° / min for the first non-doped polycrystalline silicon film 8,
In the second phosphorus-doped polycrystalline silicon film 10, 1500 ° / min is obtained, and a selectivity of 5 is obtained. Thereafter, the first interlayer oxide film 6 is formed by wet etching using diluted hydrofluoric acid.
Etching is performed at about 8000 ° for the film thickness of 12000 ° to expose the first polycrystalline silicon film 8 and the underlying polycrystalline silicon film 13. As a result, a U-shaped polycrystalline silicon film electrode 8A composed of the first polycrystalline silicon film 8 is obtained. By performing the diffusion, a capacitor electrode is formed.

In this embodiment, the same effect as that of the first embodiment can be obtained, but in this embodiment, the U-shaped electrode
In addition to 8A, since the electrode 13A made of the underlying polycrystalline silicon film is formed in a wing shape, it is possible to use this wing portion also as a capacitor electrode, and by combining these electrodes 8A and 13A, A large capacity can be obtained.

〔The invention's effect〕

As described above, according to the present invention, the first polycrystalline silicon film is formed in the groove formed in the first interlayer oxide film, and the second polycrystalline silicon film is formed on the surface thereof. By forming a crystalline silicon film and sequentially removing the first and second polycrystalline silicon films and the second interlayer oxide film by etching, a U-shaped capacitor electrode is formed from the first polycrystalline silicon film. can do.

Since the capacitor electrode thus formed has a configuration extending in a U-shape toward the upper side of the semiconductor substrate, a large electrode area can be obtained as compared with the occupied plane area, and the capacitance is increased. be able to.

In forming the capacitor electrode, a method is used in which a polycrystalline silicon film is buried in a groove of a thick first interlayer oxide film provided on the semiconductor substrate and the polycrystalline silicon film is etched back. Even if the surface has irregularities, it is hardly affected by the irregularities in the steps of film formation, patterning, etching, etc., and enables fine patterning, and causes problems due to residual etching and over-etching. There is no.

[Brief description of the drawings]

FIGS. 1A to 1I are cross-sectional views showing a first embodiment of the present invention in the order of steps, and FIGS. 2A to 2G are cross-sectional views showing a second embodiment of the present invention in the order of steps. is there. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation oxide film, 3 ... Gate polycrystalline silicon film, 4, 5, 5 '... Oxide film, 6 ... First interlayer oxide film, 7 ... Groove, 8 ... first polycrystalline silicon film, 8A ... U-shaped electrode, 9 ... second interlayer oxide film, 10
... Second polycrystalline silicon film, 11 resist mask,
12 ... window, 13 ... underlying polycrystalline silicon film, 13 A ... electrode, 14 ... resist mask.

Claims (2)

(57) [Claims] A step of forming a first interlayer oxide film of a required thickness on a semiconductor substrate on which a semiconductor memory element is to be formed, and a step of forming a surface of the semiconductor substrate at a position where an electrode of the first interlayer oxide film is to be formed. Forming a groove to be exposed, forming a first polysilicon film in a region including the groove, and forming a second interlayer oxide film on the surface of the first polysilicon film. A second polycrystalline silicon film having a higher etching rate than the first polycrystalline silicon film so as to be buried in a recess formed in the first polycrystalline silicon film on the second interlayer oxide film And etching back the second polysilicon film, the second interlayer oxide film, and the first polysilicon film to form the second polysilicon film only in the groove of the first interlayer oxide film. A polycrystalline silicon film, a second interlayer oxide film, And a step of leaving the first polycrystalline silicon film, a step of selectively etching and removing the second polycrystalline silicon film and the second interlayer oxide film in the groove, and removing the first interlayer oxide film. And a method for manufacturing a semiconductor memory device. A step of forming an insulating film on a semiconductor substrate on which a semiconductor memory element is to be formed, providing an opening in the insulating film to expose the semiconductor substrate, and forming a base polycrystalline silicon film in a region including the opening. Selectively forming, forming a first interlayer oxide film having a required thickness, and forming a groove for exposing the underlying polycrystalline silicon film at a position of the first interlayer oxide film where an electrode is to be formed. Process and a first step on the entire surface including the groove.
Forming a second polysilicon film on the surface of the first polysilicon film, forming a second interlayer oxide film on the surface of the first polysilicon film, and forming the first polysilicon film on the second interlayer oxide film. Forming a second polycrystalline silicon film having an etching rate higher than that of the first polycrystalline silicon film so as to be buried in a concave portion formed in the film; Etching back the interlayer oxide film and the first polycrystalline silicon film to form the second polycrystalline silicon film, the second interlayer oxide film, and the first polycrystalline silicon film only in the grooves of the first interlayer oxide film. A step of leaving the polycrystalline silicon film, a step of selectively etching and removing the second polycrystalline silicon film and the second interlayer oxide film in the trench, and a step of removing the first interlayer oxide film. A method for manufacturing a semiconductor memory device, comprising: