JPH04167465A - Semiconductor memory device production method - Google Patents

Abstract

PURPOSE:To increase capacity by forming a polycrystalline silicon film, interlayer oxide film, and polycrystalline silicon film in the channel formed on the interlayer oxide film and then etching and removing the latter two films, while forming a U-shaped capacity electrode of the first film. CONSTITUTION:An interlayer oxide film 6 is formed on a semiconductor substrate 1 to a certain height and in the place for this layer's electrode, a channel 7 is formed which exposes the surface of the semiconductor substrate 1. After that, a polycrystalline silicon film 8 is formed over the entire region including the channel 7, an interlayer oxide film 9 is formed on this surface, and a polycrystalline silicon film 10 is formed to fill the recess portion created in the polycrystalline silicon film 8. The polycrystalline silicon film 10, interlayer oxide film 9, and polycrystalline silicon film are then etched back and only left in the channel on interlayer oxide film 6. After the polycrystalline silicon film 10 and interlayer oxide film 9 remaining in the channel are selectively etched, the interlayer oxide film 6 is removed. The resulting capacity electrode 8A is U-shaped and since the electrode area is large compared to the occupied surface area capacity can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor memory device, and particularly to a U-shaped capacitor electrode made of polycrystalline silicon in a dynamic random access memory (hereinafter referred to as DRAM). Concerning how to form.

[Conventional technology]

When forming the polycrystalline silicon capacitor electrode of DRAM,
Conventionally, this is done by growing a polycrystalline silicon film over the entire surface and then patterning it using photolithography technology.

In recent years, with the large-scale integration of DRAMs, efforts have been made to increase the surface area of polycrystalline silicon capacitor electrodes in order to secure capacity. As a method to increase the surface area, a method of making the electrode structure three-dimensional is being considered, and one method of making the capacitor electrode three-dimensional is to form a trench in the substrate.
Method of using the sidewall as an electrode (trench capacitance)
A method (stack capacitance) in which polycrystalline silicon films for electrodes are stacked above the element is used.

[Problem to be solved by the invention]

Stacked capacitance is advantageous in that no processing is required on the substrate, but in order to form stacked capacitance electrodes, a polycrystalline silicon film is grown with the element formed and the surface flatness reduced. Thereafter, it is necessary to pattern this polycrystalline silicon film. For this reason, the following problems arise in patterning this polycrystalline silicon film.

Firstly, in the process of glazing, an increase in the surface level difference causes a focus shift between the upper and lower parts of the level difference, making it difficult to pattern with minute dimensions.

Second, when etching a polycrystalline silicon film, etching remains are created in areas with large steps, causing problems such as shorting of the electrodes, which lowers the yield. Due to over-etching or isotropic etching, side etching occurs in the polycrystalline silicon film during etching, which impairs conductivity of wiring, resulting in the same problem of lowering yield as described above.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a method for forming a U-shaped capacitor electrode that is less affected by surface irregularities among stack capacitors.

[Means to solve the problem]

The method for manufacturing a semiconductor memory device of the present invention includes a step of forming a first interlayer oxide film of a required thickness on a semiconductor substrate forming a semiconductor memory element, and a step of forming an electrode of the first interlayer oxide film. A step of forming a groove exposing the surface of the semiconductor substrate, a step of forming a first polycrystalline silicon film in a region including the groove, and a step of forming a second interlayer oxide film on the surface of the first polycrystalline silicon film. forming a second polycrystalline silicon film on the second interlayer oxide film so as to be buried in the recess formed in the first polycrystalline silicon film; a polycrystalline silicon film, a second interlayer oxide film,
and a step of etching back the first polycrystalline silicon film to leave the polycrystalline silicon film etc. only in the groove of the first interlayer oxide film; The method includes the steps of selectively etching and removing the interlayer oxide film, and removing the first interlayer oxide film.

In this case, an insulating film is formed on a semiconductor substrate forming a semiconductor memory element, an opening is formed in this insulating film to expose the semiconductor substrate, and a base polycrystalline silicon film is formed in a region including this opening. The process may also include a process of selectively forming, and then performing the above-described process.

[Function] According to the method of the present invention, the formed capacitor electrode has a U-shaped configuration extending upward from the semiconductor substrate, and the electrode area is larger than the planar area it occupies, increasing the capacitance. It becomes possible to achieve this goal.

Further, in the method of the present invention, a thick first layer provided on a semiconductor substrate is used.
This method embeds a polycrystalline silicon film in the groove of the interlayer oxide film and etches it back, so even if the surface of the semiconductor substrate is uneven, the film formation and
Processes such as patterning and etching are hardly affected by the unevenness.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(i) are cross-sectional views for explaining the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), an element isolation oxide film 2 is formed on a silicon substrate 1 by a selective oxidation method (LOCO3), and then a gate polycrystalline silicon WIt3 doped with phosphorus is grown to a thickness of 2500 nm. Further, an oxide film 4 is formed by CvD (chemical vapor deposition), and these films are subjected to RIE.
(reactive ion etching) method,
A gate is formed from a polycrystalline silicon film.

Next, as shown in Figure 1(b), a thickness of 20mm
An oxide film 5 of 0.00% is formed and etched back by RIE to leave it as a sidewall on the side surface of the gate. Hereinafter, the oxide films 4 and 5 will be illustrated as an oxide film 5 as a representative.

Next, as shown in FIG. 1(C), a first interlayer oxide film 6 doped with boron and phosphorus is formed on the entire surface to a thickness of 12,000 people, which corresponds to the height of the U-shaped capacitor electrode to be formed. Then, it is reflowed by heat treatment.

Thereafter, as shown in FIG. 1(d), the first interlayer oxidation WI1.6 in the portion where the electrode is to be formed is selectively etched away by a lithography process and an RIE process, and the groove 7 exposing the surface of the silicon substrate 1 is removed. form.

Next, as shown in FIG. 1(e), a first polycrystalline silicon film 8 not added with impurities is grown to a thickness of 2000 m on the entire surface including the groove 7, and this polycrystalline silicon film 8 is further grown to a thickness of 90 mn.
It is oxidized in an oxidizing atmosphere at 0°C to form a 200mm thick layer on its surface.
A second interlayer oxide film 9 for preventing the diffusion of variable impurities is grown.

Next, as shown in FIG. 1(f), a second polycrystalline silicon rpj! doped with phosphorus is applied to the entire surface of the groove 7, including the recess formed in the first polycrystalline silicon film 8. 10 to a thickness of about 5,000 people. As a result, the groove 7 formed in the first interlayer oxide film 6 is completely filled with these polycrystalline silicon films.

Next, as shown in FIG. 1(g), a second polycrystalline silicon Si is doped with phosphorus by the RIE method using chlorine gas or a mixed gas containing chlorine as a constituent element.

etching. Here, chlorine (C
RIE excited by high frequency power of 13.56 MH was used. The etching conditions are as follows:
The flow rate of C1□ is 20cc/min, and the pressure is 400 Torr.
It was set to r. A high frequency power of 200 W was input here, and etching was performed for 5 minutes. The etching rate obtained at this time is 1500 etching per minute for the phosphorous-doped polycrystalline silicon film.

Following this etching step, the second interlayer oxide film 9 is etched, and the first polycrystalline silicon W/, 8 is further etched. Etching of the second interlayer oxide film 9 is performed by wet etching using dilute hydrofluoric acid (HF). The first polycrystalline silicon film 8 was etched using RIE excited by a high frequency power of 13.56 MH2 using sulfur hexafluoride (SF) as a reactive gas. As etching conditions, the flow rate of SF is 50cc/
minutes and the pressure was set at 200 mTorr. Here,
Etching was performed for 1 minute by inputting a high frequency power of 300 W. The etching speed obtained at this time is 3500
Person/minute was obtained. As a result, the first polycrystalline silicon film 8 is left in the groove 7 of the first interlayer oxide film 6 in a U-shape.
A portion of the second interlayer oxide film 9 and the second polycrystalline silicon film 10 are left in the recessed portion of the first polycrystalline silicon film 8.

Next, as shown in FIG. 1(h), the RIE method using chlorine gas or a mixed gas containing chlorine as a constituent element, in this case,
Using chlorine (C1z) as a reaction gas, high frequency power 13
．． The second polycrystalline silicon film 10 is etched back using RIE excited by 56MH2. As etching conditions, the flow rate of C1t was set to 20 cc for 7 minutes, and the pressure was set to 400 mTorr. Here, 20
Etching was performed for 5 minutes by inputting high frequency power of 0W. The etching speed obtained at this time is the non-doped polycrystalline +J1711! In this case, 300 people/min can be obtained, and 1,500 people/minute can be obtained for phosphorous-doped polycrystalline silicon, and a selectivity of 5 can be obtained. Through this etching back step, the second polycrystalline silicon film 10 present within the first polycrystalline silicon film 8 is selectively removed.

Next, as shown in FIG. 1(i), by wet etching using dilute hydrofluoric acid, the first interlayer oxide film 6 was etched by about 500 mm for a film thickness of 12000 mm.
First polycrystalline silicon film 8 is exposed. Through this etching back step, a U-shaped polycrystalline silicon electrode 8A made of the first polycrystalline silicon film 8 is obtained, and a capacitor electrode is formed by vapor phase diffusion of phosphorus into this electrode.

Thereafter, a capacitor is formed by growing a dielectric film and forming a counter electrode, but a description thereof will be omitted.

The capacitor electrode 8A formed in this way is formed on the silicon substrate 1.
Since the structure extends upward in a U-shape, a large electrode area can be obtained compared to the plane area occupied, and the capacitance can be increased. When forming this capacitor electrode, a groove 7 is formed in the thick first interlayer oxide film 6 provided on the silicon substrate 1, and polycrystalline silicon films 8 and 10 are buried in the groove 7. Therefore, even if the surface of the silicon substrate 1 has unevenness, it is hardly affected by the unevenness, and fine patterning is possible, and there are no problems caused by etching residue or over-etching. .

FIGS. 2(a) to 2(g) are cross-sectional views for explaining the second embodiment of the present invention in the order of steps. Note that the same parts as in the first embodiment are given the same reference numerals.

First, as shown in FIG. 2(a), an element isolation oxide film 2 is formed on a silicon substrate 1 by a selective oxidation method, and then a film with a thickness of 2
A phosphorous-doped polycrystalline silicon film 3 and an oxide film 4 are formed by 500 people, and these films are patterned by RIE to form a gate. And on top of this, CVD
An oxide film 5' having a thickness of 2,000 wafers is formed by the method.

Next, as shown in FIG. 2(b), a resist mask 11 with a window 12 opened at a portion to be connected to an electrode is formed, and the oxide film 5' is etched by RIE using this resist mask. As a result, the surface of the silicon substrate 1 of the oxide film 5' is exposed at the electrode connection portion.

Next, as shown in FIG. 2(C), a non-doped base polycrystalline silicon film 13 is deposited to a thickness of 2000 mm, and a resist mask 14 is formed to cover the region including the electrode connection portion, and using this, RIE is performed. The base polycrystalline silicon film 13 is
etching.

Next, as shown in FIG. 2(d), after removing the resist mask 14, the first interlayer doped with boron and phosphorus has a film thickness of 12,000 mm, which corresponds to the thickness of the U-shaped electrode to be formed. An oxide film 6 is formed and heat treatment for reflow is performed.

Thereafter, as shown in FIG. 2(e), a groove 7 is formed in the first interlayer oxide film 6 by a process similar to that of the first embodiment, and a first groove 7 is formed on the first interlayer oxide film 6 to a thickness of 2000 mm without adding impurities. A polycrystalline silicon film 8 is grown, and this polycrystalline silicon film 8 is
A second interlayer oxide film 9 of about 200 carbon atoms in thickness is formed by oxidation in an oxidizing atmosphere at a temperature of 0.degree. It grows to a thickness of about 5,000 people over the entire surface including the 8th concave part.

Next, as shown in FIG. 2(f), the phosphorous-doped second polycrystalline silicon 1110 is etched back. Here, chlorine (CI□) is used as the reaction gas, and high-frequency power 1
The RIE method excited by 3.56MH2 was used.

As the enching conditions, the flow rate of CI□ was set to 20 cc/min, and the pressure was set to 400 mTorr. Here, 20
Etching was performed for 5 minutes by inputting high frequency power of 0W. The etching rate obtained at this time is 1500 etching per minute for the phosphorous-doped polycrystalline silicon film. Next, the second interlayer oxide film 9 is etched, and subsequently the first polycrystalline silicon film 8 is etched back. The second interlayer oxide film 9 is etched by wet etching using dilute hydrofluoric acid (HF). For etching back the first polycrystalline silicon film 8, sulfur hexafluoride (SF) is used as a reactive gas, and a high frequency electrode 13.56MH
The RIE method excited by 2 is utilized. As etching conditions, the flow rate of SF was set at 50 cc/min, and the pressure was set at 200 mTorr. A high frequency power of 300 W was input here, and etching was performed for 1 minute. The etching rate obtained at this time was 3500 people/min.

Next, as shown in FIG. 2(g), a second polycrystalline silicon film 1 is embedded in the recess of the first polycrystalline silicon film 8.
0 and the first interlayer oxide film 9 are removed by etching. At this time, the second polycrystalline silicon film 10 doped with phosphorus is
In order to etch back the non-doped polycrystalline silicon film 8 at a high rate, an RIE method using chlorine gas or a mixed gas containing chlorine as a constituent element is used. Here, chlorine (C1□) was used as a reaction gas, and RIE method was used in which the reaction was excited by high-frequency power of 13.56 MH2. As etching conditions, the flow rate of CL was set at 20 cc/min and the pressure was set at 400 m Torr.

Here, 200 W of high frequency power was input and etching was performed for 5 minutes. The etching rate obtained at this time is 300 people/min for the first non-doped polycrystalline silicon film 8;
With the second phosphorus-doped polycrystalline silicon M10, a rate of 1,500 people/min is obtained, and a selectivity of 5 is obtained. Thereafter, by wet etching using dilute hydrofluoric acid, the first interlayer oxide film 6 was etched by about 8,000 etchings for a film thickness of 12,000, thereby removing the first polycrystalline silicon film 8 and the underlying polycrystalline silicon film. Expose 13. As a result, a U-shaped polycrystalline silicon film electrode 8A made of the first polycrystalline silicon film 8 is obtained, and a phosphorous vapor phase is applied to this U-shaped electrode 8A and an electrode 13A formed from the underlying polycrystalline silicon film. A capacitive electrode is formed by performing the diffusion.

In this embodiment as well, the same effects as in the first embodiment can be obtained, but in addition, in this embodiment, the υ-shaped electrode 8
In addition to A, an electrode 13A made of an underlying polycrystalline silicon film
Since it is formed into a wing shape, it is possible to use this wing part as a capacitive electrode, and these electrodes 8A,
By combining 13A, it is possible to obtain even larger capacity.

〔Effect of the invention〕

As explained above, the present invention involves forming a first polycrystalline silicon film in a groove formed in a first interlayer oxide film, forming a second interlayer oxide film on the surface of the first polycrystalline silicon film, and then forming a second polycrystalline silicon film on the surface of the first polycrystalline silicon film. By forming a crystalline silicon film and sequentially etching and removing the polycrystalline silicon film and interlayer oxide film, a U-shaped capacitor electrode can be formed using the first polycrystalline silicon film.

Since the capacitor electrode formed in this way has a U-shaped configuration extending upwards of the semiconductor substrate, it is possible to obtain a large electrode area compared to the planar area it occupies.
Capacity can be increased.

When forming this capacitor electrode, a method is used in which a polycrystalline silicon film is buried in the groove of the thick first interlayer oxide film provided on the semiconductor substrate and then etched back. Even if the surface is uneven, the film formation, patterning, etching, etc. processes are hardly affected by the unevenness, making it possible to perform fine patterning, and to avoid problems caused by over-etching if etching remains. will never come to life.

[Brief explanation of the drawing]

Figures 1 (a) to i) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and Figures 2 (a) to g) are cross-sectional views showing the second embodiment of the present invention in the order of steps. be. 1... Silicon substrate, 2... Element isolation oxide film, 3.
... Gate polycrystalline silicon film, 4,5.5'... Oxide film, 6... First interlayer oxide film, 7... Groove, 8...
1st polycrystalline silicon film, 8A... U-shaped electrode, 9 Second interlayer oxide film, 10... Second polycrystalline silicon film, 11... Resist mask, 12 Kawamado, 13 ... Base polycrystalline silicon film, 13A... Electrode, 14...
resist mask. Figure 1 Figure 2 Figure 2 Figure 2

Claims (1)

[Claims] 1. A step of forming a first interlayer oxide film of a required thickness on a semiconductor substrate forming a semiconductor memory element, and a step of forming a first interlayer oxide film on the semiconductor substrate at a location where an electrode is to be formed on the first interlayer oxide film. forming a groove exposing the surface of the groove, and forming a first groove in the area including the groove.
a step of forming a second interlayer oxide film on the surface of the first polycrystalline silicon film; and a step of forming the first polycrystalline silicon film on the second interlayer oxide film. A step of forming a second polycrystalline silicon film so as to be buried in a recess formed in the film, and a step of forming a second polycrystalline silicon film, a second interlayer oxide film, and a first polycrystalline silicon film etching back to leave these polycrystalline silicon films only in the grooves of the first interlayer oxide film; and selectively etching away the second polycrystalline silicon film and the second interlayer oxide film in the grooves. and removing the first interlayer oxide film. 2. Forming an insulating film on a semiconductor substrate forming a semiconductor memory element, forming an opening in this insulating film to expose the semiconductor substrate, and selectively applying a base polycrystalline silicon film to a region including this opening. a step of forming a first interlayer oxide film of a required thickness; a step of forming a groove exposing the base polycrystalline silicon film at a location of the first interlayer oxide film where an electrode is to be formed; A step of forming a first polycrystalline silicon film on the entire surface including the groove, a step of forming a second interlayer oxide film on the surface of the first polycrystalline silicon film, and a step of forming a second interlayer oxide film on the surface of the first polycrystalline silicon film. a step of forming a second polycrystalline silicon film so as to be buried in the recess formed in the first polycrystalline silicon film;
etching back the interlayer oxide film and the first polycrystalline silicon film to leave these polycrystalline silicon films only in the grooves of the first interlayer oxide film; and etching back the second polycrystalline silicon film in the grooves. A method of manufacturing a semiconductor memory device, comprising the steps of selectively etching away a film and a second interlayer oxide film, and removing the first interlayer oxide film.