JPH0575060A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To secure the electrical insulation between a bit line and an electric charge storage electrode even though the bit line is significantly exposed during the opening of a contact of the electric charge storage electrode due to a deviation in a lithography process. CONSTITUTION:An SiO2 film 2 is first formed on a p-type semiconductor substrate 1 by a LOCOS method. Thereafter, a switching transistor and a bit line 6 are formed. Then, for connecting an electric charge storage electrode 9 to a diffusion layer 7, anisotropic etching is performed using a resist pattern 7 as mask until part of the bit line is exposed from the first insulation film 3. Then, the resist pattern 7 is removed, the second insulation film 8 made of a high temperature oxide silicon film is deposited to 150nm, a side wall is formed by etching back the second insulation film 8 by the 30% over-etching relative to deposition film thickness, and then the bit line 6 can be electrically insulated from the electric charge storage electrode 9 with the sidewall of the second insulation film 8.

Description

Detailed Description of the Invention

[0001]

The present invention relates to The present invention relates to a semiconductor memory device, and more particularly to a method of manufacturing a stack type memory cell having a structure in which a storage capacitor is formed above a switching transistor and a bit line in a DRAM (Dynamic Random Access Memory).

[0002]

2. Description of the Related Art As a memory cell for high density DRAM, 1
A "one-transistor, one-capacitor" type memory cell composed of a transistor and one storage capacitor is widely used because it has few constituent elements and the cell area can be easily miniaturized. In particular, in order to meet the demand for further miniaturization of elements, a stack type memory cell forming a storage capacitor above a switching transistor has become one of the promising candidates.

FIG. 2 is a top view of the semiconductor memory device, and FIGS. 4 and 5 are process sectional views of the conventional method for manufacturing the semiconductor memory device shown in FIG. 2, showing a cross section taken along the line AA of FIG. The figure is shown. Hereinafter, as a first conventional example, Japanese Patent Application No. 2-
The conventional technique filed in 207442 will be described with reference to FIGS. 2 and 4.

In FIGS. 2 and 4, the active region 21 of the switching transistor is electrically separated by the SiO 2 film 2, and the word line 20, the bit line 6, the charge storage electrode 9, the capacitance insulating film 10 and the plate electrode are formed on the active region 21. 11 are sequentially formed. The active region 21 is the bit line contact 2
The bit line 6 is connected by 2 and the charge storage electrode 9 is connected by the charge storage electrode contact 23. The active region 21, the bit line 6, and the charge storage electrode 9 are electrically insulated from each other by an insulating film except for the contact portions.

In FIG. 4A, the SiO 2 film 2 is first formed on the p-type semiconductor substrate 1 by the LOCOS method. After that, the switching transistor and the bit line 6 are formed by using a known technique. Here, 7 is an n + type diffusion layer which is the source / drain of the switching transistor, and 3 is the first
, And 6 is a bit line. Next, in order to connect the charge storage electrode 9 and the diffusion layer 7, the first insulating film 3 is anisotropically etched by using the resist pattern 17 as a mask.
The diffusion layer is exposed by providing the opening 13 in the.
At this time, as the device becomes finer, the bit line is easily exposed due to misalignment in the lithography process. Therefore, next, as shown in FIG. 4B, the second insulating film 8 is formed.
After covering the side wall of the opening 13 with, the charge storage electrode 9 is formed as shown in FIG.

Next, a second conventional technique will be described with reference to FIG. Several structures have been proposed in which the bottom surface of the charge storage electrode is also used as the electrode surface in order to obtain a sufficient charge storage capacity as the device becomes higher in density. One example is a wet method using a hydrofluoric acid solution. There is a method of removing a part of the first insulating film 3 by etching to provide a space between the first insulating film 3 and the charge storage electrode 9.

In FIG. 5A, a silicon nitride film as the second insulating film 8 and a silicon oxide film as the third insulating film 31 are sequentially deposited on the first insulating film 3 and then the resist pattern 17 is used as a mask. , The third insulating film 31, the second insulating film 8, and the first insulating film 3 are removed by anisotropic etching to form the opening 13
To open. Next, in FIG. 5B, a sidewall is formed with the fourth insulating film 33 in order to ensure insulation between the bit line 6 and a charge storage electrode that will be formed later. After that, FIG.
After depositing polycrystalline silicon as the first conductive film 32 as shown in (c), the charge storage electrode is patterned as shown in FIG. 5 (d). Then, as shown in FIG. 5E, the third insulating film 3 is formed.
The silicon oxide film of No. 1 is removed using a hydrofluoric acid solution,
A space 1 is formed between the bottom surface of the charge storage electrode 9 and the second insulating film 8.
4, the charge storage electrode surface exposed by the space 14 is also used as an electrode to obtain a sufficient storage capacity.

[0008]

However, the above-mentioned configuration has the following problems. First, in the first conventional technique, if the exposed width of the bit line 6 is larger than the film thickness of the second insulating film 8, the bit line exposed portion 15 remains even after the sidewall protective film of the second insulating film 8 is formed. Will end up.
Therefore, as shown in FIG. 4C, there is a problem that the bit line 6 and the charge storage electrode 9 are short-circuited after the charge storage electrode 9 is formed. 16 indicates a short-circuited portion.

In view of the above point, the first object of the present invention is to provide a large exposure of the bit line when the opening is provided due to misalignment in the lithography process.
An object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of ensuring electrical insulation between a bit line and a charge storage electrode.

Next, in the second conventional technique, during wet etching, the first insulating film 3 is also etched through the sidewalls of the fourth insulating film 33 as shown in FIG. Exposed. If the capacitance insulating film and the plate electrode are formed in this state, there is a problem in that the capacitance between the bit line and the plate electrode increases, which causes inconvenience in stable operation of the device.

Therefore, a second object of the present invention is to stabilize a semiconductor memory device in which the bottom surface of the charge storage electrode is also used as an electrode surface even if the side wall of the insulating film is used, without etching the first insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device that can be manufactured according to the above method.

[0012]

In order to solve the above-mentioned problems, the first invention of the present invention is to electrically connect a diffusion layer of a switching transistor and a charge storage electrode,
Etching a part of the first insulating film until the bit line is exposed, etching the exposed bit line, and etching the remaining first insulating film to provide an opening, The method includes a step of depositing a second insulating film so as to cover the opening, and a step of etching back the second insulating film by an anisotropic etching method by at least the deposited film thickness. A method of manufacturing a semiconductor memory device is characterized by ensuring electrical insulation between a line and the charge storage electrode.

A second aspect of the present invention is a step of depositing a second insulating film, a third insulating film, and a first conductive film to be the bottom of the charge storage electrode on the first insulating film. And a step of etching the first conductive film to electrically connect the diffusion layer of the switching transistor and the charge storage electrode, and a third insulating film, a second insulating film, and a first insulating film. A step of etching the film to provide an opening, and a step of depositing a fourth insulating film so as to cover the opening,
Etching back by an anisotropic etching method so that a part of the cross section of the first insulation film is exposed by the fourth insulation film and the cross section of the bit line is covered; and a diffusion layer of the switching transistor. A step of forming a charge storage electrode after depositing a second conductive film so as to be electrically connected to the first conductive film, and A step of selectively removing the third insulating film under an etching condition in which the etching rate of the third insulating film is sufficiently large, ensuring electrical insulation between the bit line and the charge storage electrode, and storing the charge. In the method of manufacturing a semiconductor memory device, the bottom surface of the electrode is also used as the electrode.

[0014]

According to the present invention, even if the bit line is largely exposed when the opening is formed in the first insulating film according to the above-described first structure, a vertical step is added by adding a step of etching the exposed bit line. Since the cross section of the opening is obtained, it is possible to ensure the insulation between the bit line and the charge storage electrode without exposing the bit line even after forming the sidewall of the second insulating film later.

Further, since the cross section of the opening of the third insulating film is completely covered with the second conductive film by the above-described second structure, the etching solution is used during the wet etching after the charge storage electrode is formed. Does not penetrate below the second insulating film, and the first insulating film and the fourth insulating film are not etched. Therefore, it is possible to ensure electrical insulation between the bit line and the charge storage electrode, and to secure a sufficient insulating film between the plate electrode and the bit line even when the bottom surface of the charge storage electrode is used as an electrode. ..

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the steps of a method for manufacturing a semiconductor memory device according to the first embodiment of the present invention, the section being taken along the plane AA of FIG. is there.

In FIG. 1A, a SiO2 film 2 is first formed on a p-type semiconductor substrate 1 by the LOCOS method. After that, the switching transistor and the bit line 6 are formed by using a known technique. Here, 7 is an n + type diffusion layer which is a source / drain of a switching transistor, 3 is a first insulating film, and 6 is a bit line. Next, the charge storage electrode 9
Pattern 17 for connecting the diffusion layer 7 and the diffusion layer 7.
Is used as a mask to anisotropically etch the first insulating film 3 until a part of the bit line is exposed. FIG. 1A shows a case where the bit line is exposed by 200 nm due to misalignment in the lithography process.

Next, in FIG. 1B, the bit line 6 exposed by using the resist pattern 7 as a mask is continuously removed by etching, and then the remaining first insulating film 3 is removed by etching to form an opening 13 having a vertical sectional shape. To open.

Next, in FIG. 1C, after the opening 13 is provided and the resist pattern 17 is removed, a second insulating film 8 made of a high temperature CVD silicon oxide film (hereinafter referred to as HTO) 150 is formed.
After the nm deposition, the second insulating film 8 is etched back by overetching 30% of the deposited film thickness to form sidewalls.

Thereafter, in FIG. 1D, a charge storage electrode 9 made of polycrystalline silicon, a capacitive insulating film 10 made of silicon oxynitride, and a plate electrode 11 made of polycrystalline silicon.
To form. A storage capacitor is formed by the charge storage electrode 9, the capacitance insulating film 10, and the plate electrode 11.

As described above, according to this embodiment, the opening 1
Even if the bit line 6 is largely exposed when opening 3, the opening 13 having a vertical cross-sectional shape can be formed by adding a step of etching the exposed bit line 6. The side wall of the insulating film can electrically insulate the bit line 6 and the charge storage electrode 9 from each other.

The etching conditions for the first insulating film 3 and the bit line 6 are reactive ion etching using CH2F2 / CF4 gas and reactive ion etching using HCl / HBr / SF6 / O2, respectively. Using a multi-chamber system equipped with a chamber, the opening 13 was opened by three-step etching without exposing the wafer to the atmosphere.

In this embodiment, the multi-chamber type etching apparatus performs three-step etching, but three-step etching may be performed in the same processing chamber by changing the processing conditions.

(Embodiment 2) FIG. 3 is a sectional view showing the steps of a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention, the section being taken along the plane AA of FIG. is there. In FIG. 3A, LOC is first formed on the p-type semiconductor substrate 1.
The SiO 2 film 2 is formed by the OS method. After that, the switching transistor and the bit line 6 are
To form. Here, 7 is an n + type diffusion layer which is a source / drain of the switching transistor, and 3 is a first insulating film. Next, 30 nm of silicon nitride is used as the second insulating film 8 on the first insulating film 3, and H is used as the third insulating film 31.
TO 30 nm, and further, n + polycrystalline silicon is sequentially deposited as the first conductive film 32, the first conductive film 32 is etched by anisotropic etching using the resist pattern 7 as a mask, and then the third insulating film 31 and the second insulating film 31 are formed. Insulating film 8, first
The insulating film 3 is sequentially removed by etching to open the opening 13.

In FIG. 3B, after forming the opening 13 and removing the resist pattern 17, a fourth insulating film 33 made of a high temperature CVD silicon oxide film (hereinafter referred to as HTO) is formed to a thickness of 150 n.
After the m deposition, the fourth insulating film 33 is etched back until the cross section of the third insulating film is completely exposed to form sidewalls.

In FIG. 3C, n + polycrystalline silicon is deposited as the second conductive film 34 so as to be electrically connected to the n + diffusion layer 7 and the first conductive layer 32.

In FIG. 3D, the second conductive film 34 and the first conductive film 34 are formed.
The conductive film 32 is etched to pattern the charge storage electrode.

In FIG. 3E, after the third insulating film 31 is removed by etching with a mixed solution of hydrofluoric acid and ammonium fluoride, the capacitive insulating film 10 made of silicon oxynitride and the plate electrode made of polycrystalline silicon are formed. 11 is formed. A storage capacitor is formed by the charge storage electrode 9, the capacitance insulating film 10, and the plate electrode 11.

During the wet etching, since the charge storage electrode 9 and the second insulating film 8 made of silicon nitride are hardly etched, they act as an etching stopper and only the third insulating film 31 can be selectively removed.

As described above, according to this embodiment, the opening 1
Since the cross section of the third insulating film in 3 is completely covered with the second conductive film 34, the bottom surface of the charge storage electrode also serves as an electrode surface without loss of the first insulating film 3 during the subsequent wet etching. It is possible to manufacture a usable semiconductor memory device. Further, at the time of etching back the fourth insulating film 33, the first conductive film 32 serves as an etching stopper to prevent the reduction of the interlayer insulating film.

The etching conditions for the third insulating film 31, the second insulating film 8, the first insulating film 3, the first conductive film 32, and the bit line 6 are reactive ion etching using CH2F2 / CF4 gas, respectively. And HCl / HBr / SF6 /
By reactive ion etching using O2, the opening 13 was opened by four-step etching without exposing the wafer to the atmosphere by using a multi-chamber system equipped with each processing chamber.

In this embodiment, the multi-chamber type etching apparatus performs three-step etching, but four-step etching may be performed in the same processing chamber by changing the processing conditions.

In this embodiment, the bit line 6 is not exposed when the opening 13 is opened, but when the bit line 6 is exposed, the bit line etching process is performed as in the first embodiment. If added, the bit line 6 and the charge storage electrode 9
It is possible to manufacture a semiconductor memory device in which the bottom surface of the charge storage electrode can be used as an electrode surface without any loss of the first insulating film 3 while ensuring insulation with

In the present embodiment, the charge storage electrode 9 has a simple block type, but after forming a multilayer structure of silicon oxide and polycrystalline silicon to realize a more complicated three-dimensional structure. The present invention can also be applied to the case of a charge storage electrode that removes a silicon oxide film.

[0036]

As described above, the first aspect of the present invention is the first aspect.
Even if the bit line is largely exposed when the opening is formed in the insulating film of, the vertical cross section of the opening can be obtained by adding the step of etching the exposed bit line.
Even after the side wall of the insulating film is formed, the bit line is not exposed and the insulation between the bit line and the charge storage electrode can be ensured, which has a large practical effect.

Further, according to the second aspect of the present invention, since the cross section of the third insulating film in the opening is completely covered with the second conductive film, the wet state after the formation of the charge storage electrode is completed. At the time of etching, the etching liquid does not penetrate below the second insulating film, and the first insulating film and the fourth insulating film are not etched. Therefore, it is possible to secure electrical insulation between the bit line and the charge storage electrode, and to secure a sufficient insulating film between the plate electrode and the bit line even when the bottom surface of the charge storage electrode is used as an electrode. The practical effect is great.

[Brief description of drawings]

FIG. 1 is a process sectional view in a first embodiment of the present invention.

FIG. 2 is a surface view of a memory cell in the example.

FIG. 3 is a process sectional view in the second embodiment of the present invention.

FIG. 4 is a process sectional view of a first conventional technique.

FIG. 5 is a process sectional view of a second conventional technique.

[Explanation of symbols]

 2 SiO2 film 6 bit line 7 n + diffusion layer

Claims (5)

[Claims] 1. A semiconductor memory device of a DRAM comprising a switching transistor, a bit line formed on the switching transistor on a semiconductor substrate, and a storage capacitor formed on the bit line, and a diffusion layer of the switching transistor and charge storage. A step of etching a part of the first insulating film until the bit line is exposed, and a step of etching the exposed bit line to electrically connect with the electrode;
A step of etching the remaining first insulating film to form an opening, a step of depositing a second insulating film so as to cover the opening, and a step of depositing at least the second insulating film. A method of manufacturing a semiconductor memory device, comprising the step of etching back by a thickness of an anisotropic etching method to ensure electrical insulation between the bit line and the charge storage electrode. 2. A multi-chamber etching step for etching the first insulating film and the bit line according to claim 1 using a multi-chamber type etching apparatus having an insulating film etching processing chamber and a bit line etching processing chamber. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the etching is performed. 3. A DR comprising a switching transistor on a semiconductor substrate and a storage capacitor formed on the switching transistor.
In the semiconductor memory device of AM, the second insulating film is formed on the first insulating film.
For depositing an insulating film, a third insulating film, and a first conductive film that will be the bottom of the charge storage electrode, and for electrically connecting the diffusion layer of the switching transistor and the charge storage electrode, A step of etching the first conductive film, a step of etching the third insulating film, the second insulating film and the first insulating film to form an opening, and a fourth step of covering the opening. The step of depositing the insulating film of
Etching back by an anisotropic etching method so that a part of the cross section of the first insulation film is exposed by the insulation film and the cross section of the bit line is covered with the diffusion layer of the switching transistor and the first insulation film. Forming a charge storage electrode after depositing a second conductive film so as to be electrically connected to the second conductive film, and a third process for the first and second conductive films and the second insulating film. A step of selectively removing the third insulating film under an etching condition in which the etching rate of the insulating film is sufficiently large, ensuring electrical insulation between the bit line and the charge storage electrode, and the bottom surface of the charge storage electrode. A method for manufacturing a semiconductor memory device, characterized in that it is also used as an electrode. 4. A multi-chamber method comprising: the first conductive film according to claim 3; and a third conductive film etching process chamber for etching the third, second and first insulating films. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein the etching is performed by two-step multi-step etching. 5. The first and second conductive films according to claim 3 are polycrystalline silicon, the second insulating film is a silicon nitride film, and the third insulating film is a silicon oxide film. The method of manufacturing a semiconductor memory device according to claim 3.