KR100370169B1 - Method for manufacturing capacitor of semiconductor - Google Patents

Abstract

The present invention provides a method of manufacturing a capacitor of a semiconductor device that oxidizes a silicide generated through a reaction between a lower electrode material and polysilicon to separate an inter-cell storage node of a capacitor, the front surface of a semiconductor substrate including a cell transistor. Forming a contact hole by forming a first oxide film in the contact hole and selectively etching, forming a contact layer by sequentially stacking a plug layer and a barrier layer in the contact hole, and forming a second oxide film and a polysilicon layer on the entire surface of the contact hole And selectively etching the polysilicon layer to etch a second oxide layer using the mask layer to form a trench, and forming a lower electrode forming material layer on the entire surface of the trench to simultaneously react with the polysilicon layer. Forming a silicide layer, and oxidizing the silicide layer It is characterized in that it comprises the step of the isolation between the secondary electrodes, and the step of depositing a high-k dielectric layer and a material for forming the upper electrode on the front.

Description

METHODS FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device in which a storage node between cells is separated by oxidizing silicide generated by a reaction between a lower electrode material and polysilicon.

In general, as the integration degree of DRAM increases, an area per unit area of a cell becomes small, and in addition, an effective area of a capacitor decreases. As an alternative to this, a capacitor having BST (Ba: barium, Sr: strontium, Ti: titanium) as a high dielectric film was introduced. Since the deposition of the high dielectric film proceeds mainly in an oxidizing atmosphere, the lower electrode of the high dielectric film is inevitable. It is composed of Pt (platinum), Ru (ruthnum) or oxides of these materials.

Hereinafter, a capacitor manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views of a manufacturing process of a capacitor according to a conventional method.

Before describing a capacitor of a conventional semiconductor device, a transistor having a source, a drain, and a gate electrode is formed on a semiconductor substrate under the first oxide 101, although not shown in the drawing.

As shown in FIG. 1A, the first oxide 101 in the region where the poly plug 102 is to be formed is etched to expose the drain electrode of the transistor so as to be in contact with the drain electrode to form a contact hole. Silicon is deposited.

Thereafter, the polysilicon is planarized by a chemical mechanical polishing (CMP) process to form a poly plug 102 in the contact hole.

The nitride film 103 and the second oxide 104 are sequentially deposited on the poly plug 102 and the first oxide 101.

The nitride layer 103 serves as an etch spopper to protect the lower first oxide 101 when defining the size of the storage node.

As shown in FIG. 1B, after the second oxide 104 of the storage node forming region excluding the inter-cell isolation region is wet-etched and removed, the nitride layer under the etched second oxide 104 ( 103 is etched to form a cylindrical trench.

As shown in FIG. 1C, the barrier layer 105 is formed on the upper and side surfaces of the second oxide 104 and the first oxide 101 and the poly plug 102 by a chemical vapor deposition (CVD) method. After deposition, the lower electrode 106 is formed on the barrier layer 105 by a metal organic chemical vapor deposition (MOCVD) method.

Thereafter, the photoresist 107 is filled on the lower electrode 106 in the concave region of the cylindrical trench by a spin coat method.

The lower electrode 106 is composed of Pt (platinum, Ru (ruthenium) or oxides of such materials having heat resistance and oxidation resistance.

Lower electrode 106 and barrier layer 105 in the portion not covered with photoresist 107 to etch back photoresist 107 and expose second oxide 104 as shown in FIG. 1D. In order to isolate the inter-cell storage nodes in order, the photoresist 107 is removed and cleaned, and the high-k dielectric layer 108 is deposited on the entire surface by the MOCVD method.

In the above process, the high dielectric layer 108 is formed using a material such as BST (Ba: barium, Sr: strontium, Ti: titanium).

Thereafter, an upper electrode 109 is formed on the high dielectric layer 108 to complete a capacitor by a conventional method.

However, the conventional capacitor manufacturing method of the semiconductor device as described above has the following problems.

First, when defining the storage node area, the process is complicated because the nitride film used as the etch stopper layer to protect the lower insulating layer must be etched again.

Second, the photoresist etch back and the etch back of the lower electrode material and barrier layer at the inter-cell node separation result in poor process reproducibility and unevenness in the wafer resulting in the top portion of the storage node. Loss occurs.

Third, the high dielectric material material and the material of the barrier layer is in contact with each other to form a current leakage path (current leakage path) after the device is formed to reduce the reliability of the device.

Fourth, the process is difficult because the etching of Pt (platinum, Ru (ruthenium)) or the lower electrode composed of these materials is difficult to etch.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device for separating a storage node by oxidizing a silicide generated through a reaction between a lower electrode and polysilicon. .

1A to 1D are cross-sectional views of a capacitor manufacturing process of a semiconductor device of the related art.

2A to 2E are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

201: first oxide 202: barrier plug

203: second oxide 204: polysilicon

205: lower electrode 206: silicide

207: silicide oxide layer 208: high dielectric layer

209: upper electrode

According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method comprising: forming a contact hole by forming a first oxide film on an entire surface of a semiconductor substrate including a cell transistor and selectively etching the contact hole; Stacking and burying a plug layer and a barrier layer in order, forming a second oxide film and a polysilicon layer on the entire surface, selectively etching the polysilicon layer, and etching the second oxide film with a mask layer to form a trench Forming a silicide layer by forming a material layer for forming a lower electrode on the front surface of the trench and reacting with the polysilicon layer; and oxidizing the silicide layer to isolate the lower electrodes. And depositing a material for forming a high dielectric layer and an upper electrode on the front surface in turn. It characterized in that comprises the system.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2B are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.

Although not shown in the drawings before describing the capacitor of the semiconductor device of the present invention, a transistor having a source, a drain, and a gate electrode is formed on the semiconductor substrate under the first oxide 201.

As shown in FIG. 2A, the first oxide 201 in the region where the barrier plug 202 is to be formed is etched to expose the drain electrode of the transistor so as to contact the drain electrode to form a contact hole, and a barrier on the front surface thereof. Deposit the material.

Thereafter, the barrier material is planarized by a chemical mechanical polishing (CMP) process to form the barrier plug 202 in the contact hole.

A second oxide 203 and a polysilicon 204 are sequentially formed on the barrier plug 202 and the first oxide 201.

The thickness of the second oxide 203 is determined in consideration of the capacity of the DRAM capacitor.

The polysilicon 204 is a mask for later etching the second oxide 203 and is used to simultaneously separate the inter-cell storage nodes.

As shown in FIG. 2B, the polysilicon 204 wets and removes the storage node forming region except for the inter-cell isolation region through photo-lithography, and then removes the lower portion of the etched polysilicon 204. The second oxide 203 is etched to expose the barrier plug 202 and the first oxide 201 to form a cylindrical trench.

As shown in FIG. 2C, the lower electrode (top) of the polysilicon 204 and the side of the second oxide 203 and the first oxide 201 and the barrier plug 202 may be formed by a metal organic chemical vapor deposition (MOCVD) method. 205 is deposited.

The lower electrode 205 is made of Pt (platinum, Ru (ruthenium) or oxides of such materials having heat resistance and oxidation resistance.

In this process, the polysilicon 204 and the lower electrode 205 react to form the silicide 206.

As shown in FIG. 2D, heat treatment is performed in an O ₂ atmosphere to oxidize the silicide 206 to form a silicide oxide layer 207.

As shown in FIG. 2E, a high dielectric layer 208 is deposited on the silicide oxide layer 207 and the lower electrode 205 by a metal organic chemical vapor deposition (MOCVD) method.

The high dielectric layer 208 is made of a high dielectric layer including BST (Ba: barium, Sr: strontium, Ti: titanium), TaO 2, Al03, and oxygen.

In the above process, the silicide oxide layer 207 is completely oxidized to separate the storage node.

Thereafter, the upper electrode 209 is deposited to complete the capacitor of the semiconductor device according to the embodiment of the present invention.

The method of manufacturing a capacitor of the semiconductor device of the present invention as described above has the following effects.

First, since a lower electrode having a desired profile is formed by a simple process, a fine pattern of the lower electrode can be formed.

Second, when the storage node is separated between cells, the process is simple, so the process is reproducible and the reliability of the device is improved.

Third, since silicides are formed to separate storage nodes between cells, plasma damage of the high-k dielectric layer due to etching can be eliminated.

Claims (4)

Forming a contact hole by forming a first oxide film on the entire surface of the semiconductor substrate including the cell transistor and selectively etching the contact hole; Stacking and burying a plug layer and a barrier layer in the contact hole; Forming a second oxide film and a polysilicon layer on the entire surface; Selectively etching the polysilicon layer to etch a second oxide layer using a mask layer to form a trench; Forming a silicide layer by forming a lower electrode forming material layer on the front of the trench and reacting with the polysilicon layer; Oxidizing the silicide layer to allow isolation between lower electrodes; Capacitor forming method comprising the step of depositing a high-k dielectric layer, a material for forming the upper electrode on the front. The method of claim 1, And etching the polysilicon layer so as to remain only in portions except the lower electrode formation region. The method of claim 1, And the formation thickness of the second oxide film varies depending on the formation height of the lower electrode. delete