JPH056975A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device which is provided with no sharp angle at the end of a memory node and inhibits the generation of insulation breakdown and its manufacturing method. CONSTITUTION:A semiconductor memory device is a semiconductor memory device provided with a plurality of memory cells which include an accumulation capacity formed on a semiconductor board 1. The accumulation capacity comprises a memory node 10 whose edge angle is round, a capacity insulation film 11 formed on the memory node 10 and a plate electrode 12 formed on the capacity insulation film 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a stack type dynamic random access memory (DRAM) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Currently, DRAMs are becoming highly integrated,
A method has been proposed in which the capacitance forming portion is formed three-dimensionally. Among them, the stack type DRAM in which the capacity forming portion is stacked on the upper part of the substrate to serve as a storage node increases the capacity, and thus the reference T. Ema et al. "3-Dimensional Stacked Cap
acitor Cell for 16M and 64M DRAMs "IEEE Internation
al Electron Device MeetingTechical Digest, p592-59
5, various structures have been proposed in Dec.1988 and the like.

FIG. 5 is a sectional view showing the steps of a conventional semiconductor device having a memory node and its manufacturing method. Figure 5 (a)
As shown in FIG. 3, a device isolation insulating film 2 and a word line 3 which is a gate of a switching transistor are formed on a semiconductor substrate 1.
And the active region 4 of the switching transistor is formed, as shown in FIG.
-B is a SiN film, a first oxide film 6-A, a first conductive film 7-A is a polysilicon film, and a second oxide film 6-B.
Are sequentially deposited, and thereafter the contact window 8 reaching the active region of the switching transistor is opened by anisotropic etching. Polysilicon is deposited thereon as a second conductive film 7-B to form a resist pattern 9, as shown in FIG. Using the resist pattern 9 as a mask, as shown in FIG.
Etching method is used to form the second conductive film 7-B, the second oxide film 6-B, the first conductive film 7-A, and the first oxide film 6-.
After sequentially etching A, the first oxide film 6-A and the second oxide film 6-B are etched with an HF-based etching solution to form the memory node 10. Next, as shown in FIG. 2E, a dielectric film 11 made of a multilayer film of SiO2 and SiN is formed on the surface of the memory node 10, and a third conductive film 12 is formed through this dielectric. Deposit to form a cell plate, followed by formation of bit line 13.

[0004]

In such a conventional semiconductor device and the manufacturing method thereof, since the RIE method is used when forming the memory node, the memory node as shown in FIG. A sharp corner was formed at the end of the door 10. At the steep corner of the end of the memory node, the electric field is concentrated and the dielectric breakdown of the dielectric film 11 is likely to occur as shown in FIG. 6B. Furthermore, if oxidation is performed at about 850 ° C. when forming a dielectric film at this steep angle, the reference document Extended
Abstructs of the 16th (1984 International) Confere
nce on Solid State Devices and Materials, Kobe, 198
A steeper angle is generated due to the horn phenomenon as shown in 4, pp.475-478. Further, even in structures other than the multi-fin type stacked DRAM, there are steep corners, which makes manufacturing difficult.

In FIG. 6 (b), the angle θ is 90 as a steep angle.
The figure of ° is shown. The electric field to the dielectric film varies depending on the angle of the steep angle. FIG. 7 shows the relationship between this angle and the electric field strength concentrated on the angle. In FIG. 7, the electric field strength in the flat portion is set to 1. As shown in FIG. 7, it can be seen that the electric field concentrates as the angle becomes smaller, and the insulation film breakdown of the dielectric film easily occurs. Further, FIG. 8 shows a sectional view when a DRAM having the same structure is miniaturized. As is clear from FIG. 8, as the miniaturization progresses, the angle of the storage node 10 becomes smaller (θ ₁ > θ ₂ > θ ₃ ), and the dielectric breakdown of the dielectric film easily occurs from the relationship of FIG. 7. Further, as miniaturization progresses, the capacity of the cell decreases, so it is necessary to form a storage node with a larger surface area to compensate for this, but the steep angle increases, including the multi-fin type. Therefore, also in this sense, dielectric breakdown of the dielectric film is likely to occur.

The present invention solves the above problems and provides a semiconductor memory device which does not have a steep corner at the end of the memory node and in which dielectric breakdown of the dielectric film does not easily occur, and a method for manufacturing the same. The purpose is to

[0007]

A semiconductor memory device of the present invention is a semiconductor memory device provided with a plurality of memory cells including a storage capacitor formed on a semiconductor substrate, and has a rounded corner. The storage capacitor is composed of a storage node, a capacitance insulating film formed on the storage node, and a plate electrode formed on the capacitance insulating film.

The radius of curvature of the storage node is at least four times the film thickness of the capacitive insulating film. Further, the storage node is composed of a first member having an angular edge and a second member covering the edge of the first member. The second member allows the edge corner of the storage node to be formed. Is characterized by having a rounded shape.

A method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a semiconductor memory device including a plurality of memory cells including a storage capacitor formed on a semiconductor substrate, wherein an edge corner is formed on the semiconductor substrate. The method includes the steps of forming a storage node having a rounded shape, forming a capacitor insulating film on this memory node, and forming a plate electrode on this capacitor insulating film, wherein the storage capacitor stores the memory It is characterized by being composed of a node, a capacitor insulating film, and a plate electrode.

As a method of forming the storage node, a step of forming a multilayer structure including a conductive film sandwiching an insulating film on a semiconductor substrate, a step of patterning the multilayer structure by selective etching, and the insulating film The method includes a step of removing by etching, and a step of removing a sharp corner of the edge of the conductive film by etching.

As a method of forming the storage node, a step of forming a multilayer structure including a first conductive film sandwiching an insulating film on a semiconductor substrate, a step of patterning the multilayer structure by selective etching, The method includes a step of removing the insulating film by etching, and a step of forming a second conductive film that covers an edge of the first conductive film.

As a method of forming the storage node, a step of forming a multi-layer structure including a conductive film sandwiching an insulating film on a semiconductor substrate, a step of patterning the multi-layer structure by selective etching, and a step of forming the insulating film The method includes a step of removing the oxide film by etching, a step of forming an oxide film on the surface of the conductive film, and a step of removing the oxide film by etching.

[0013]

According to the present invention, by having the storage node with all the corners rounded according to the above-mentioned structure, it is possible to prevent the dielectric film from causing dielectric breakdown due to the electric field not being concentrated on the dielectric film. You can

[0014]

(Embodiment 1) FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 1 (a) to FIG.
The steps up to (d) are basically the same as those of the conventional example shown in FIGS. 5 (a) to 5 (d), but will be described in more detail.

In FIG. 1A, an oxide film of about 400 nm is formed as a device isolation insulating film 2 by a LOCOS method on a p-type silicon substrate as a semiconductor substrate 1 and a word line 3 which is a gate of a switching transistor. After that, a polysilicon wiring in which P is diffused is formed, P and As are ion-implanted as an active region 4 of the switching transistor to form an n layer, and then an interlayer insulating film 5-A is formed as shown in FIG.
After depositing 0 nm BPSG (Boron doped Phospho-Silicate Glass) by atmospheric pressure CVD method and flattening by heat treatment, depositing about 20 nm SiN film as an interlayer insulating film 5-B by CVD method, and then forming a first oxide film 6- An oxide film containing P (phosphorus) as A, a polysilicon film containing P as the first conductive film 7-A, and an oxide film containing P as the second oxide film 6-B are sequentially deposited by the CVD method, After that, a resist pattern is formed by an ordinary photolithography method, and a contact window 8 reaching the active region 4 of the switching transistor 8 is formed.
Are opened by anisotropic etching such as RIE.
In this embodiment, the first oxide film 6-A and the second oxide film 6-B are used.
Was etched with a mixed gas of CHF ₃ and O ₂ , and the first conductive material 7-A was etched with a mixed gas of HBr and HCl.

In FIG. 3C, polysilicon containing P is deposited as the second conductive film 7-B to form a resist pattern 9. Using this resist pattern 9 as a mask, the first anisotropic etching is performed by using the RIE method as shown in FIG. 3D, for example, the second conductivity is obtained by using the RIE method using HBr gas as a main component. The film 7-B and the first conductive film 7-A were formed by RI using a CHF ₃ + O ₂ -based gas.
After the second oxide film 6-B and the first oxide film 6-A are sequentially etched by the E method, the first oxide film 6-A and the second oxide film 6-B are removed with an HF-based etching solution. The memory node 10 is formed by etching. In the present embodiment, P is used as the first conductive film 7-A and the second conductive film 7-B, respectively.
Was deposited to a thickness of about 200 nm. Where P
The reason why polysilicon containing impurities such as is used is that polysilicon containing impurities can be deposited so as to easily fill the contact window 8 by a low pressure CVD method or the like, and F (fluorine) can be deposited.
Alternatively, it can be easily etched by a gas containing at least either Br (bromine) or Cl (chlorine), and has excellent compatibility with the conventional technique.

Next, in FIG. 1E, the resist pattern 9
After the removal, the storage node 10, which is a feature of the present invention, is isotropically etched. In this embodiment, ECR (Electron Cyc
The lotron resonance method was used to etch about 10 nm with SF ₆ gas flow rate: 50 sccm, pressure: 7 Pa, and microwave (μ) wave: 220 mA to remove all sharp corners of the memory node 10. In this embodiment, a multi-fin type storage node is used, but isotropic etching is used for any type of storage node such as a n-type fin type or cylindrical type storage node. You can remove sharp corners.

Next, as in the conventional example, in FIG.
SiO ₂ of about 2 nm is formed as a dielectric film 11 on the surface of the memory node 10 and SiN of about 5 nm is formed by the low pressure CVD method, and the third conductive film 12 is formed by the low pressure CVD method through the dielectric film 11. 200nm of polysilicon film containing impurities such as P
To form a cell plate, and then form the bit line 13.

In this way, the steepest part of the storage node with all the corners rounded becomes a corner where three surfaces gather when the shape of the storage node is a rectangular parallelepiped. However, the curvature radius of the corner of the storage node viewed from above the silicon substrate is generally 25 due to the resolution limit of the photography technology.
There is more than 00Å. Furthermore, since the capacity insulating film normally used is 100 liters or less when converted to a thermal oxide film, it can be said that it is sufficiently rounded with respect to the capacity insulating film. Therefore, the electric field concentration at the corners of the storage node can be considered in two dimensions as shown in FIG. In this case, considering that the charge is evenly distributed in the corner portion, the electric field concentration in the corner portion is inversely proportional to the ratio of the outer circumference to the inner circumference of the capacitive insulating film.

FIG. 10 shows the capacitance insulating film thickness T with respect to the ratio of the electric field strength Eflat in the flat portion and the electric field strength Ecorner in the corner portion.
The relationship between the ratio of the curvature radius r of _ox and the corner portion is shown. Generally, by suppressing the electric field concentration to about 1.25 times that of the flat portion, the breakdown of the capacitive insulating film can be reduced. Figure 10
From this relationship, it can be seen that in this case, it is necessary to have a relative radius of curvature that is four times the film thickness of the capacitive insulating film. If the relative flatness is 1.2 times or less, the relative radius of curvature is 5 times the film thickness of the capacitive insulating film, and if it is 1.1 times or less, it is 10 times the film thickness of the capacitive insulating film. It is necessary to have a relative radius of curvature.

Although SF ₆ gas was used by the ECR method for isotropic etching in the first embodiment, CF ₄ , H
The same effect can be obtained by using at least a gas containing F or Br or Cl such as Br or HCl. Furthermore, etching methods other than the ECR method,
For example, the same effect can be obtained by the triode method, the downflow method, or the RIE method under the condition of side etching. Further, the isotropic etching can be performed with a liquid containing fluorinated nitric acid as a main component.

Further, in FIG. 1B, the first conductive film 7
-A shows the case of one set, but a plurality of sets may be stacked via an oxide film.

(Embodiment 2) FIG. 2 is a cross-sectional view of steps in a method of manufacturing a semiconductor device according to a second embodiment. 2 (a) is shown in FIG.
Since it corresponds to (d) and its steps are completely the same as those in FIG. That is, the feature of the second embodiment is that the second anisotropic etching is performed after removing the resist pattern 8 as shown in FIG. In this example, the RIE method was used to carry out etching by about 10 nm with HBr gas flow rate: 60 sccm, HCl gas flow rate: 20 sccm, pressure: 15 Pa, and RF power: 150 W. At this time, due to the sputtering effect, the memory node 1
The tendency of etching so that a sharp corner of 0 is removed was used. The reason for using the above-mentioned gas system in this embodiment is to emphasize the effect of rounding the corners by utilizing the reaction between polysilicon and gas. Next, in FIG. 2 (c),
A dielectric film 11 is formed on the surface of the memory node 10, a third conductive film 12 is formed through the dielectric film 11, and then a bit line 13 is formed.

Although a mixed gas of HBr and HCl was used by the RIE method for the second anisotropic etching in this embodiment, it contains F, Br, or Cl such as CF ₄ , HBr, and HCl. The same effect can be obtained by using at least gas. The same effect can be obtained with a sputtering gas such as Ar. Furthermore, R
An etching method other than the IE method, such as an ECR method in which RF (high frequency) is applied, is also possible.

(Embodiment 3) FIG. 3 is a cross-sectional view of steps in a method of manufacturing a semiconductor device according to a third embodiment. That is, FIG.
1A corresponds to FIG. 1D, and the process up to that is exactly the same as that in FIG. That is, the steps that characterize the third embodiment will be described.

In FIG. 6B, the fourth conductive film 14 is deposited after removing the resist pattern 9. Normally, when the fourth conductive film 14 is deposited on the memory node 10, the corners of the memory node 10 are rounded, both convex and concave. The coverage of the fourth conductive film 14 is uniform (1: on the surface and the side surface:
In the case of 1), the deposited film thickness becomes the radius of curvature, and the film thickness of the fourth conductive film 14 may be set to be four times or more the film thickness of the capacitance insulating film. In this embodiment, the second conductive film 14 is formed into the second conductive film 14.
Polysilicon containing P was deposited to a thickness of about 70 nm as in the case of the conductive film 7-B. The film thickness of the fourth conductive film 14 corresponds to 10 times the film thickness of the capacitive insulating film. Here, the reason why the film similar to the second conductive film 7-B is used as the fourth conductive film 14 is that the etching rate in the next step is different from that of the fourth conductive film 14 and the second conductive film 7-B. This is to prevent the formation of a steep angle due to overetching by making the same for the film 7-B.

Next, in FIG. 7C, the fourth conductive film 14 is formed.
Then, the portion other than the storage node 10 is removed by anisotropic etching, and the storage node 10 is formed again. At this time, the 4th
The rounded corners at the top of the memory node 10 when the conductive film 14 of FIG. Next, the same figure (d)
As shown in FIG. 1, a dielectric film 11 is formed on the surface of the memory node 10 as in the conventional example, and a third conductive film 12 is formed through the dielectric film 11 to form a cell plate, and the bit line 1
3 is formed.

In this embodiment, the second conductive film 7-B is used.
Although the same material is used for the fourth conductive film 14 and the fourth conductive film 14, different materials may be used.

(Embodiment 4) FIG. 4 is a sectional view of steps in a method of manufacturing a semiconductor device according to a fourth embodiment. That is, FIG.
1A corresponds to FIG. 1D, and the process up to that is the same as that in FIG. That is, the steps that characterize the fourth embodiment will be described. That is, as shown in FIG. 2B, after the resist pattern 9 is removed, the memory node 1
Oxidize 0. At this time, if oxidation is performed at a temperature of 900 ° C. or less, a steeper angle is generated due to the horn phenomenon. However, when the oxidation temperature is set to 1000 ° C. or higher, the oxide film 15 is formed by being oxidized so that sharp corners are rounded. In this example, the oxide was oxidized to about 50 nm at 1100 ° C.

Next, in FIG. 7C, the oxide film 15 is formed of HF-based material.
It was removed by the etching solution. This oxide film removal process
Is C even if the wet etching method is used as in this embodiment.
HF ₃Isotropic plasma etching method using gases such as
The same effect can be obtained by using. Next, as shown in FIG.
As in the conventional example, the dielectric film 1 is formed on the surface of the memory node 10.
1 is formed, and the third conductive film is formed through the dielectric film 11.
12 to form a cell plate, followed by bit line 13
To form.

In the first, second, third and fourth embodiments, polysilicon containing P as an impurity is used as the first and second conductive films, but an n-type impurity such as As is used. If Further, another conductive film such as W may be used.
Further, the first and second conductive films may be made of different materials.

In each of the embodiments, a stack type DRAM having a double fin structure is used, but an n-fold fin type DRAM may be used, and another stack type DRAM such as a cylinder type shown in FIG. 11 may be used. The effect is obtained. Further, although the p-type silicon substrate is used as the semiconductor substrate 1, another semiconductor substrate such as GaAs may be used. As a dielectric film, SiO2 and
Although the multilayer film of SiN is used, other dielectric films such as Si02, SiN, and TaO may be used. Further, similar effects can be obtained even if the p-type and the n-type are reversed in each of the embodiments.

[0033]

As is apparent from the above description, according to the present invention, it is possible to provide a semiconductor device in which the corners of a memory node can be rounded and dielectric breakdown of a dielectric film does not occur, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a process sectional view of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

5A to 5C are process sectional views showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a schematic diagram showing an electric field applied to a dielectric film in a conventional semiconductor device.

FIG. 7 is a characteristic diagram of the angle of the storage node and the relative electric field strength.

FIG. 8 is a sectional view of a DRAM using different design rules.

FIG. 9 is a schematic diagram showing a radius of curvature of a storage node and a thickness of a capacitor insulating film.

FIG. 10 is a relational diagram of the ratio of the thickness of the capacitive insulating film _Tox and the radius of curvature r of the corner portion to the ratio of the electric field strength Eflat of the flat portion and the electric field strength Ecorner of the corner portion.

FIG. 11 is a sectional view of a cylindrical stack type DRAM.

[Explanation of symbols]

1 Semiconductor substrate 4 Active area 7-A First conductive film 7-B Second conductive film 10 storage nodes 11 Dielectric film 12 Third conductive film

Claims (7)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cells including storage capacitors formed on a semiconductor substrate, the memory node having rounded corners, and the memory node formed on the memory node. A semiconductor memory device characterized in that the storage capacitor is composed of the formed capacitive insulating film and a plate electrode formed on the capacitive insulating film. 2. A semiconductor memory device according to claim 1, wherein the radius of curvature of the storage node is at least four times the film thickness of the capacitive insulating film. 3. The storage node according to claim 1, comprising a first member having an edge with an angular corner, and a second member covering the edge of the first member, and the second member. As a result, the semiconductor memory device is characterized in that the corners of the edges of the storage node have a rounded shape. 4. A method of manufacturing a semiconductor memory device comprising a plurality of memory cells including storage capacitors formed on a semiconductor substrate, comprising: a storage node having rounded corners on a semiconductor substrate. A step of forming, a step of forming a capacitance insulating film on the storage node, and a step of forming a plate electrode on the capacitance insulating film, wherein the storage capacitance is formed from the storage node, the capacitance insulating film, and the plate electrode. A method for manufacturing a semiconductor memory device, which is configured. 5. A method of forming a storage node according to claim 4, wherein a step of forming a multi-layer structure including a conductive film sandwiching an insulating film on a semiconductor substrate, and a step of pattern-forming this multi-layer structure by selective etching. A method of manufacturing a semiconductor memory device, comprising: a step of removing the insulating film by etching; and a step of removing a sharp corner of an edge of the conductive film by etching. 6. A method of forming a storage node according to claim 4, wherein a step of forming a multi-layer structure including a first conductive film sandwiching an insulating film on a semiconductor substrate, and a pattern formation of this multi-layer structure by selective etching. And a step of removing the insulating film by etching, and a step of forming a second conductive film that covers an edge of the first conductive film. 7. A method of forming a storage node according to claim 4, wherein a step of forming a multilayer structure including a conductive film sandwiching an insulating film on a semiconductor substrate, and a step of patterning the multilayer structure by selective etching. A method for manufacturing a semiconductor memory device, comprising: a step of removing the insulating film by etching; a step of forming an oxide film on the surface of the conductive film; and a step of removing the oxide film by etching. .