JP3125353B2 - Semiconductor storage device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device such as a stack type dynamic random access memory (DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, DRAMs are steadily becoming more highly integrated.
A method of three-dimensionally forming a capacitance forming part has been proposed. Among them, a stacked DRAM in which a capacitance forming section is stacked on the upper part of a substrate and has a storage node increases the capacity, and therefore, the reference document T.Ema et al. "3-Dimensional Stacked Cap
acitor Cell for 16M and 64M DRAMs "IEEE International
al Electron Device MeetingTechical Digest, p592-59
Various structures are proposed in 5, Dec. 1988 and the like.

FIG. 5 is a process sectional view of a conventional semiconductor device having a storage node and a method of manufacturing the same. FIG. 5 (a)
As shown in FIG. 1, an element isolation insulating film 2 and a word line 3 serving as a gate of a switching transistor are formed on a semiconductor substrate 1.
Is formed to form the active region 4 of the switching transistor, and then, as shown in FIG.
-B, a SiN film, a first oxide film 6-A, a first conductive film 7-A, a polysilicon film, a second oxide film 6-B
Are sequentially deposited, and then a contact window 8 reaching the active region of the switching transistor is opened by anisotropic etching. Polysilicon is deposited thereon as the second conductive film 7-B as shown in FIG. 3C, and a resist pattern 9 is formed. Using this resist pattern 9 as a mask, RIE (Reactive Ion) as shown in FIG.
The second conductive film 7-B, the second oxide film 6-B, the first conductive film 7-A, and the first oxide film 6-
After sequentially etching A, the first oxide film 6-A and the second oxide film 6-B are etched with an HF-based etchant to form the storage node 10. Next, as shown in FIG. 1E, a dielectric film 11 composed of a multilayer film of SiO2 and SiN is formed on the surface of the storage node 10, and a third conductive film 12 is formed via the dielectric. Deposition is performed to form a cell plate, and then a bit line 13 is formed.

[0004]

In such a conventional semiconductor device and its manufacturing method, since the RIE method is used when forming the storage node, as shown in FIG. A sharp corner is formed at the end of the gate 10. At a steep angle at the end of the storage node, there is a problem that an electric field is concentrated as shown in FIG. 6B and dielectric breakdown of the dielectric film 11 is likely to occur. Further, at this steep angle, when oxidizing at about 850 ° C. when forming the dielectric film, the reference document Extended
Abstructs of the 16th (1984 International) Confere
nce on Solid State Devices and Materials, Kobe, 198
Due to the horn phenomenon as shown in 4, pp. 475-478, a steeper angle will be generated. Further, even in a structure other than the multi-fin type stacked DRAM, a steep corner exists, and it is difficult to manufacture.

FIG. 6B shows a steep angle of 90 °.
° figure is shown. The electric field applied to the dielectric film varies depending on the steep angle. FIG. 7 shows the relationship between this angle and the electric field strength concentrated on the angle. In FIG. 7, the calculation is performed assuming that the electric field strength of the flat portion is 1. As shown in FIG. 7, the electric field concentrates as the angle becomes smaller, and the dielectric film of the dielectric film is easily broken. FIG. 8 is a cross-sectional view when a DRAM having the same structure is miniaturized. As is clear from FIG. 8, as the miniaturization proceeds, the angle of the storage node 10 becomes smaller (θ ₁ > θ ₂ > θ ₃ ), and dielectric breakdown of the dielectric film easily occurs from the relationship of FIG. In addition, as the miniaturization advances, the capacity of the cell becomes smaller. To compensate for this, it is necessary to form a storage node having a larger surface area. However, a steep corner including a multi-fin type increases. Therefore, also from this meaning, dielectric breakdown of the dielectric film easily occurs.

The present invention solves the above-mentioned problems, and provides a semiconductor memory device which does not have a sharp angle at an end of a storage node and is less likely to cause dielectric breakdown of a dielectric film, and a method of manufacturing the same. The purpose is to:

[0007]

A semiconductor memory device according to the present invention comprises a multi-fin type storage node, a capacitance insulating film formed on the surface of the storage node, and a plate electrode formed on the capacitance insulating film. a semiconductor memory device having a storage capacity which is constituted by the said storage node, if angular corners
First conductive film having an irregular shape, and the first conductive film
Of the second conductive film covering the corners of the second conductive film.
The present invention is characterized in that all corners present in the multiple fins of the storage node are rounded due to the conductive film .

[0008]

According to the first, second and third methods of manufacturing a semiconductor memory device of the present invention, a multi-fin type storage node, a capacitor insulating film formed on the storage node, and a A method of manufacturing a semiconductor memory device having a storage capacitor constituted by a formed plate electrode, wherein the method of forming the storage capacitor is performed by using the multi-fin type device comprising a first conductive film on a semiconductor substrate. Forming a storage node, forming roundness in all corners present in the multiple fins of the storage node, and forming the capacitor insulating film on the surface of the multiple fins of the storage node having a rounded corner. And a step of forming a plate electrode on the capacitive insulating film .

[0010] A first method of manufacturing a semiconductor memory device according to the present invention.
Is a method of manufacturing a semiconductor memory device according to the first aspect,
Is formed of a polysilicon film containing impurities,
The step of forming roundness in all corners present in the multiple fins of the storage node is performed by isotropically etching the polysilicon film containing the impurity using a gas containing either fluorine, bromine, or chlorine. It is characterized by.

[0011] A second method of manufacturing a semiconductor memory device according to the present invention.
In the method for manufacturing a semiconductor memory device, the step of forming roundness in all corners present in the multiple fins of the storage node includes the step of forming a second conductive film covering a corner of the first conductive film. It is characterized by being formed by forming.

A third method of manufacturing a semiconductor memory device according to the present invention.
In the method for manufacturing a semiconductor memory device, the step of forming roundness in all corners existing in the multiple fins of the storage node includes the step of: forming an oxide film on the surface of the first conductive film at an oxidation temperature of 1000 ° C. or more. Is formed, and then the oxide film is removed.

[0013]

According to the present invention, the storage node having all the rounded corners according to the above-mentioned configuration prevents the electric field from being concentrated on the dielectric film, thereby preventing the dielectric film from causing dielectric breakdown. Can be.

[0014]

(Embodiment 1) FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device according to a first embodiment. 1 (a) to FIG.
Up to (d), it is basically the same as FIGS. 5 (a) to 5 (d) of the conventional example, but will be described in more detail.

In FIG. 1A, an oxide film of about 400 nm is formed as a semiconductor substrate 1 on a p-type silicon substrate as an element isolation insulating film 2 by a LOCOS method, and a word line 3 serving as a gate of a switching transistor is formed. Is formed, and P and As are ion-implanted as an active region 4 of the switching transistor to form an n-layer, and then an interlayer insulating film 5-A is formed as shown in FIG.
After depositing 0 nm BPSG (Borondoped Phospho-Silicate Glass) by normal pressure CVD and flattening by heat treatment, an approximately 20 nm SiN film is deposited as an interlayer insulating film 5-B by CVD, and then the first oxide film 6-6. An oxide film containing P (phosphorus) as A, a polysilicon film containing P as the first conductive film 7-A, and an oxide film containing P as the second oxide film 6-B are sequentially deposited by CVD. Thereafter, a resist pattern is formed by a usual photolithography method, and a contact window 8 reaching the active region 4 of the switching transistor is formed.
Is opened by anisotropic etching, for example, RIE.
In this embodiment, the first oxide film 6-A and the second oxide film 6-B
Is etched with a mixed gas of CHF ₃ and O ₂ , and the first conductive material 7-A is etched with a mixed gas of HBr and HCl.

In FIG. 1C, polysilicon containing P is deposited as a second conductive film 7-B, and a resist pattern 9 is formed. Using this resist pattern 9 as a mask, the first anisotropic etching using RIE as shown in FIG. 3D, for example, the second conductive using RIE using HBr gas as a main component. The film 7-B and the first conductive film 7-A are formed by using RI using CHF ₃ + O ₂ -based gas.
After the second oxide film 6-B and the first oxide film 6-A are sequentially etched by the method E, the first oxide film 6-A and the second oxide film 6-B are etched with an HF-based etchant. The storage node 10 is formed by etching. In this embodiment, the first conductive film 7-A and the second conductive film 7-B are P
Was deposited to a thickness of about 200 nm. Where P
The reason for using polysilicon containing impurities is that polysilicon containing impurities can be easily deposited to fill the contact window 8 by a low pressure CVD method or the like, and that F (fluorine) is used.
Alternatively, it can be easily etched by a gas containing at least either Br (bromine) or Cl (chlorine), and has excellent compatibility with the conventional technology.

Next, in FIG. 1E, a resist pattern 9 is shown.
After the removal, the storage node 10 which is a feature of the present invention is isotropically etched. In this embodiment, ECR (Electron Cyc
Using the SF ₆ gas flow rate: 50 sccm, pressure: 7 Pa, micro (μ) wave: 220 mA, about 10 nm was etched using a lotron resonance method to remove all steep corners of the memory node 10. In this embodiment, a multi-fin type storage node is used. However, the storage node having any structure, such as a case where an n-layer fin type or cylindrical storage node is used, is subjected to isotropic etching to achieve all steepness. Corners can be removed.

Next, as in the conventional example, in FIG.
On the surface of the storage node 10, SiO ₂ is formed as a dielectric film 11 at a thickness of about 2 nm and SiN is formed at a thickness of about 5 nm by a low pressure CVD method. 200 nm of polysilicon film containing impurities such as P
To form a cell plate, and then a bit line 13 is formed.

The steepest part of the storage node having all the rounded corners becomes the corner where three surfaces are gathered when the shape of the storage node is a rectangular parallelepiped. However, in general, the radius of curvature of the corner of the storage node viewed from above the silicon substrate is 25 due to the resolution limit of the photography technology and the like.
There is more than 00Å. Furthermore, since the capacitance insulating film that is usually used is 100 ° or less when converted into a thermal oxide film, it can be said that the capacitor insulating film is sufficiently rounded with respect to the capacitance insulating film. Therefore, the electric field concentration at the corner of the storage node can be considered in two dimensions as shown in FIG. In this case, assuming that charges are uniformly distributed also at the corners, the electric field concentration at the corners is inversely proportional to the ratio of the outer circumference to the inner circumference of the capacitive insulating film.

FIG. 10 shows the capacitance insulating film thickness T with respect to the ratio of the electric field intensity Eflat at the flat portion to the electric field intensity Ecorner at the corner portion.
The relationship between _ox and the ratio of the radius of curvature r of the corner is shown. Generally, by suppressing the electric field concentration to about 1.25 times that of the flat portion, the breakdown of the capacitor insulating film can be reduced. FIG.
In this case, it is understood that in this case, it is necessary to provide a relative curvature radius of four times the film thickness of the capacitive insulating film. Further, when the thickness is set to be 1.2 times or less of the flat portion, the relative curvature radius of 5 times the thickness of the capacitor insulating film is set. It is necessary to have a relative radius of curvature.

[0021] In the above first embodiment was used SF ₆ gas at the ECR as isotropic etching, CF _4, H
A similar effect can be obtained by using at least a gas containing either F or Br or Cl such as Br or HCl. Furthermore, etching methods other than the ECR method,
For example, a similar effect can be obtained by a triode method, a downflow method, or an RIE method under conditions where side etching is performed. Further, the isotropic etching can be performed with a liquid containing hydrofluoric nitric acid as a main component.

In FIG. 1B, the first conductive film 7
Although -A shows a case of one set, a plurality of sets may be further stacked via an oxide film.

(Embodiment 2) FIG. 2 is a process sectional view of a method of manufacturing a semiconductor device according to a second embodiment. FIG. 2A shows FIG.
This corresponds to (d), and the steps up to that are exactly the same as those in FIG. That is, the feature of the second embodiment is that the second anisotropic etching is performed after the resist pattern 8 is removed as shown in FIG. In this embodiment, the etching was performed by the RIE method at an HBr gas flow rate of 60 sccm, an HCl gas flow rate of 20 sccm, a pressure of 15 Pa, and an RF power of 150 W to about 10 nm. At this time, the memory node 1 is generated due to the sputtering effect.
The tendency to be etched so as to remove a steep 0 angle was used. The reason why the above-described gas system is used in the present embodiment is to emphasize the effect of rounding corners by utilizing the reaction between polysilicon and gas. Next, in FIG.
A dielectric film 11 is formed on the surface of the storage node 10, a third conductive film 12 is formed through the dielectric film 11, and then a bit line 13 is formed.

In this embodiment, a mixed gas of HBr and HCl is used by the RIE method for the second anisotropic etching, but it contains any one of F, Br and Cl such as CF ₄ , HBr and HCl. A similar effect can be obtained by using at least a gas. Similar effects can be obtained with a sputtering gas such as Ar. And R
An etching method other than the IE method, for example, an ECR method to which RF (high frequency) is applied is also possible.

(Embodiment 3) FIG. 3 is a process sectional view of a method of manufacturing a semiconductor device according to a third embodiment. That is, FIG.
(A) corresponds to FIG. 1 (d), and the steps up to that are exactly the same as in FIG. That is, a process which is a feature of the third embodiment will be described.

In FIG. 2B, after removing the resist pattern 9, a fourth conductive film 14 is deposited. Normally, when the fourth conductive film 14 is deposited on the storage node 10, the corners of the storage node 10 are deposited with rounded convex portions and concave portions. The coverage of the fourth conductive film 14 is uniform (1:
In the case of 1), the deposited film thickness has a radius of curvature, and the film thickness of the fourth conductive film 14 may be set to be at least four times the film thickness of the capacitor insulating film. In the present embodiment, the second conductive film
As in the case of the conductive film 7-B, polysilicon containing P was deposited to a thickness of about 70 nm. The thickness of the fourth conductive film 14 corresponds to ten times the thickness of the capacitance insulating film. Here, the reason why a film similar to the second conductive film 7-B is used as the fourth conductive film 14 is that the etching rate in the next step is set to be equal to the fourth conductive film 14 and the second conductive film 7-B. This is for preventing the formation of a sharp angle due to over-etching by making the same for the film 7-B.

Next, in FIG. 3C, the fourth conductive film 14 is formed.
Is removed by anisotropic etching to remove portions other than the storage node 10, and the storage node 10 is formed again. At this time, the fourth
The shape of the uppermost rounded corner of the storage node 10 when the conductive film 14 is deposited is maintained. Next, FIG.
As shown in FIG. 1, a dielectric film 11 is formed on the surface of the storage node 10 as in the conventional example, and a third conductive film 12 is formed through the dielectric film 11 to form a cell plate.
Form 3

In this embodiment, the second conductive film 7-B
Although the same material is used for the fourth conductive film 14 and the fourth conductive film 14, different materials may be used.

(Embodiment 4) FIG. 4 is a process sectional view of a method of manufacturing a semiconductor device according to a fourth embodiment. That is, FIG.
(A) corresponds to FIG. 1 (d), and up to that step is the same as FIG. That is, a process which is a feature of the fourth embodiment will be described. That is, as shown in FIG. 2B, after the resist pattern 9 is removed, the storage node 1 is removed.
Oxidizes 0. At this time, if oxidized at a temperature of 900 ° C. or less, a sharper angle is generated due to the horn phenomenon. However, by setting the oxidation temperature to 1000 ° C. or higher, the oxide film 15 is oxidized so that the sharp corners are rounded. In this embodiment, oxidation was performed at 1100 ° C. to about 50 nm.

Next, in FIG. 3C, the oxide film 15 is made of an HF type.
And removed with an etching solution. Removal process of this oxide film
Is C even when wet etching is used as in this embodiment.
HF _ThreeIsotropic plasma etching method using such gases
The same effect can be obtained by using. Next, FIG.
As described above, the dielectric film 1 is formed on the surface of the storage node 10 as in the conventional example.
1 and a third conductive film via the dielectric film 11
12 to form a cell plate, followed by a bit line 13
To form

In the first, second, third and fourth embodiments, polysilicon containing P as an impurity is used for the first and second conductive films, but n-type impurity such as As is used. Should be fine. Further, another conductive film such as W may be used.
Further, the first and second conductive films may be made of different materials.

In each of the embodiments, a stacked DRAM having a double fin structure is used. However, an n-fold fin type DRAM may be used, and other stacked DRAMs such as a cylindrical type as shown in FIG. The effect is obtained. Further, although a p-type silicon substrate is used as the semiconductor substrate 1, another semiconductor substrate such as GaAs may be used. In addition, as a dielectric film,
Although a multilayer film of SiN is used, other dielectric films such as Si02, SiN, and TaO may be used. Further, in each embodiment, the same effect can be obtained even if the p-type and the n-type are configured in reverse.

[0033]

As is clear from the above description, according to the present invention, it is possible to provide a semiconductor device in which the corner of the storage node can be rounded and dielectric breakdown of the dielectric film does not occur, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a process sectional view of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 5 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a schematic view showing an electric field applied to a dielectric film in a conventional semiconductor device.

FIG. 7 is a characteristic diagram of an angle of a storage node and a relative electric field intensity.

FIG. 8 is a sectional view of a DRAM using different design rules.

FIG. 9 is a schematic diagram illustrating a radius of curvature of a storage node and a thickness of a capacitor insulating film;

FIG. 10 is a diagram showing the relationship between the ratio of the electric field intensity Eflat of a flat portion and the electric field intensity Ecorner of a corner portion to the ratio of the thickness T _ox of the capacitive insulating film to the radius of curvature r of the corner portion.

FIG. 11 is a sectional view of a cylindrical stack type DRAM.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 4 active region 7-A first conductive film 7-B second conductive film 10 storage node 11 dielectric film 12 third conductive film

Continuation of the front page (56) References JP-A-1-147857 (JP, A) JP-A-1-96950 (JP, A) JP-A-62-185353 (JP, A) JP-A-2-95421 (JP) JP-A-2-291162 (JP, A) JP-A-3-11629 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (4)

(57) [Claims] 1. A semiconductor memory device having a storage capacitor composed of a multi-fin type storage node, a capacitor insulating film formed on a surface of the storage node, and a plate electrode formed on the capacitor insulating film. Wherein the storage node has a first shape with a corner having a square shape.
A conductive film, and a second conductive film covering a corner of the first conductive film.
A semiconductor memory device comprising a conductive film, wherein the second conductive film has a rounded shape in all corners present in the multiple fins of the storage node. 2. A multi-fin type storage node, and said storage
A capacitor insulating film formed on the node;
With a storage capacitor composed of a plate electrode
A method of forming a storage capacitor, the method comprising: forming a first storage capacitor on a semiconductor substrate;
Forming the multi-fin type storage node made of a conductive film
And present in the multiple fins of the storage node
Forming roundness in all corners, and forming roundness in the corners
On the surface of the multiple fins of the storage node
Forming an edge film; and forming a plate electrode on the capacitive insulating film.
Forming a pole, wherein the first conductive film is made of a polysilicon film containing an impurity, and the step of forming roundness in all corners present in the multiple fins of the storage node includes the step of removing the impurity. A method of manufacturing a semiconductor memory device, comprising: performing isotropic etching using a gas containing any of fluorine, bromine, and chlorine on a polysilicon film containing the same. 3. A multi-fin type storage node, and said storage
A capacitor insulating film formed on the node;
With a storage capacitor composed of a plate electrode
A method of forming a storage capacitor, the method comprising: forming a first storage capacitor on a semiconductor substrate;
Forming the multi-fin type storage node made of a conductive film
And present in the multiple fins of the storage node
Forming roundness in all corners, and forming roundness in the corners
On the surface of the multiple fins of the storage node
Forming an edge film; and forming a plate electrode on the capacitive insulating film.
Forming a second conductive film covering a corner of the first conductive film, wherein forming a rounded corner at an entire corner present in the multiple fins of the storage node. A method for manufacturing a semiconductor memory device. 4. A multi-fin type storage node and said storage
A capacitor insulating film formed on the node;
With a storage capacitor composed of a plate electrode
A method of forming a storage capacitor, the method comprising: forming a first storage capacitor on a semiconductor substrate;
Forming the multi-fin type storage node made of a conductive film
And present in the multiple fins of the storage node
Forming roundness in all corners, and forming roundness in the corners
On the surface of the multiple fins of the storage node
Forming an edge film; and forming a plate electrode on the capacitive insulating film.
Forming a pole in the multiple fins of the storage node, wherein the step of forming a rounded corner on the entire corner present in the multiple fins of the storage node reduces the surface of the first conductive film by 100%.
A method for manufacturing a semiconductor memory device, comprising: forming an oxide film at an oxidation temperature of 0 ° C. or higher, and removing the oxide film.