KR100269609B1 - Capacitor Formation Method - Google Patents

Capacitor Formation Method Download PDF

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KR100269609B1
KR100269609B1 KR1019970067204A KR19970067204A KR100269609B1 KR 100269609 B1 KR100269609 B1 KR 100269609B1 KR 1019970067204 A KR1019970067204 A KR 1019970067204A KR 19970067204 A KR19970067204 A KR 19970067204A KR 100269609 B1 KR100269609 B1 KR 100269609B1
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insulating layer
layer
forming
etching
implanted
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KR19990048482A (en
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류종암
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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Abstract

PURPOSE: A method for forming a capacitor is provided to increase a capacitance by increasing a surface area of a storage electrode, and simplifies a fabrication process. CONSTITUTION: A first insulating layer and a pure second insulating layer are alternately deposited formed on a semiconductor substrate(200) including an impurity area. F-ion is implanted in the first insulating layer. F-ion is not implanted in the second insulating layer. The first insulating layer and the second insulating layer are wet etched, and a contact hole partially exposes the impurity to remain the first insulating layer between the second insulating layers. A polysilicon layer covers a total structure, and its one part corresponding to the first insulating layer is etched with the first and second insulating layers, thereby forming a polysilicon layer. The second insulating layer is removed by using the polysilicon layer as a mask, thereby forming a storage electrode(230).

Description

캐패시터 형성방법Capacitor Formation Method

본 발명은 캐패시터(capacitor) 형성방법에 관한 것으로, 특히 표면적을 증가시키어 축전용량(capacitance)을 증대시키고 또한, 그 제조공정을 단순화하기에 적당한 반도체 소자의 캐패시터의 스토리지전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor, and more particularly to a method of forming a storage electrode of a capacitor of a semiconductor device suitable for increasing the surface area to increase the capacitance and simplifying the manufacturing process.

반도체소자의 고집적화에 따라 셀면적이 축소되어도 캐패시터가 일정한 축전용량을 갖도록 축전밀도를 증가시키기 위한 많은 연구가 진행되고 있다.Many studies have been conducted to increase the storage density so that capacitors have a constant capacitance even with a reduced cell area due to high integration of semiconductor devices.

이 축전밀도를 증가시키기 위해서는 캐패시터를 적층하거나 또는 트렌치를 이용하여 3차원 구조로 형성하는 방법 등이 있다.In order to increase the storage density, there is a method of stacking capacitors or forming a three-dimensional structure using a trench.

상기 3차원 구조를 갖는 캐패시터 중 적층 구조를 갖는 것은 제조공정이 용이하고 대량 생산성에 적합한 구조로서 축전 용량을 증대시키는 동시에 알파입자에 의한 전하 정보 혼란에 대하여 면역성을 갖는다.The laminated structure among the capacitors having the three-dimensional structure is a structure that is easy to manufacture and suitable for mass productivity, while increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles.

적층 캐패시터는 스토리지전극의 형태에 따라 2중 적층구조, 핑거(finger)구조 또는 크라운(crown)구조 등으로 구별된다.The stacked capacitors are classified into a double stacked structure, a finger structure, or a crown structure according to the shape of the storage electrode.

도 1a 내지 도 1e 는 종래 기술에 따른 일반적인 캐패시터 제조공정도이다.1A to 1E are general capacitor manufacturing process diagrams according to the prior art.

도면에는 도시되어 있지는 않지만, 반도체기판(100)은 트랜지스터가 형성된 상태이다. 즉, 반도체기판(100) 상에는 소자의 활성영역과 필드영역을 한정하는 필드산화층이 형성되어져 있고, 소자의 활성영역 상에 게이트산화층이 개재된 게이트전극이 형성되어져 있으며, 이 게이트전극 양측의 활성영역에 소오스/드레인(source/drain)영역으로 이용되는 불순물 확산영역이 존재하는 트랜지스터(transistor)가 형성되어져 있다.Although not shown, the semiconductor substrate 100 is in a state where a transistor is formed. That is, a field oxide layer defining an active region and a field region of the device is formed on the semiconductor substrate 100, and gate electrodes having a gate oxide layer interposed therebetween are formed on the active region of the device, and active regions on both sides of the gate electrode are formed. A transistor is formed in which an impurity diffusion region used as a source / drain region exists.

도 1a 를 참조하면, 상술한 구조의 전표면에 화학기상증착(Chemical Vapor Deposition: 이하 CVD라 칭함) 방법으로 산화실리콘을 성장시키어 제 1절연층(102)을 형성하고, 그 상부에 제 1다결정실리콘층(104)을 순차적으로 적층하여 형성한다. 이 제 1다결정실리콘층(104) 상에 다시 산화실리콘을 증착하여 제 2절연층(106)을 형성한다.Referring to FIG. 1A, silicon oxide is grown on the entire surface of the structure described above by chemical vapor deposition (CVD) to form a first insulating layer 102, and a first polycrystal is formed thereon. The silicon layer 104 is formed by stacking sequentially. Silicon oxide is again deposited on the first polysilicon layer 104 to form a second insulating layer 106.

그리고 제 2절연층(106) 상에 포토레지스트(PR: photoresist)를 도포한 후, 노광 및 현상하여 불순물영역(도면에는 도시되지 않음)과 대응되는 부위가 노출되도록 패터닝하여 제 1마스크패턴(107)을 형성한다.After applying a photoresist (PR) on the second insulating layer 106, the photoresist (PR) is exposed and developed to pattern the first mask pattern 107 so as to expose portions corresponding to the impurity regions (not shown). ).

도 1b 를 참조하면, 이 제 1마스크패턴(107)을 식각용 마스크로 이용하여 제 2절연층(106) 및 제 1다결정실리콘층(104) 및 제 1절연층(102)을 제거하여 반도체기판(100)의 일부를 노출시키는 콘택홀(H1)을 형성한다.Referring to FIG. 1B, the second insulating layer 106, the first polysilicon layer 104, and the first insulating layer 102 are removed by using the first mask pattern 107 as an etching mask. A contact hole H1 exposing a portion of the 100 is formed.

도 1b를 참조하면, 제 1마스크패턴(107)을 제거한다.Referring to FIG. 1B, the first mask pattern 107 is removed.

잔류된 제 2절연층(106) 상에 콘택홀(H1)을 덮도록 제 2다결정실리콘층(108)을 형성한다. 그리고 제 2다결정실리콘층(108) 상에 상술한 방법과 마찬가지 방식으로, 포토레지스트를 도포 및 현상, 노광하여 콘택홀(H1)과 대응된 부위를 덮도록 패터닝하여 제 2마스크패턴(110)을 형성한다.The second polysilicon layer 108 is formed on the remaining second insulating layer 106 to cover the contact hole H1. The second mask pattern 110 is formed on the second polysilicon layer 108 in the same manner as described above by applying, developing, and exposing a photoresist to pattern a portion corresponding to the contact hole H1. Form.

도 1c를 참조하면, 이 제 2마스크패턴(110)을 식각용 마스크로 이용하여 제 2다결정실리콘층(108) 및 제 2절연층(106) 및 제 1다결정실리콘층(104) 및 제 1절연층(102)를 제거함으로써 스토리지전극이 형성될 외각을 패터닝한다.Referring to FIG. 1C, using the second mask pattern 110 as an etching mask, the second polysilicon layer 108 and the second insulating layer 106, and the first polycrystalline silicon layer 104 and the first insulating layer are used. By removing the layer 102, the outer surface on which the storage electrode is to be formed is patterned.

도 1d를 참조하면, 제 2마스크패턴(110)을 마스크로 하여 습식식각 방법으로 산화실리콘인 제 2절연층(106) 및 제 1절연층(102)을 제거하여 핀구조의 스토리지전극(130)을 형성한다. 이 후에, 제 2마스크패턴(110)을 제거한다.Referring to FIG. 1D, the second insulating layer 106 and the first insulating layer 102, which are silicon oxides, are removed by a wet etching method using the second mask pattern 110 as a mask to form a finned storage electrode 130. To form. After that, the second mask pattern 110 is removed.

도면에 도시되지 않았지만, 스토리지전극(130) 상에 질화실리콘 등을 얇게 성장시키어 유전체를 형성하고, 그 상부에 다결정실리콘을 증착하여 플레이트전극을 형성함으로써 캐패시터의 제조를 완료한다.Although not shown in the figure, a silicon nitride or the like is thinly grown on the storage electrode 130 to form a dielectric, and polycrystalline silicon is deposited thereon to form a plate electrode to complete the manufacture of the capacitor.

상술한 바와 같이, 종래에는 산화실리콘층 및 다결정실리콘층을 연속적으로 다층 적층한 후, 식각선택비를 이용하여 산화실리콘층을 습식식각함으로써 캐패시터의 핀 구조의 스토리지전극을 패터닝하였다. 즉, 제 2다결정실리콘층 식각 → 산화실리콘인 제 2절연층 식각→ 제 1다결정실리콘층 식각 →산화실리콘인 제 1절연층 식각 순으로 각각 제거되었다.As described above, conventionally, after the silicon oxide layer and the polycrystalline silicon layer are successively laminated in multiple layers, the storage electrode having a fin structure of the capacitor is patterned by wet etching the silicon oxide layer using an etching selectivity. That is, the second polysilicon layer etch → the second insulating layer etched silicon oxide → the first polycrystalline silicon layer etch → the first insulating layer etched silicon oxide.

따라서, 종래의 캐패시터 제조방법에서는 산화실리콘층과 다결정실리콘층을 각각 식각함에 따라, 한 장비 내에서 동시에 진행하는 데 어려움이 있으며, 그에 따라 공정시간이 지연 및 공정이 복잡해지는 문제점이 있었다.Therefore, in the conventional capacitor manufacturing method, as the silicon oxide layer and the polycrystalline silicon layer are etched, respectively, it is difficult to proceed simultaneously in one equipment, and thus there is a problem that the process time is delayed and the process is complicated.

또한, 종래기술에서는 캐패시터의 스토리지전극의 축전용량을 증가시키는 데에는 그 한계가 있었다.In addition, in the prior art, there is a limit to increasing the capacitance of the storage electrode of the capacitor.

상기의 문제점을 해결하고자, 본 발명의 목적은 스토리지전극의 표면적을 증가시키어 축전용량을 증가시킬 수 있는 캐패시터 형성방법을 제공함에 있다.In order to solve the above problems, an object of the present invention is to provide a method of forming a capacitor that can increase the capacitance by increasing the surface area of the storage electrode.

본 발명의 다른 목적은 스토리지전극 제조공정이 단순화된 캐패시터 형성방법을 제공함에 있다.Another object of the present invention is to provide a method of forming a capacitor in which the storage electrode manufacturing process is simplified.

본 발명에서는 동일한 물질로 형성되되, 이온주입을 실시한 층과 그렇지 않은 층으로 구분하여 적층한 후, 이온주입을 실시한 층과 그렇지 않은 층 간의 식각비가 급격히 변화되어 선택적으로 식각되는 원리를 이용함으로써 한 번의 식각공정을 진행시킴에 따라 공정을 단순화하려는 것이다.In the present invention, the layer is formed of the same material, and divided into layers that are ion implanted and layers that are not implanted, and then the etching ratio between the layer implanted with the ion implantation and the layer that is not is rapidly changed and is selectively etched by using a principle of etching. As the etching process proceeds, the process is simplified.

또한, 본 발명에서는 스토리지전극 형성용 다결정실리콘층을 한 번 증착함으로써 그에 따른 식각공정을 줄임으로써 보다 제조공정을 단순화 및 스토리지전극의 표면적이 증가시키려는 것이다.In addition, the present invention is to simplify the manufacturing process and increase the surface area of the storage electrode by reducing the etching process according to the deposition of the polysilicon layer for forming the storage electrode once.

따라서, 본 발명의 캐패시터 형성방법은 불순물영역을 포함하는 트랜지스터가 형성된 반도체기판에 F 이온주입된 제 1절연층과 F 이온이 주입되지 않은 순수한 제 2절연층을 n 번(n 은 자연수) 교번시키어 적층하여 형성하는 공정과, 제 1절연층과 제 2절연층을 습식식각하여 제 1절연층을 제 2절연층 사이에 일부 잔류되도록 불순물영역을 노출시키는 접촉홀을 형성하는 공정과, 상술한 구조 전면을 덮되, 제 1절연층과 대응된 부위가 제 1절연층과 제 2절연층과 함께 식각되도록 다결정실리콘층을 형성하는 공정과, 다결정실리콘층을 마스크로 제 2절연층을 제거하여 스토리지전극을 형성하는 공정을 구비한 것을 특징으로 한다.Therefore, in the capacitor formation method of the present invention, F is formed on a semiconductor substrate on which a transistor including an impurity region is formed. Ion implanted first insulating layer and F Forming a pure second insulating layer which is not implanted with ion by alternating n times (n is a natural number), and wet etching the first insulating layer and the second insulating layer to form a first insulating layer between the second insulating layers. Forming a contact hole exposing the impurity region so as to remain at a portion thereof; and covering the entire surface of the structure, wherein the polysilicon layer is etched so that the portion corresponding to the first insulating layer is etched together with the first insulating layer and the second insulating layer. And forming a storage electrode by removing the second insulating layer using the polysilicon layer as a mask.

불순물영역을 포함하는 트랜지스터가 형성된 반도체기판에 제 1다결정실리콘층을 형성하는 공정과, 제 1다결정실리콘층 상에 F 이온주입된 제 1절연층과 이온주입되지 않은 제 2절연층을 n 번(n 은 자연수) 교번시키어 적층하여 형성하는 공정과, 제 2절연층과 제 1절연층과 다결정실리콘층을 상기 불순물영역이 덮이도록 식각하여 제 1절연층을 제 2절연층 사이에 일부 잔류시키는 공정과, 구조 전면을 덮되, 제 1절연층과 대응된 부위가 노출되도록 제 2다결정실리콘층을 형성하는 공정과, 제 2다결정실리콘층을 마스크로 제 1절연층과 제 2절연층을 식각하여 스토리지전극을 형성하는 공정을 구비한 것을 특징으로 한다.Forming a first polycrystalline silicon layer on a semiconductor substrate on which a transistor including an impurity region is formed; and F on the first polycrystalline silicon layer Forming an ion implanted first insulating layer and a non-ion implanted second insulating layer alternately n times (n is a natural number), and forming a second insulating layer, the first insulating layer, and a polysilicon layer; Etching the cover so as to partially leave the first insulating layer between the second insulating layers, forming a second polysilicon layer covering the entire structure of the structure and exposing a portion corresponding to the first insulating layer; And forming a storage electrode by etching the first insulating layer and the second insulating layer using the second polysilicon layer as a mask.

도 1a 내지 도 1d 는 종래 기술에 따른 캐패시터 제조공정도이고,1a to 1d is a manufacturing process diagram of a capacitor according to the prior art,

도 2a 내지 도 2g 는 본 발명의 제 1실시예로, 캐패시터 제조공정도이다.2A to 2G illustrate a capacitor manufacturing process according to a first embodiment of the present invention.

도 3a 내지 도 3g 는 본 발명의 제 2실시예로, 캐패시터 제조공정도이다.3A to 3G are diagrams illustrating a capacitor manufacturing process according to a second embodiment of the present invention.

도 4는 본 발명의 F 이온을 주입한 절연층과 F 이온을 함유하지 않은 절연층 간의 식각비를 비교한 그래프이다.4 is F of the present invention Insulation layer implanted with ions and F It is a graph comparing the etching ratio between the insulating layers containing no ions.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200, 300. 트랜지스터가 형성된반도체기판100, 200, 300. Semiconductor substrate with transistor

102, 106, 202, 206, 302, 305. 이온주입되지 않은 절연막102, 106, 202, 206, 302, 305. Non-ion implanted insulating film

201, 203, 301, 303. 이온주입된 절연막201, 203, 301, 303. Ion implanted insulating film

104, 108, 208,304, 308. 다결정실리콘층104, 108, 208, 304, 308. Polycrystalline silicon layer

107, 110, 204, 210, 306, 310. 마스크패턴107, 110, 204, 210, 306, 310. Mask pattern

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2g 는 본 발명의 제 1실시예로, 핀구조의 캐패시터 제조공정도이다. 그리고 도 4는 본 발명의 F 이온을 주입한 절연층과 F 이온을 함유하지 않은 절연층 간의 식각비를 비교한 그래프이다.2A to 2G are diagrams illustrating a capacitor manufacturing process of the fin structure according to the first embodiment of the present invention. And Figure 4 is F of the present invention Insulation layer implanted with ions and F It is a graph comparing the etching ratio between the insulating layers containing no ions.

도면에는 도시되지 않았지만, 반도체기판(200)은, 종래와 마찬가지로, 소자의 활성영역과 필드영역을 한정한 필드산화층이 있고, 소자의 활성영역 상에 게이트절연막이 개재된 게이트전극이 있으며, 이 게이트전극 양측의 활성영역에는 소오스/드레인영역으로 이용되는 불순물 확산영역이 있는 트랜지스터가 형성되어져 있다.Although not shown in the drawing, the semiconductor substrate 200 has a field oxide layer defining an active region and a field region of a device as in the prior art, and a gate electrode having a gate insulating film interposed therebetween on the active region of the device. Transistors having impurity diffusion regions used as source / drain regions are formed in active regions on both sides of the electrodes.

도 2a를 참조하면, 상술한 구조의 반도체기판(200) 전표면에 CVD 방법으로 산화실리콘을 증착한 후, F(fluorine)이온을 주입하여 불순물이 도핑된 제 1절연층(201)을 형성한다.Referring to FIG. 2A, after depositing silicon oxide on the entire surface of the semiconductor substrate 200 having the above-described structure by CVD, an F (fluorine) ion is injected to form a first insulating layer 201 doped with impurities. .

도 2b를 참조하면, 이 불순물이 도핑된 제 1절연층(201) 상에 산화실리콘을 증착하여 불순물이 도핑되지 않은 순순한 제 2절연층(202)을 형성한다.Referring to FIG. 2B, silicon oxide is deposited on the first insulating layer 201 doped with the impurity to form a pure second insulating layer 202 that is not doped with the impurity.

그리고, 이 제 2절연층(202)상에 산화실리콘을 증착한 후, F 이온을 주입하여 불순물이 도핑된 제 3절연층(203)을 형성한다.After depositing silicon oxide on the second insulating layer 202, F Ions are implanted to form a third insulating layer 203 doped with impurities.

도 2c를 참조하면, 제 3절연층(203) 상에 산화실리콘을 증착하여 불순물이 도핑되지 않은 순수한 제 4절연층(206)을 형성한다. 상기와 같은 방법대로, 각각의 제 1, 제 2, 제 3, 제 4절연층(201)(202)(203)(206)은 F 이온 주입된 산화실리콘층(201)(203)과 순수한 산화실리콘층(202)(206)을 교번하여 증착함으로써 형성된다.Referring to FIG. 2C, silicon oxide is deposited on the third insulating layer 203 to form a pure fourth insulating layer 206 that is not doped with impurities. As described above, each of the first, second, third, and fourth insulating layers 201, 202, 203, and 206 is F. The ion implanted silicon oxide layers 201 and 203 and the pure silicon oxide layers 202 and 206 are alternately deposited.

이어서, 제 4절연층(206) 상에 포토레지스트를 도포한 후, 노광 및 현상하여 불순물영역(도면에 도지되지 않음)과 대응된 부위가 노출되도록 패터닝하여 제 1마스크패턴(204)을 형성한다.Subsequently, after the photoresist is coated on the fourth insulating layer 206, the photoresist is exposed and developed to pattern the first mask pattern 204 by exposing the portions corresponding to the impurity regions (not shown in the drawing) to be exposed. .

도 2d를 참조하면, 이 제 1마스크패턴(204)을 식각용 마스크로 각각의 제 1, 제 2, 제 3, 제 4절연층(201)(202)(203)(206)을 BOE(Buffered Oxide Etchant) 식각용액을 사용하여 습식식각 방법으로 제거함으로써 반도체기판(200)의 일부위를 노출시키는 콘택홀(H2)을 형성한다.Referring to FIG. 2D, each of the first, second, third, and fourth insulating layers 201, 202, 203, and 206 is buffered by using the first mask pattern 204 as an etching mask. Oxide Etchant) is removed by a wet etching method using an etching solution to form a contact hole H2 exposing a portion of the semiconductor substrate 200.

이 때, F이온 주입된 산화실리콘층(201)(203)은 순수한 산화실리콘층(202)(206)에 비해 식각비가 크기 때문에 측면으로 과도하게 식각됨으로써, 도면에서와 같은 핀구조를 형성한다. 점선은 이상적인 식각부위를 나타내지만, 실제로는 습식액에 의해 이온주입된 제 1, 3절연층(201)(203) 뿐만 아니라, 그렇지 않은 절연층(202)(206)까지도 측면으로 식각된다.At this time, the silicon oxide layers 201 and 203 implanted with F ions are excessively etched to the side because the etching ratio is larger than that of the pure silicon oxide layers 202 and 206, thereby forming a fin structure as shown in the drawing. The dotted line shows the ideal etching site, but in practice, not only the first and third insulating layers 201 and 203 implanted with the wet liquid but also the insulating layers 202 and 206 that are not ionically implanted are laterally etched.

즉, 도 4에서 알 수 있듯이, F 이온을 주입한 절연층이 F 이온을 함유하지 않은 절연층보다 BOE 식각용액 내에서 식각비가 급격하게 커지는 것을 볼 수 있다. 그리고 F 이온농도에 따라 식각비 조정이 가능하므로 이온주입 조건 및 BOE 식각용액에서 식각되는 시간에 따라 캐패시터 형상 및 용량을 조절할 수 있다.That is, as can be seen in Figure 4, F Insulation layer implanted with ions is F It can be seen that the etching ratio is sharply increased in the BOE etching solution than the insulating layer containing no ions. And F Since the etching rate can be adjusted according to the ion concentration, the shape and capacity of the capacitor can be adjusted according to the ion implantation conditions and the time of etching in the BOE etching solution.

이 후에, 제 1마스크패턴(204)을 제거한다.After that, the first mask pattern 204 is removed.

도 2e를 참조하면, 상기 구조를 덮도록 제 1다결정실리콘층(208)을 형성하는 데, 이 제 1다결정실리콘층(208)은 스텝커버리지(step coverage)가 우수하므로, 제 2절연층(202)과 제 4절연층(206) 사이의 과도하게 식각된 부위까지도 덮는다.Referring to FIG. 2E, a first polysilicon layer 208 is formed to cover the structure, and since the first polysilicon layer 208 has excellent step coverage, the second insulating layer 202 is formed. ) And an excessively etched portion between the fourth insulating layer 206 and the fourth insulating layer 206.

도 2f를 참조하면, 제 1다결정실리콘층(208) 상에 상술한 방법과 마찬가지 방식으로, 포토레지스트를 도포 및 현상, 노광하여 콘택홀(H2)과 대응된 부위를 포함하도록 패터닝하여 제 2마스크패턴(210)을 형성한다. 이 제 2마스크패턴(210)은 잔류된 제 1, 제 3절연층(201)(203)은 포함되지 않도록 하며, 이 제 1, 제 3절연층(201)(203)은 이 후의 식각공정에서 모두 제거되도록 한다.Referring to FIG. 2F, a second mask is formed on the first polysilicon layer 208 in the same manner as described above by applying, developing, and exposing a photoresist to pattern the portion to correspond to the contact hole H2. The pattern 210 is formed. The second mask pattern 210 does not include the remaining first and third insulating layers 201 and 203, and the first and third insulating layers 201 and 203 are used in a subsequent etching process. Make sure everything is removed.

이 제 2마스크패턴(210)을 식각용 마스크로 이용하여 제 1다결정실리콘층(208) 및 제 4, 제 3, 제 2, 제 1절연층(206)(203)(202)(201)을 제거함으로써 이 후에 스토리지전극이 형성될 외각을 패터닝한다.Using the second mask pattern 210 as an etching mask, the first polysilicon layer 208 and the fourth, third, second, and first insulating layers 206, 203, 202, and 201 are used. By removing it, the outer shell on which a storage electrode is to be formed is subsequently patterned.

도 2g를 참조하면, 상술한 구조를 습식식각 방법으로 처리하여 측면에 잔류된 제 2, 제 4절연층(202)(206)을 제거시킴으로써 본 발명의 핀구조의 스토리지전극(230)을 형성한다. 이 후에, 제 2마스크패턴(210)을 제거한다.Referring to FIG. 2G, the fin structure of the fin structure of the present invention is formed by removing the second and fourth insulating layers 202 and 206 remaining on the side surface by treating the above structure by a wet etching method. . After that, the second mask pattern 210 is removed.

도면에 도시되지 않았지만, 이 후에 스토리지전극(230) 상에 질화실리콘 또는산화탄탈늄(Ta2O5) 또는 PZT(Pb(Zr Ti)O3) 또는 BST((Ba Sr)TiO3) 등의 고유전 물질 등을 이용하여 유전체를 형성하고, 그 상부에 다결정실리콘을 증착하여 플레이트전극을 형성함으로써 캐패시터의 제조를 완료한다.Although not shown in the drawings, a silicon nitride or tantalum oxide (Ta 2 O 5 ), PZT (Pb (Zr Ti) O 3 ), BST ((Ba Sr) TiO 3 ), or the like is formed on the storage electrode 230. A dielectric is formed using a high dielectric material and the like, and polycrystalline silicon is deposited thereon to form a plate electrode to complete the manufacture of the capacitor.

본 발명의 제 1실시예에서는, 반도체기판 상에 F 이온 주입을 진행시킨 산화실리콘층과 이온주입되지 않은 산화실리콘층을 교번하여 다층 적층시킨 후, 이 이온주입된 층과 그렇지 않은 층이 서로 식각비가 다르다는 점을 이용하여 핀구조의 스토리지전극을 형성한다. 캐패시터의 내부를 습식처리한 후, 외곽을 패터닝 및 이온주입되지 않은 산화실리콘층 습식식각하는 방법으로 외측으로 굴곡진 핀구조를 갖도록 형성한다.In the first embodiment of the present invention, F is provided on a semiconductor substrate. After the ion implanted silicon oxide layer and the non-ion implanted silicon oxide layer are alternately stacked, a finned storage electrode is formed using the difference in etching ratio between the ion implanted layer and the non-ion implanted layer. . After the inside of the capacitor is wet-treated, the outside is formed to have a fin structure that is bent outward by a method of wet etching the silicon oxide layer without patterning and ion implantation.

상기와 같은 방법대로 F 이온 주입을 진행시킨 산화실리콘층과 이온주입되지 않은 산화실리콘층을 교번하여 간단하게 다층 형성 및 식각이 가능하므로, 스토리지전극의 표면적이 증가되어 결국 캐패시터의 축전용량이 증대된다.F as above Since the silicon oxide layer which has undergone ion implantation and the silicon oxide layer which are not ion implanted can be alternately formed and easily etched, the surface area of the storage electrode is increased, and thus the capacitance of the capacitor is increased.

또한, 본 발명에서는 스토리지전극 형성용 다결정실리콘층을 한 번 증착함으로써 그에 따른 식각공정을 줄임으로써 보다 제조공정을 단순화할 수 있다.In addition, the present invention can simplify the manufacturing process by reducing the etching process according to the deposition of the polysilicon layer for forming the storage electrode once.

도 3a 내지 도 3g 는 본 발명의 제 2실시예로, 핀구조의 캐패시터의 제조공정도이다.3A to 3G illustrate a manufacturing process of a capacitor having a fin structure according to a second embodiment of the present invention.

도 3a를 참조하면, 반도체기판(300)은 소자의 활성영역과 필드영역을 한정한 필드산화층이 있고, 소자의 활성영역 상에 게이트절연막이 개재된 게이트전극이 있으며, 이 게이트전극 양측의 활성영역에는 소오스/드레인영역으로 이용되는 불순물 확산영역이 있는 트랜지스터가 형성되어져 있다.Referring to FIG. 3A, a semiconductor substrate 300 includes a field oxide layer defining an active region and a field region of a device, a gate electrode having a gate insulating film interposed therebetween, and an active region on both sides of the gate electrode. In the transistor, a transistor having an impurity diffusion region used as a source / drain region is formed.

상술한 구조의 반도체기판(300) 전표면에 제 1다결정실리콘층(304)을 형성한다. 그리고 제 1다결정실리콘층(304) 상에 산화실리콘을 증착한 후, F 이온을 주입함으로써 불순물이 도핑된 제 1절연층(301)을 형성한다.The first polysilicon layer 304 is formed on the entire surface of the semiconductor substrate 300 having the above-described structure. After depositing silicon oxide on the first polysilicon layer 304, F By implanting ions, the first insulating layer 301 doped with impurities is formed.

도 3b를 참조하면, 제 1절연층(301) 상에 산화실리콘을 증착하여 불순물이 도핑되지 않은 순수한 제 2절연층(302)을 형성한다. 그리고 제 2절연층(302) 상에 산화실리콘을 증착한 후, 전면에 F 이온을 주입함으로써 불순물이 도핑된 제 3절연층(303)을 형성한다.Referring to FIG. 3B, silicon oxide is deposited on the first insulating layer 301 to form a pure second insulating layer 302 which is not doped with impurities. After depositing the silicon oxide on the second insulating layer 302, F on the front By implanting ions, a third insulating layer 303 doped with impurities is formed.

도 3c를 참조하면, 제 3절연층(303) 상에 산화실리콘을 증착하여 불순물이 도핑되지 않은 순수한 제 4절연층(305)을 형성한다. 상술한 바와 같은 방법대로, 각각의 제 1, 제 2, 제 3, 제 4절연층(301)(302)(303)(305)은 F 이온 주입된 산화실리콘층(301)(303)과 순수한 산화실리콘층(302)(305)을 교번하여 증착함으로써 형성된다.Referring to FIG. 3C, silicon oxide is deposited on the third insulating layer 303 to form a pure fourth insulating layer 305 which is not doped with impurities. As described above, each of the first, second, third, and fourth insulating layers 301, 302, 303, 305 is F. The ion implanted silicon oxide layers 301 and 303 and the pure silicon oxide layers 302 and 305 are alternately deposited.

이어서, 제 4절연층(305) 상에 포토레지스트를 도포한 후, 노광 및 현상하여 불순물영역(도면에 도지되지 않음)과 대응된 부위가 포함되도록 패터닝하여 제 1마스크패턴(306)을 형성한다.Subsequently, after the photoresist is applied on the fourth insulating layer 305, the photoresist is exposed and developed to pattern the first mask pattern 306 to include portions corresponding to the impurity regions (not shown in the drawing). .

이 제 1마스크패턴(306)을 식각용 마스크로 이용하여 제 4, 제 3, 제 2, 제 1절연층(301)(302)(303)(305) 및 제 1다결정실리콘층(304)을 제거함으로써 이 후에 스토리지전극이 형성될 외각을 패터닝한다.Using the first mask pattern 306 as an etching mask, the fourth, third, second, and first insulating layers 301, 302, 303, 305, and the first polycrystalline silicon layer 304 are used. By removing it, the outer shell on which a storage electrode is to be formed is subsequently patterned.

도 3d를 참조하면, 제 1마스크패턴(306)을 다시 한번 식각용 마스크로 이용하여 제 4, 제 3, 제 2, 제 1절연층(301)(302)(303)(305)을 BOE 식각용액을 사용하여 습식식각 방법으로 제거함으로써 도면에서와 같이, 이온주입된 제 1절연층(301) 및 제 3절연층(303)이 양측면으로 과도하게 식각되어 핀구조를 이루게 된다.Referring to FIG. 3D, the fourth, third, second, and first insulating layers 301, 302, 303, and 305 are etched BOE using the first mask pattern 306 as an etching mask once again. By using a solution to remove by a wet etching method, as shown in the drawing, the ion-implanted first insulating layer 301 and the third insulating layer 303 are excessively etched on both sides to form a fin structure.

도 4에서 알 수 있듯이, F 이온이 주입된 제 1, 제 3절연층(301)(303)은 식각용액과의 반응성이 높아 빠르게 측면으로 침투되면서 측면으로 과도하게 식각이 진행된다. 그리고 F 이온농도에 따라 식각비 조정이 가능하므로 이온주입 조건 및 BOE 식각용액에서 식각되는 시간에 따라 캐패시터 형상 및 용량을 조절할 수 있다.As can be seen in Figure 4, F The first and third insulating layers 301 and 303 into which the ions are implanted have high reactivity with the etching solution and thus rapidly penetrate to the side and excessively etch the side. And F Since the etching rate can be adjusted according to the ion concentration, the shape and capacity of the capacitor can be adjusted according to the ion implantation conditions and the time of etching in the BOE etching solution.

도 3e 내지 도 3g 는 도 3d를 일부 확대한 도면이다.3E to 3G are partially enlarged views of FIG. 3D.

도 3e를 참조하면, 제 1마스크패턴(306)을 제거한다.Referring to FIG. 3E, the first mask pattern 306 is removed.

상기 핀구조 전면을 덮도록 제 2다결정실리콘층(308)을 형성한다. 이 제 2다결정실리콘층(308)은 스텝커버리지가 우수하기 때문에, 과도하게 식각된 제 1, 제 3절연층(301)(303)의 측면을 따라 덮고 있다.A second polysilicon layer 308 is formed to cover the entire fin structure. Since the second polysilicon layer 308 has excellent step coverage, the second polysilicon layer 308 is covered along the side surfaces of the first and third insulating layers 301 and 303 that are excessively etched.

이어서, 제 2다결정실리콘층(308) 상에 상술한 방법과 마찬가지 방식으로, 포토레지스트를 도포 및 현상, 노광하여 불순물영역(도면에 도시되지 않음)과 대응된 부위를 포함하도록 패터닝하여 제 2마스크패턴(310)을 형성한다. 이 제 2마스크패턴(310)은 잔류된 제 1, 제 3절연층(301)(303)과 대응된 부위가 노출되도록 형성시키어 이 후의 식각공정에서 모두 제거되도록 한다.Subsequently, the second mask is patterned on the second polysilicon layer 308 in the same manner as described above by applying, developing, and exposing the photoresist to pattern the region corresponding to the impurity region (not shown). The pattern 310 is formed. The second mask pattern 310 is formed so that the portions corresponding to the remaining first and third insulating layers 301 and 303 are exposed to be removed in the subsequent etching process.

도 3f를 참조하면, 제 2마스크패턴(310)을 식각용 마스크로 이용하여 제 2다결정실리콘층(308)의 일부를 제거한다.Referring to FIG. 3F, a portion of the second polysilicon layer 308 is removed using the second mask pattern 310 as an etching mask.

도 3g를 참조하면, 잔류된 제 2다결정실리콘층(308) 내부에 있는 제 4, 제 3, 제 2, 제 1절연층(305)(303)(302)(301)을 습식식각 방법으로 제거하여 본 발명의 핀구조의 스토리지전극(330)을 형성한다. 이 후에, 제 2마스크패턴(310)을 제거한다.Referring to FIG. 3G, the fourth, third, second, and first insulating layers 305, 303, 302, and 301 in the remaining second polysilicon layer 308 are removed by a wet etching method. As a result, the fin electrode storage electrode 330 is formed. After that, the second mask pattern 310 is removed.

도면에 도시되지 않았지만, 이 후에 스토리지전극(330) 상에 질화실리콘 또는산화탄탈늄(Ta2O5) 또는 PZT(Pb(Zr Ti)O3) 또는 BST((Ba Sr)TiO3) 등의 고유전 물질 등을 이용하여 유전체를 형성하고, 그 상부에 다결정실리콘을 증착하여 플레이트전극을 형성함으로써 캐패시터의 제조를 완료한다.Although not shown in the drawings, a silicon nitride or tantalum oxide (Ta 2 O 5 ), PZT (Pb (Zr Ti) O 3 ), BST ((Ba Sr) TiO 3 ), or the like is subsequently formed on the storage electrode 330. A dielectric is formed using a high dielectric material and the like, and polycrystalline silicon is deposited thereon to form a plate electrode to complete the manufacture of the capacitor.

상술한 바에서 살펴보았듯이, 본 발명의 제 2실시예에서는 제 1실시예에서와 마찬가지로, 반도체기판 상에 F 이온 주입을 진행시킨 산화실리콘층과 이온주입되지 않은 산화실리콘층을 교번하여 다층 적층시킨 후, 이 이온주입된 층과 그렇지 않은 층이 서로 식각비가 다르다는 점을 이용하여 핀구조의 스토리지전극을 형성한다. 캐패시터의 스토리지전극의 외곽을 먼저 패터닝한 후, 내부를 습식식각 처리하여 내측으로 굴곡진 핀형상을 갖도록 형성한다.As described above, in the second embodiment of the present invention, as in the first embodiment, F is placed on a semiconductor substrate. After the ion implanted silicon oxide layer and the non-ion implanted silicon oxide layer are alternately stacked, a finned storage electrode is formed using the difference in etching ratio between the ion implanted layer and the non-ion implanted layer. . The outer edge of the storage electrode of the capacitor is first patterned, and then the inside is wet etched to form a fin shape curved inwardly.

본 발명에서는 동일한 물질로 형성되되, 이온주입을 실시한 층과 그렇지 않은 층으로 구분하여 적층한 후, 이온주입을 실시한 층과 그렇지 않은 층 간의 식각비가 급격히 변화되어 선택적으로 식각되는 원리를 이용함으로써 식각공정 횟수를 줄이어 제조공정을 단순화한다.In the present invention, formed by the same material, but separated into a layer subjected to ion implantation and a layer not laminated, the etching process by using the principle that the etching ratio between the ion implanted layer and the other layer is rapidly changed to selectively etch the etching process Reduce the number of times to simplify the manufacturing process.

상술한 바와 같이, 본 발명의 캐패시터 제조방법에서는 F 이온주입을 실시한 산화실리콘층과 그렇지 않은 산화실리콘층을 교번하여 동일 필름을 적층시킴으로써 한 장비내에서 식각공정을 진행시킬 수 있어 전체 공정이 단순화되고, 또한, 스토리지전극의 표면적 증가로 캐패시터의 축전용량이 증대된다.As described above, in the capacitor manufacturing method of the present invention, F By stacking the same film by alternating the silicon oxide layer which has been implanted with ion and the silicon oxide layer which are not implanted, the etching process can be carried out in one equipment, and the overall process is simplified, and the capacitance of the capacitor is increased by increasing the surface area of the storage electrode. Is increased.

그리고 F 이온농도에 따라 식각비 조정이 가능하므로 이온주입 조건 및 BOE 식각용액에서 식각되는 시간에 따라 캐패시터 형상 및 용량을 조절할 수 있는 잇점이 있다.And F Since the etching rate can be adjusted according to the ion concentration, there is an advantage in that the capacitor shape and capacity can be adjusted according to the ion implantation conditions and the time of etching in the BOE etching solution.

Claims (2)

불순물영역을 포함하는 트랜지스터가 형성된 반도체기판에 F 이온주입된 제 1절연층과 F 이온이 주입되지 않은 순수한 제 2절연층을 n 번(n 은 자연수) 교번시키어 적층하여 형성하는 공정과,F on a semiconductor substrate on which a transistor including an impurity region is formed Ion implanted first insulating layer and F Forming a pure second insulating layer which is not implanted with ion by alternating n times (n is a natural number) and laminating them; 상기 제 1절연층과 상기 제 2절연층을 습식식각하여 상기 제 1절연층을 상기 제 2절연층 사이에 일부 잔류되도록 상기 불순물영역을 노출시키는 접촉홀을 형성하는 공정과,Wet etching the first insulating layer and the second insulating layer to form a contact hole exposing the impurity region to partially retain the first insulating layer between the second insulating layer; 상기 구조 전면을 덮되, 상기 제 1절연층과 대응된 부위가 상기 제 1절연층과 상기 제 2절연층과 함께 식각되도록 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer covering an entire surface of the structure, wherein a portion corresponding to the first insulating layer is etched together with the first insulating layer and the second insulating layer; 상기 다결정실리콘층을 마스크로 상기 제 2절연층을 제거하여 스토리지전극을 형성하는 공정을 구비한 캐패시터 형성방법.And removing the second insulating layer using the polysilicon layer as a mask to form a storage electrode. 불순물영역을 포함하는 트랜지스터가 형성된 반도체기판에 제 1다결정실리콘층을 형성하는 공정과,Forming a first polycrystalline silicon layer on a semiconductor substrate on which a transistor including an impurity region is formed; 상기 제 1다결정실리콘층 상에 F 이온주입된 제 1절연층과 이온주입되지 않은 제 2절연층을 n 번(n 은 자연수) 교번시키어 적층하여 형성하는 공정과,F on the first polycrystalline silicon layer Forming an ion-implanted first insulating layer and an ion-implanted second insulating layer by alternating n times (n is a natural number) and laminating them; 상기 제 2절연층과 상기 제 1절연층과 상기 다결정실리콘층을 상기 불순물영역이 덮이도록 식각하여 상기 제 1절연층을 상기 제 2절연층 사이에 일부 잔류시키는 공정과,Etching the second insulating layer, the first insulating layer, and the polysilicon layer to cover the impurity region to partially retain the first insulating layer between the second insulating layer; 상기 구조 전면을 덮되, 상기 제 1절연층과 대응된 부위가 노출되도록 제 2다결정실리콘층을 형성하는 공정과,Forming a second polysilicon layer covering the entire surface of the structure and exposing a portion corresponding to the first insulating layer; 상기 제 2다결정실리콘층을 마스크로 상기 제 1절연층과 상기 제 2절연층을 식각하여 스토리지전극을 형성하는 공정을 구비한 캐패시터 형성방법.And forming a storage electrode by etching the first insulating layer and the second insulating layer using the second polysilicon layer as a mask.
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