KR100652361B1 - Method for fabricating a semiconductor device using self aligned contact - Google Patents

Method for fabricating a semiconductor device using self aligned contact Download PDF

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KR100652361B1
KR100652361B1 KR1020000053413A KR20000053413A KR100652361B1 KR 100652361 B1 KR100652361 B1 KR 100652361B1 KR 1020000053413 A KR1020000053413 A KR 1020000053413A KR 20000053413 A KR20000053413 A KR 20000053413A KR 100652361 B1 KR100652361 B1 KR 100652361B1
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gate
semiconductor substrate
film
layer
forming
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KR20020020313A (en
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지경구
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3

Abstract

자기정렬방식에 의한 콘택 형성시, 산화막과 질화막이 갖는 식각선택비의 영향을 크게 받지 않는 반도체 소자의 제조방법에 관해 개시한다. 이를 위하여 본 발명은 게이트 절연막이 형성된 반도체 기판 위에 게이트 전극층, 실리사이드층, 상부절연막 및 게이트 스페이서로 이루어진 게이트 패턴을 형성하는 공정과, 상기 게이트 패턴이 형성된 반도체 기판 전면을 덮는 층간절연막을 증착하는 공정과, 상기 반도체 기판에서 콘택이 형성될 영역의 층간절연막을 게이트 패턴 높이 이하로 부분 식각하는 공정과, 상기 부분식각된 층간절연막의 측벽에 스페이서를 형성하는 공정과, 상기 부분식각된 층간절연막을 2차 식각하여 게이트 패턴 사이의 반도체 기판 표면을 노출시키는 공정과, 상기 반도체 기판 전면에 콘택 형성용 도전층을 형성하는 공정 및 상기 게이트 패턴 상부절연막을 연마저지층으로 상기 콘택 형성용 도전층을 평탄화시키는 공정을 구비하는 것을 특징으로 하는 자기정렬 방식에 의한 반도체 소자의 제조방법을 제공한다. A method of manufacturing a semiconductor device in which contact formation by a self-aligning method is not greatly influenced by an etching selectivity of an oxide film and a nitride film. To this end, the present invention is a process for forming a gate pattern consisting of a gate electrode layer, a silicide layer, an upper insulating film and a gate spacer on a semiconductor substrate having a gate insulating film, and depositing an interlayer insulating film covering the entire surface of the semiconductor substrate on which the gate pattern is formed; And partially etching the interlayer insulating layer in the region where the contact is to be formed in the semiconductor substrate to a gate pattern height, forming a spacer on sidewalls of the partially etched interlayer insulating layer, and performing secondary etching of the partially etched interlayer insulating layer. Etching to expose the surface of the semiconductor substrate between the gate patterns; forming a contact forming conductive layer on the entire surface of the semiconductor substrate; and planarizing the contact forming conductive layer using the gate pattern upper insulating layer as an abrasive blocking layer. Self-aligning room comprising a It provides a method for manufacturing a semiconductor device according to.

Description

자기정렬 방식에 의한 반도체 소자의 제조방법{Method for fabricating a semiconductor device using self aligned contact}Method for fabricating a semiconductor device using self aligned contact}

도 1 내지 도 4는 본 발명의 실시예에 의한 자기정렬 방식의 반도체 소자의 제조방법을 설명하기 위해 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a self-aligning semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100: 반도체 기판, 102: 게이트 절연막,100: semiconductor substrate, 102: gate insulating film,

104: 게이트 패턴, 106: 콘택이 형성될 영역,104: gate pattern, 106: region where a contact is to be formed,

108: 층간절연막, 110: 게이트 전극층,108: interlayer insulating film, 110: gate electrode layer,

112: 실리사이드층, 114: 상부 절연막,112: silicide layer, 114: upper insulating film,

116: 게이트 스페이서, 118: 스페이서,116: gate spacer, 118: spacer,

120: 콘택 형성용 도전층.120: conductive layer for forming a contact.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 자기 정렬 방식의 콘택(SAC: Self Aligned Contact)을 이용한 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a self aligned contact (SAC).                         

반도체 소자의 미세화가 진행됨에 따라, 이를 가공하는 공정의 공정 난이도 역시 증대하고 있다. 특히 미세패턴의 사진공정에서 오버레이 마진(overlay margin)이 협소해짐에 따라 미세한 크기의 콘택 형성 공정 자체가 힘들어지고 있다. 이에 대한 대안으로 미세패턴을 사용하는 반도체 소자의 제조공정에서는 자기정렬방식의 콘택(SAC) 형성 기술이 도입되고 있다. As the miniaturization of semiconductor devices proceeds, the difficulty of processing the same increases. In particular, as the overlay margin narrows in the photo process of the micro pattern, the contact formation process of the micro size becomes difficult. As an alternative, a self-aligning contact (SAC) forming technology is introduced in a semiconductor device manufacturing process using a fine pattern.

자기정렬방식의 콘택(SAC) 형성 기술은 두 개의 절연막 사이의 식각선택비를 이용하는 콘택형성 기술로서 현재 일반적으로 사용하는 막질로는 산화막을 식각할 때, 질화막을 스페이서와 마스크로 사용하는 방식이다.Self-aligned contact (SAC) formation technology is a contact formation technique using an etch selectivity between two insulating films. In general, a film quality that uses a nitride film as a spacer and a mask when etching an oxide film.

그러나, 반도체 소자의 고접적화에 따라, 콘택홀을 형성할 때 종횡비(Aspect ratio)가 증가하고, 이에 따라 가공에 필요한 산화막과 질화막 사이의 식각선택비 증가도 함께 요구되고 있는 실정이다. 일반적인 반도체 소자의 제조공정에서 통상적으로 얻을 수 있는 산화막/질화막의 식각선택비는 5:1 이하이나, 실제로 안정된 반도체 소자의 가공에 필요한 식각선택비는 20:1을 상회하고 있는 실정이다. However, according to the high integration of semiconductor devices, aspect ratios are increased when forming contact holes, and accordingly, an etching selectivity between an oxide film and a nitride film required for processing is also required. The etching selectivity of the oxide / nitride film that can be generally obtained in a general semiconductor device manufacturing process is 5: 1 or less, but the etching selectivity required for processing a stable semiconductor device actually exceeds 20: 1.

이러한 필요에 부응하기 위해 산화막과 질화막 사이의 식각선택비를 높이기 위한 다각적인 연구가 지속으로 행하여져 오고 있다. 상기 다각적인 연구의 대표적인 예로서는, 식각시 챔버 벽(wall)의 가열에 의한 플라즈마 내의 CFx의 레디컬(radical) 농도를 증가시키려는 노력과, 높은 C/F 비(radio)를 갖는 신규 가스로서 C4F8, C5F8, C3F6 등을 사용한 식각공정의 개발, 그리고 로우 일렉트론 온도(low electron temperature)를 갖는 플라즈마 원을 개발하여 플라즈마 내부에서 지나친 해리에 의한 과도한 불소기(F radical)가 발생하는 것을 억제하는 연구 등을 들 수 있다.In order to meet this need, various studies have been continuously conducted to increase the etching selectivity between the oxide film and the nitride film. Representative examples of such multifaceted studies include efforts to increase the radical concentration of CFx in the plasma by heating the chamber walls during etching, and C 4 as a novel gas having a high C / F radio. Development of an etching process using F 8 , C 5 F 8 , C 3 F 6, etc., and the development of a plasma source with low electron temperature, resulting in excessive dissociation in the plasma. Research to suppress the occurrence of

그러나 현시점에서 이러한 산화막과 질화막 사이의 식각선택비를 높이기 위한 연구의 결과에 의해 도출된 산화막과 질화막 사이의 식각선택비가 아직까지 10:1을 넘지 못하는 실정이다.However, at present, the etching selectivity between the oxide film and the nitride film derived by the results of the research for increasing the etching selectivity between the oxide film and the nitride film has not exceeded 10: 1.

본 발명이 이루고자 하는 기술적 과제는 자기정렬방식으로 콘택 형성시에 산화막과 질화막이 갖는 식각선택비의 영향을 크게 받지 않는 자기정렬 방식의 반도체 소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a self-aligning semiconductor device that is not significantly affected by the etching selectivity of the oxide film and the nitride film at the time of forming a contact by the self-aligning method.

상기 기술적 과제를 달성하기 위하여 본 발명은, 게이트 절연막이 형성된 반도체 기판 위에 게이트 전극층, 실리사이드층, 상부절연막 및 게이트 스페이서로 이루어진 게이트 패턴을 형성하는 공정과, 상기 게이트 패턴이 형성된 반도체 기판 전면을 덮는 층간절연막을 증착하는 공정과, 상기 반도체 기판에서 콘택이 형성될 영역의 층간절연막을 게이트 패턴 높이 이하로 부분 식각하는 공정과, 상기 부분식각된 층간절연막의 측벽에 스페이서를 형성하는 공정과, 상기 부분식각된 층간절연막을 2차 식각하여 게이트 패턴 사이의 반도체 기판 표면을 노출시키는 공정과, 상기 반도체 기판 전면에 콘택 형성용 도전층을 형성하는 공정 및 상기 게이트 패턴 상부절연막을 연마저지층으로 상기 콘택 형성용 도전층을 평탄화시키는 공정을 구비하는 것을 특징으로 하는 자기정렬 방식에 의한 반도체 소자의 제조방법을 제공한다. According to an aspect of the present invention, there is provided a method of forming a gate pattern including a gate electrode layer, a silicide layer, an upper insulating layer, and a gate spacer on a semiconductor substrate on which a gate insulating layer is formed, and an interlayer covering an entire surface of the semiconductor substrate on which the gate pattern is formed. Depositing an insulating film, partially etching an interlayer insulating film in a region where a contact is to be formed in the semiconductor substrate to a gate pattern height or less, forming a spacer on a sidewall of the partially etched interlayer insulating film, and performing the partial etching Etching the interlayer insulating film to expose the surface of the semiconductor substrate between the gate patterns, forming a contact forming conductive layer on the entire surface of the semiconductor substrate, and forming the contact using the gate pattern upper insulating film as an abrasive blocking layer. Characterized in that it comprises a step of planarizing the conductive layer. Provided is a method of manufacturing a semiconductor device by a self-aligning method.                     

본 발명의 바람직한 실시예에 의하면, 상기 스페이서는 상기 층간절연막에 대해 식각선택비를 갖는 물질을 사용하여 형성하는 것이 적합하며, 이러한 물질은 질화막, 탄화실리콘막(SiC), 산화알루미늄막(Al2O3), 금속막 및 실리사이드막으로 이루어진 물질군중에서 선택된 어느 하나인 것이 적합하다.According to a preferred embodiment of the present invention, the spacer is suitably formed using a material having an etch selectivity with respect to the interlayer insulating film, and the material may be formed of a nitride film, a silicon carbide film (SiC), or an aluminum oxide film (Al 2). O 3 ), a metal film and a silicide film are any one selected from the group of materials.

본 발명에 따르면, 자기정렬방식에 의한 콘택 형성시에 산화막과 질화막이 갖는 식각선택비의 영향을 크게 받지 않는 새로운 자기정렬 방식의 반도체 소자의 제조방법을 구현할 수 있다.According to the present invention, a method of manufacturing a new self-aligning semiconductor device can be realized which is not significantly affected by the etching selectivity of the oxide film and the nitride film at the time of forming the contact by the self-aligning method.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 4는 본 발명의 실시예에 의한 자기정렬 방식의 반도체 소자의 제조방법을 설명하기 위해 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a self-aligning semiconductor device according to an embodiment of the present invention.

도 1을 참조하면, 반도체 기판(100)에 게이트 절연막(102)을 형성하고, 그 상부에 게이트 전극층(110), 실리사이드층(112) 및 상부절연막(114)을 순차적으로 적층한다. 상기 게이트 전극층(110)은 폴리실리콘을, 실리사이드층(112)은 텅스텐 실리사이드(WSix)를, 상부절연막(114)은 질화막을 이용하여 각각 형성할 수 있다. Referring to FIG. 1, a gate insulating layer 102 is formed on a semiconductor substrate 100, and a gate electrode layer 110, a silicide layer 112, and an upper insulating layer 114 are sequentially stacked on the gate insulating layer 102. The gate electrode layer 110 may be formed of polysilicon, the silicide layer 112 may be formed of tungsten silicide (WSix), and the upper insulating layer 114 may be formed of a nitride layer.

계속해서 상기 게이트 전극층(110), 실리사이드층(112) 및 상부절연막(114)을 식각하여 게이트 전극 패턴을 형성한다. 상기 게이트 전극 패턴이 형성된 반도체 기판 전면에 게이트 스페이서 형성을 위한 절연막, 예컨대 질화막을 증착하고 이를 이방성으로 식각하여 게이트 스페이서(116)를 형성함으로써 게이트 전극층(110), 실리사이드층(112), 상부절연막(114) 및 게이트 스페이서(116)로 이 루어진 게이트 패턴(104)을 형성한다.Subsequently, the gate electrode layer 110, the silicide layer 112, and the upper insulating layer 114 are etched to form a gate electrode pattern. The gate electrode layer 110, the silicide layer 112, and the upper insulating layer may be formed by depositing an insulating layer, for example, a nitride layer, to form a gate spacer on the semiconductor substrate on which the gate electrode pattern is formed, and then etching the anisotropic layer to form the gate spacer 116. A gate pattern 104 formed of 114 and a gate spacer 116 is formed.

상기 게이트 패턴(104)이 형성된 반도체 기판 위에 층간절연막(108), 예컨대 산화막 또는 산화막을 포함하는 복합막을 형성한다. 그 후, 콘택이 형성될 영역(106)을 부분적으로 식각하되, 식각된 깊이가 상기 게이트 패턴(104)이 높이보다 낮도록 부분 식각을 진행한다. 이어서, 상기 부분 식각을 위해 사용된 포토레지스트 패턴을 에싱(Ashing) 및 황산 스트립(strip) 공정으로 제거한다.An interlayer insulating film 108, for example, an oxide film or a composite film including an oxide film, is formed on the semiconductor substrate on which the gate pattern 104 is formed. Thereafter, the region 106 in which the contact is to be formed is partially etched, and the partial etching is performed so that the etched depth is lower than the height of the gate pattern 104. The photoresist pattern used for the partial etching is then removed by ashing and sulfuric acid strip processes.

도 2를 참조하면, 상기 부분 식각이 진행된 반도체 기판 위에 스페이서 형성을 위한 물질막을 반도체 기판의 표면 단차를 따라 일정한 두께로 형성한다. 상기 스페이서 형성을 위한 물질막은 상기 층간절연막(108)과 식각선택비를 갖는 물질막으로서, 질화막, 탄화실리콘막(SiC), 산화알루미늄막(Al2O3), 폴리실리콘막, 금속막 및 실리사이드막중에서 하나를 이용하여 형성하는 것이 바람직하다. 계속해서 상기 스페이서 형성을 위한 물질막, 예컨대 폴리실리콘막에 이방성 식각을 진행하여 상기 부분 식각된 층간절연막(108)의 측벽에 폴리실리콘으로 된 스페이서(118)를 형성한다. Referring to FIG. 2, a material layer for forming a spacer is formed on the semiconductor substrate subjected to the partial etching to a predetermined thickness along a surface step of the semiconductor substrate. The material film for forming the spacer is a material film having an etch selectivity with respect to the interlayer insulating film 108, and includes a nitride film, a silicon carbide film (SiC), an aluminum oxide film (Al 2 O 3 ), a polysilicon film, a metal film, and a silicide. It is preferable to form using one of the films. Subsequently, anisotropic etching is performed on the material layer for forming the spacer, such as a polysilicon layer, to form a spacer 118 made of polysilicon on the sidewall of the partially etched interlayer insulating layer 108.

도 3을 참조하면, 상기 스페이서(118)가 형성된 반도체 기판에 2차 식각을 진행하여 상기 게이트 패턴(104) 사이의 콘택이 형성될 부분, 즉 반도체 기판(100) 표면을 노출시킨다. 상기 스페이서(118)가 형성된 반도체 기판 전면에 콘택 형성용 도전층(120), 예컨대 폴리실리콘층을 상기 콘택이 형성될 부분(106)을 채우면서 상기 스페이서(118)를 덮도록 충분한 두께로 증착한다.Referring to FIG. 3, secondary etching is performed on a semiconductor substrate on which the spacers 118 are formed to expose a portion where a contact between the gate patterns 104 is to be formed, that is, a surface of the semiconductor substrate 100. A contact forming conductive layer 120, for example, a polysilicon layer, is deposited on the entire surface of the semiconductor substrate on which the spacer 118 is formed to a sufficient thickness to cover the spacer 118 while filling the portion 106 where the contact is to be formed. .

도 4를 참조하면, 상기 증착된 콘택 형성용 도전층(120)에 화학기계적 연마(CMP: Chemical Mechanical Polishing) 공정을 진행하여 완성된 구조의 자기정렬 방식에 의한 콘택을 갖는 반도체 소자를 형성한다. 이때, 게이트 패턴(104)의 상기 상부절연막(114)은 화학기계적 연마(CMP) 공정에서 연마저지층(polishing stopper)의 역할을 수행한다. Referring to FIG. 4, a chemical mechanical polishing (CMP) process is performed on the deposited contact forming layer 120 to form a semiconductor device having a contact by a self-aligning method of a completed structure. In this case, the upper insulating layer 114 of the gate pattern 104 serves as a polishing stopper in a chemical mechanical polishing (CMP) process.

본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

따라서, 상술한 본 발명에 따르면, 자기정렬방식에 의한 콘택 형성시에 산화막과 질화막이 갖는 식각선택비의 영향을 크게 받지 않는 새로운 자기정렬 방식의 반도체 소자의 제조방법을 구현할 수 있다. Therefore, according to the present invention described above, it is possible to implement a new method of manufacturing a semiconductor device of a new self-aligning method that is not significantly affected by the etching selectivity of the oxide film and the nitride film when forming a contact by the self-aligning method.

Claims (3)

게이트 절연막이 형성된 반도체 기판 위에 게이트 전극층, 실리사이드층, 상부절연막 및 게이트 스페이서로 이루어진 게이트 패턴을 형성하는 공정;Forming a gate pattern including a gate electrode layer, a silicide layer, an upper insulating film, and a gate spacer on the semiconductor substrate on which the gate insulating film is formed; 상기 게이트 패턴이 형성된 반도체 기판 전면을 덮는 층간절연막을 증착하는 공정;Depositing an interlayer insulating film covering an entire surface of the semiconductor substrate on which the gate pattern is formed; 상기 반도체 기판에서 콘택이 형성될 영역의 층간절연막을 게이트 패턴 높이 이하로 부분 식각하는 공정;Partially etching an interlayer insulating film in a region where a contact is to be formed in the semiconductor substrate to a gate pattern height or less; 상기 부분식각된 층간절연막의 측벽에 스페이서를 형성하는 공정;Forming a spacer on sidewalls of the partially etched interlayer insulating film; 상기 부분식각된 층간절연막을 2차 식각하여 게이트 패턴 사이의 반도체 기 판 표면을 노출시키는 공정;Second etching the partially etched interlayer insulating film to expose a surface of the semiconductor substrate between the gate patterns; 상기 반도체 기판 전면에 콘택 형성용 도전층을 형성하는 공정; 및Forming a conductive layer for forming a contact on the entire surface of the semiconductor substrate; And 상기 게이트 패턴 상부절연막을 연마저지층으로 상기 콘택 형성용 도전층을 평탄화시키는 공정을 구비하는 것을 특징으로 하는 자기정렬 방식에 의한 반도체 소자의 제조방법.And planarizing the conductive layer for forming a contact with the gate pattern upper insulating film using an abrasive blocking layer. 제1항에 있어서, The method of claim 1, 상기 스페이서는 상기 층간절연막에 대해 식각선택비를 갖는 물질을 사용하여 형성하는 것을 특징으로 하는 자기정렬 방식에 의한 반도체 소자의 제조방법.And the spacers are formed using a material having an etch selectivity with respect to the interlayer insulating layer. 제2항에 있어서, The method of claim 2, 상기 층간절연막에 대해 식각선택비를 갖는 물질은 질화막, 탄화실리콘막(SiC), 산화알루미늄막(Al2O3), 폴리실리콘막, 금속막 및 실리사이드막으로 이루어진 물질군중에서 선택된 어느 하나인 것을 특징으로 하는 자기정렬 방식에 의한 반도체 소자의 제조방법.The material having an etch selectivity with respect to the interlayer insulating film is any one selected from the group consisting of a nitride film, a silicon carbide film (SiC), an aluminum oxide film (Al 2 O 3 ), a polysilicon film, a metal film, and a silicide film. A method of manufacturing a semiconductor device by a self-aligning method, characterized in that.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07147322A (en) * 1993-11-25 1995-06-06 Nec Corp Manufacture of semiconductor device
JPH09232427A (en) * 1996-02-23 1997-09-05 Nec Corp Manufacturing method for semiconductor device
KR19990042192A (en) * 1997-11-26 1999-06-15 구본준 Manufacturing Method of Semiconductor Device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07147322A (en) * 1993-11-25 1995-06-06 Nec Corp Manufacture of semiconductor device
JPH09232427A (en) * 1996-02-23 1997-09-05 Nec Corp Manufacturing method for semiconductor device
KR19990042192A (en) * 1997-11-26 1999-06-15 구본준 Manufacturing Method of Semiconductor Device

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