KR19990042192A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990042192A KR19990042192A KR1019970062922A KR19970062922A KR19990042192A KR 19990042192 A KR19990042192 A KR 19990042192A KR 1019970062922 A KR1019970062922 A KR 1019970062922A KR 19970062922 A KR19970062922 A KR 19970062922A KR 19990042192 A KR19990042192 A KR 19990042192A
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- insulating film
- contact hole
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 abstract description 15
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000005368 silicate glass Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명에 따른 반도체소자의 제조 방법은 반도체기판 상에 불순물영역 및 게이트를 포함하는 트랜지스터를 형성하는 공정과, 상기 반도체기판 상에 상기 트랜지스터를 덮는 제 1 절연막 및 평탄한 제 2 절연막을 형성하고 상기 제 2 절연막 상에 상기 제 1 및 제 2 절연막과 식각선택비가 다른 제 3 절연막을 형성하는 공정과, 상기 제 3 절연막 상에 포토레지스트를 도포하고 노광 및 현상하여 상기 불순물영역과 대응하는 부분의 포토레지스트를 제거하는 패턴을 형성하는 공정과, 상기 잔존하는 포토레지스트를 마스크로 사용하여 상기 제 3 및 제 2 절연막을 이방성 건식식각하여 제 1 절연막의 소정 부분이 노출되는 제 1 접촉홀을 형성하는 공정과, 상기 제 3 절연막 상에 상기 제 1 접촉홀의 표면을 덮고 상기 제 1 및 제 2 절연막과는 식각선택비가 다른 물질을 증착하고 에치백하여 상기 제 1 접촉홀을 측면에 측벽을 형성하는 공정과, 상기 제 3 절연막을 마스크로 상기 잔류하는 제 2 및 제 1 절연막을 습식식각하여 상기 불순물영역의 소정 부분을 노출시키는 제 2 접촉홀을 형성하는 공정을 구비한다. 따라서, 본 발명에 따라 제조된 반도체소자는 불순물영역의 소정 부분을 노출시키는 접촉홀을 형성하기 위해 건식식각과 습식식각을 같이 사용하여 접촉홀의 폭이 넓어지는 것을 방지하는 한편 건식식각에 의한 반도체기판의 로스와 산화물과 질화물의 고식각선택비에 의해 플러그와 게이트가 연결되는 브리지를 방지하여 반도체소자 특성의 열화를 방지하는 잇점이 있다.A method of manufacturing a semiconductor device according to the present invention includes forming a transistor including an impurity region and a gate on a semiconductor substrate, forming a first insulating film and a flat second insulating film covering the transistor on the semiconductor substrate, and forming the transistor. Forming a third insulating film having an etch selectivity different from that of the first and second insulating films on the insulating film; and applying and exposing and developing a photoresist on the third insulating film to form a photoresist of a portion corresponding to the impurity region. Forming a first contact hole through which a predetermined portion of the first insulating film is exposed by anisotropically dry etching the third and second insulating films using the remaining photoresist as a mask; And covering the surface of the first contact hole on the third insulating film and having an etch selectivity different from that of the first and second insulating films. Depositing and etching back to form sidewalls of the first contact hole, and wet etching the remaining second and first insulating layers using the third insulating layer as a mask to expose a predetermined portion of the impurity region. And forming a second contact hole. Therefore, the semiconductor device manufactured according to the present invention prevents the width of the contact hole from being widened by using both dry etching and wet etching to form contact holes for exposing a predetermined portion of the impurity region. Due to the high etch selectivity of the oxide and the nitride and the high etch selectivity, the bridge between the plug and the gate is prevented, thereby deteriorating the characteristics of the semiconductor device.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로서, 특히, 콘택을 형성하는 건식식각으로 인한 반도체소자의 열화를 방지하는 반도체소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing deterioration of the semiconductor device due to dry etching for forming a contact.
반도체소자가 고집적화됨에 따라 단위소자의 크기가 감소되었다. 따라서, 금속배선의 선폭이 감소되고, 선간거리 또한 감소되어 갔다. 이에 따라, 접촉홀의 직경이 작고 깊이 방향이 큰, 즉, 종횡비(aspect ratio)가 커지게 되었다.As semiconductor devices have been highly integrated, the size of unit devices has been reduced. Therefore, the line width of the metal wiring is reduced, and the line distance is also reduced. Accordingly, the diameter of the contact hole is small and the depth direction is large, that is, the aspect ratio becomes large.
따라서, 종횡비가 큰 반도체소자를 정밀하게 미세가공할 수 있는 건식식각(Dry Etching) 방법을 사용하여 반도체소자의 접촉홀을 형성하게 되었다.Therefore, the contact holes of the semiconductor devices are formed by using a dry etching method capable of precisely processing a semiconductor device having a high aspect ratio.
도 1a 내지 도 1c는 종래 기술에 따른 반도체소자의 제조 방법을 도시하는 공정도이다.1A to 1C are process diagrams illustrating a method of manufacturing a semiconductor device according to the prior art.
종래에는 도 1a에 나타낸 바와 같이 반도체기판(11) 상에 LOCOS(Local Oxidation of Silicon) 등과 같은 통상적인 소자 격리 방법으로 필드산화막(12)을 형성하여 활성영역을 한정하고, 상기 필드산화막(12)이 형성된 반도체기판(11) 상에 열산화의 방법으로 게이트산화막(13)을 형성하고, 상기 게이트산화막(13) 상에 불순물이 도핑된 다결정실리콘(Polysilicon)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한 후 상기 다결정실리콘층 상에 질화물을 이용하여 캡절연막(15)을 형성한다. 그리고 상기 캡절연막(15), 다결정실리콘층, 게이트 절연막(13)이 상기 필드산화막(12)으로 한정된 활성영역 상에 잔류하도록 포토리쏘그래피(Photolithograpy) 방법으로 패터닝하여 게이트(14)를 형성한다. 상기 반도체기판(11) 상에 상기 게이트(14)를 덮는 절연물질을 증착하고 에치백하여 상기 게이트(14)의 측면에 측벽(16)을 형성하고, 상기 캡절연막(15) 및 측벽(16)을 마스크로 사용하여 상기 반도체기판(11)에 반도체기판(11)과 도전형이 다른 불순물을 이온주입하여 소오스/드레인영역으로 사용되는 불순물영역(17)을 형성한다.In the related art, as shown in FIG. 1A, a field oxide film 12 is formed on a semiconductor substrate 11 by a conventional device isolation method such as LOCOS (Local Oxidation of Silicon) to define an active region, and the field oxide film 12 is formed. The gate oxide film 13 is formed on the formed semiconductor substrate 11 by thermal oxidation, and a polycrystalline silicon (Polysilicon) doped with impurities is formed on the gate oxide film 13. After the deposition by a CVD method to form a cap insulating film 15 by using a nitride on the polysilicon layer. The cap 14, the polysilicon layer, and the gate insulating layer 13 are patterned by photolithography so as to remain on the active region defined by the field oxide layer 12 to form the gate 14. The insulating material covering the gate 14 is deposited and etched back on the semiconductor substrate 11 to form sidewalls 16 on the side surfaces of the gates 14, and the cap insulating layer 15 and the sidewalls 16. The impurity region 17 used as a source / drain region is formed by ion implanting impurities having a conductivity different from that of the semiconductor substrate 11 into the semiconductor substrate 11 using the mask as a mask.
그런 후에, 도 1b에 나타낸 바와 같이, 상기 반도체기판(11) 상에 상기 게이트(14)를 보호하는 제 1 절연막(18)을 형성하고 상기 제 1 절연막(18) 상에 실리케이트 유리(Silicate Glass)에 불순물을 첨가하여 점성을 낮춘 붕소 인 실리케이트 유리(Boronphospho Silicate Glass) 등을 증착하여 평탄한 제 2 절연막(19)을 형성한다. 그리고 상기 평탄한 제 2 절연막(19) 상에 포토레지스트(20)를 도포하고 노광 및 현상하여 상기 게이트(14) 사이의 불순물영역(17)과 대응하는 부분의 포토레지스트(20)가 제거된 패턴을 형성한다.Thereafter, as shown in FIG. 1B, a first insulating film 18 is formed on the semiconductor substrate 11 to protect the gate 14, and silicate glass is formed on the first insulating film 18. An impurity is added to the boron phosphorus silicate glass having a lower viscosity to deposit a second insulating film 19. Then, the photoresist 20 is coated on the flat second insulating layer 19, and the photoresist 20 is exposed and developed to remove the photoresist 20 of the portion corresponding to the impurity region 17 between the gates 14. Form.
그리고, 도 1c와 같이 상기 잔존하는 포토레지스트(20)를 마스크로 사용하여 상기 제 2 및 제 1 절연막(19)(18)을 순차적으로 이방성 건식 식각하여 상기 소정의 불순물영역(17)을 노출시키는 접촉홀을 형성한다.As shown in FIG. 1C, the second and first insulating layers 19 and 18 are sequentially anisotropically dry-etched using the remaining photoresist 20 as a mask to expose the predetermined impurity region 17. Form a contact hole.
상술한 바와 같이 종래에는 반도체기판 상에 불순물영역 및 게이트를 포함하는 트랜지스터를 형성하고 상기 반도체기판 상에 평탄한 절연막을 형성하고 상기 절연막을 건식식각하여 상기 반도체기판의 불순물영역을 노출시키는 접촉홀을 형성하였다.As described above, in the related art, a transistor including an impurity region and a gate is formed on a semiconductor substrate, a flat insulating layer is formed on the semiconductor substrate, and the contact hole is formed by dry etching the insulating layer to expose the impurity region of the semiconductor substrate. It was.
그러나 상기 반도체기판의 불순물영역을 노출시키기 위해 사용한 건식식각으로 인해 상기 반도체기판까지 영향을 받아 반도체기판의 로스(loss) 및 플라즈마 데미지(damage)로 인해 반도체소자의 저항이 증가하고 반도체기판의 결함(defect)을 유발하여 반도체소자의 특성을 열화 시킨다. 또한 게이트의 캡절연막 및 질화물 측벽의 증착량이 적을 경우 건식식각으로 인해 상기 산화막의 식각시 질화막이 함께 식각되어 이후에 상기 접촉홀에 도전물질을 채워 플러그를 형성할 때, 상기 플러그가 상기 게이트와 서로 연결되는 브리지(Bridge)가 발생하는 문제가 있었다.However, due to the dry etching used to expose the impurity region of the semiconductor substrate, the semiconductor substrate is affected by the loss and plasma damage of the semiconductor substrate, resulting in an increase in resistance of the semiconductor device and defects in the semiconductor substrate. defects) and deteriorate the characteristics of the semiconductor device. Also, when the deposition amount of the cap insulation layer and the nitride sidewall of the gate is small, the nitride layer is etched together during the etching of the oxide layer due to dry etching, and when the plug is filled with a conductive material in the contact hole to form a plug, the plug and the gate There was a problem that a bridge to be connected occurs.
따라서, 본 발명의 목적은 플러그를 위해 접촉홀을 형성할 때, 반도체기판의 로스나 결함을 방지하여 반도체소자 특성의 열화를 방지하는 반도체소자의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device which prevents loss of semiconductor substrates or deterioration of semiconductor device characteristics when forming a contact hole for a plug.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조 방법은 반도체기판 상에 불순물영역 및 게이트를 포함하는 트랜지스터를 형성하는 공정과, 상기 반도체기판 상에 상기 트랜지스터를 덮는 제 1 절연막 및 평탄한 제 2 절연막을 형성하고 상기 제 2 절연막 상에 상기 제 1 및 제 2 절연막과 식각선택비가 다른 제 3 절연막을 형성하는 공정과, 상기 제 3 절연막 상에 포토레지스트를 도포하고 노광 및 현상하여 상기 불순물영역과 대응하는 부분의 포토레지스트를 제거하는 패턴을 형성하는 공정과, 상기 잔존하는 포토레지스트를 마스크로 사용하여 상기 제 3 및 제 2 절연막을 이방성 건식식각하여 제 1 절연막의 소정 부분이 노출되는 제 1 접촉홀을 형성하는 공정과, 상기 제 3 절연막 상에 상기 제 1 접촉홀의 표면을 덮고 상기 제 1 및 제 2 절연막과는 식각선택비가 다른 물질을 증착하고 에치백하여 상기 제 1 접촉홀을 측면에 측벽을 형성하는 공정과, 상기 제 3 절연막을 마스크로 상기 잔류하는 제 2 및 제 1 절연막을 습식식각하여 상기 불순물영역의 소정 부분을 노출시키는 제 2 접촉홀을 형성하는 공정을 구비한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a transistor comprising an impurity region and a gate on a semiconductor substrate, a first insulating film and a second flat planar covering the transistor on the semiconductor substrate Forming an insulating film and forming a third insulating film having an etch selectivity different from that of the first and second insulating films on the second insulating film, and applying and exposing and developing a photoresist on the third insulating film to form the impurity region; Forming a pattern for removing a photoresist of a corresponding portion; and first contacting the third and second insulating films by anisotropic dry etching using the remaining photoresist as a mask to expose a predetermined portion of the first insulating film. Forming a hole, covering the surface of the first contact hole on the third insulating film, and the first and second insulation Depositing and etching back a material having an etch selectivity different from that of the film to form sidewalls on the side of the first contact hole, and wet etching the remaining second and first insulating films using the third insulating film as a mask. And forming a second contact hole for exposing a predetermined portion of the impurity region.
도 1a 내지 도 1c는 종래 기술에 따른 반도체소자의 제조 방법을 도시하는 공정도.1A to 1C are process drawings showing a method for manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체소자의 제조 방법을 도시하는 공정도.2A to 2D are flowcharts illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 간단한 설명><Brief description of symbols for the main parts of the drawings>
21 : 반도체기판 24 : 게이트21: semiconductor substrate 24: gate
27 : 불순물영역 28 : 제 1 절연막27 impurity region 28 first insulating film
29 : 제 2 절연막 31 : 제 3 절연막29: second insulating film 31: third insulating film
33 : 질화물 측벽 35 : 접촉홀33: nitride sidewall 35: contact hole
이하, 첨부된 도면을 참조로 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체소자의 제조 방법을 도시하는 공정도이다.2A to 2D are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
본 방법은 도 2a에 나타낸 바와 같이 반도체기판(21) 상에 LOCOS 등과 같은 통상적인 소자 격리 방법으로 필드산화막(22)을 형성하여 활성영역을 한정하고, 상기 필드산화막(22)이 형성된 반도체기판(21) 상에 열산화의 방법으로 게이트산화막(23)을 형성하고, 상기 게이트산화막(23) 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착한 후 상기 다결정실리콘층 상에 질화물을 이용하여 캡절연막(25)을 형성한다. 그리고 상기 캡절연막(25), 다결정실리콘층, 게이트 절연막(23)이 상기 필드산화막(22)으로 한정된 활성영역 상에 잔류하도록 포토리쏘그래피 방법으로 패터닝하여 게이트(24)를 형성한다. 상기 반도체기판(21) 상에 상기 게이트(24)를 덮는 절연물질을 증착하고 에치백하여 상기 게이트(24)의 측면에 측벽(26)을 형성하고, 상기 캡절연막(25) 및 측벽(26)을 마스크로 사용하여 상기 반도체기판(21)에 반도체기판(21)과 도전형이 다른 불순물을 이온주입하여 소오스/드레인영역으로 사용되는 불순물영역(27)을 형성한다.As shown in FIG. 2A, the field oxide film 22 is formed on the semiconductor substrate 21 by a conventional device isolation method such as LOCOS to define an active region, and the semiconductor substrate having the field oxide film 22 formed thereon ( 21) a gate oxide film 23 is formed on the gate oxide film 23 by a thermal oxidation method, and polycrystalline silicon doped with impurities on the gate oxide film 23 is deposited by a CVD method, and then a cap is formed on the polysilicon layer using nitride. The insulating film 25 is formed. The cap 24, the polysilicon layer, and the gate insulating layer 23 are patterned by photolithography so as to remain on the active region defined by the field oxide layer 22 to form the gate 24. The insulating material covering the gate 24 is deposited on the semiconductor substrate 21 and etched back to form sidewalls 26 on the side of the gate 24, and the cap insulating layer 25 and the sidewalls 26 are formed. The impurity region 27 used as a source / drain region is formed by ion implanting impurities having a conductivity different from that of the semiconductor substrate 21 into the semiconductor substrate 21 using the mask as a mask.
그런 후에, 도 2b에 나타낸 바와 같이, 상기 반도체기판(21) 상에 상기 게이트(24)를 보호하는 제 1 절연막(28)을 형성하고 상기 제 1 절연막(28) 상에 실리케이트 유리에 불순물을 첨가하여 점성을 낮춘 붕소 인 실리케이트 유리 등을 증착하여 평탄한 제 2 절연막(29)을 형성한다. 그리고 상기 평탄한 제 2 절연막(29) 상에 질화물질과 같이 상기 산화막으로 형성된 제 1 및 제 2 절연막과 식각선택비가 다른 제 3 절연막(31)을 형성하고, 상기 제 3 절연막(31) 상에 포토레지스트(32)를 도포하고 노광 및 현상하여 상기 게이트(24) 사이의 불순물영역(27)과 대응하는 부분의 포토레지스트(32)가 제거된 패턴을 형성한다.Thereafter, as shown in FIG. 2B, a first insulating film 28 is formed on the semiconductor substrate 21 to protect the gate 24, and impurities are added to the silicate glass on the first insulating film 28. By depositing boron phosphorus silicate glass having a lower viscosity to form a flat second insulating film 29. A third insulating film 31 having an etch selectivity different from that of the first and second insulating films formed of the oxide film, such as a nitride material, is formed on the flat second insulating film 29, and a photo is formed on the third insulating film 31. The resist 32 is applied, exposed and developed to form a pattern in which the photoresist 32 in the portion corresponding to the impurity region 27 between the gate 24 is removed.
그리고, 도 2c와 같이 상기 잔존하는 포토레지스트(32)를 마스크로 사용하여 상기 제 3 및 제 2 절연막(31)(29)을 부분적으로 이방성 건식 식각하여 단차에 의해 게이트(24)의 상부에 형성된 상기 제 1 절연막(28)의 소정 부분이 노출도록 패터닝한다. 상기 패터닝에 의해 상기 제 3 및 제 2 절연막(31)(29)에 생성된 홀의 표면을 덮도록 상기 제 3 절연막(31) 상에 질화물과 같이 상기 제 1 및 제 2 절연막(28)(29)과 식각선택비가 다른 물질을 증착하고 에치백하여 상기 홀의 측면에 질화물 측벽(33)을 형성한다.As shown in FIG. 2C, the third and second insulating layers 31 and 29 are partially anisotropically dry-etched using the remaining photoresist 32 as a mask, and are formed on the gate 24 by a step. Patterning is performed such that a predetermined portion of the first insulating layer 28 is exposed. The first and second insulating films 28 and 29, like nitride, are formed on the third insulating film 31 so as to cover the surfaces of the holes formed in the third and second insulating films 31 and 29 by the patterning. A material having a different etch selectivity is deposited and etched back to form a nitride sidewall 33 on the side of the hole.
그런 후에, 도 2d에 나타낸 바와 같이 질화물로 형성된 상기 제 3 절연막 및 질화물 측벽(31)(33)을 마스크로 사용하여 산화물 습식식각을 하면 상기 반도체기판(21) 불순물영역(27)의 소정 부분을 노출시키는 접촉홀(35)이 형성된다.After that, as shown in FIG. 2D, oxide wet etching is performed using the third insulating film and the nitride sidewalls 31 and 33 formed of nitride as a mask, thereby forming a predetermined portion of the impurity region 27 of the semiconductor substrate 21. A contact hole 35 for exposing is formed.
상술한 바와 같이 본 발명에서는 반도체기판 상에 불순물영역 및 게이트를 포함하는 트랜지스터를 형성하고 상기 반도체기판 상에 상기 트랜지스터를 덮는 평탄한 산화막 및 질화막을 형성하고 상기 산화막 및 질화막을 상기 게이트의 높이까지 건식식각한 후 질화물측벽을 형성하여 잔류하는 산화막은 습식식각하여 상기 반도체기판 불순물영역의 소정 부분을 노출시키는 접촉홀을 형성하였다.As described above, in the present invention, a transistor including an impurity region and a gate is formed on a semiconductor substrate, and a flat oxide film and a nitride film are formed on the semiconductor substrate to cover the transistor, and the oxide and nitride film are dry-etched to the height of the gate. After that, the nitride side wall was formed to wet the remaining oxide film to form a contact hole exposing a predetermined portion of the semiconductor substrate impurity region.
따라서, 본 발명에 따라 제조된 반도체소자는 불순물영역의 소정 부분을 노출시키는 접촉홀을 형성하기 위해 건식식각과 습식식각을 같이 사용하여 접촉홀의 폭이 넓어지는 것을 방지하는 한편 건식식각에 의한 반도체기판의 로스와 산화물과 질화물의 고식각선택비에 의해 플러그와 게이트가 연결되는 브리지를 방지하여 반도체소자 특성의 열화를 방지하는 잇점이 있다.Therefore, the semiconductor device manufactured according to the present invention prevents the width of the contact hole from being widened by using both dry etching and wet etching to form contact holes for exposing a predetermined portion of the impurity region. Due to the high etch selectivity of the oxide and the nitride and the high etch selectivity, the bridge between the plug and the gate is prevented, thereby deteriorating the characteristics of the semiconductor device.
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| KR100652361B1 (en) * | 2000-09-08 | 2006-11-30 | 삼성전자주식회사 | Method for fabricating a semiconductor device using self aligned contact |
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