KR100226767B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100226767B1 KR100226767B1 KR1019960043852A KR19960043852A KR100226767B1 KR 100226767 B1 KR100226767 B1 KR 100226767B1 KR 1019960043852 A KR1019960043852 A KR 1019960043852A KR 19960043852 A KR19960043852 A KR 19960043852A KR 100226767 B1 KR100226767 B1 KR 100226767B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트에 손상을 주지 않으면서 평탄화시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that flattens a gate without damaging the gate.
이를 위한 본 발명의 반도체 소자의 제조 방법은 기판상에 제 1 , 제 2 캡 절연막을 구비한 게이트 전극을 형성하는 단계, 전면에 제 3 절연막을 형성하는 단계와 상기 제 3 절연막과 제 2 캡 절연막을 에치백하는 단계를 포함하여 이루어짐을 특징으로 한다.The method for fabricating a semiconductor device of the present invention includes the steps of forming a gate electrode having first and second cap insulating films on a substrate, forming a third insulating film on the entire surface, And performing an etch-back process.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트에 손상을 주지 않으면서 평탄화시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that flattens a gate without damaging the gate.
디바이스(Device)의 집적도가 커질수록 디자인 룰(Design Rule)이 점점 작아짐에 따라 게이트 라인 피치(Gate Line Pitch)가 점점 줄어 들면서 이후 셀 콘택을 형셩하기 위한 노광시 평탄도 문제에 따라 노광 문제가 대두 될 수 있다. 이에 따라 BPSG(Boron Phosphrus Silicate Glass)를 비롯한 평탄화용 절연막을 에치백(Etch Back)시 게이트 손상이 적고, 평탄도 측면에서도 우수한 공정이 필요하게 되었다.As the degree of integration of the device increases, the design rule becomes smaller and the gate line pitch gradually decreases. Thereafter, the exposure problem occurs due to the flatness problem at the time of forming the cell contact. . Accordingly, an insulating film for planarization including BPSG (Boron Phosphorus Silicate Glass) is required to have a superior process in terms of flatness and less damage to the gate during etchback.
이하 첨부된 도면을 참고하여 종래의 반도체 소자의 제조 방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1C are process sectional views showing a conventional method of manufacturing a semiconductor device.
도 1a에서와 같이, 반도체 기판(11)상에 차례로 산화막, 다결정 실리콘, 질화막과 감광막(14)을 형성한 다음, 상기 감광막(14)을 게이트가 형성될 부위만 남도록 선택적으로 노광 및 현상한다.1A, an oxide film, a polycrystalline silicon film, a nitride film and a photoresist film 14 are sequentially formed on a semiconductor substrate 11, and then the photoresist film 14 is selectively exposed and developed such that only a portion where a gate is to be formed is left.
상기 선택적으로 노광 및 현상된 감광막(14)을 마스크로 이용하여 차례로 상기 산화막, 다결정 실리콘과 질화막을 선택적으로 식각하여 게이트 산화막(16)과 게이트 캡 질화막(13)을 구비한 다수개의 게이트(12)들을 형성한 후, 상기 감광막(14)을 제거한다. 여기서 상기 질화막 대신 산화막을 성장시켜 게이트 캡 산화막을 사용해도 괜찮다.A plurality of gates 12 having a gate oxide film 16 and a gate cap nitride film 13 selectively etching the oxide film, the polycrystalline silicon film, and the nitride film sequentially using the selectively exposed and developed photoresist film 14 as a mask, The photoresist film 14 is removed. A gate cap oxide film may be used instead of the nitride film by growing an oxide film.
도 1b에서와 같이, 상기 게이트(12)와 게이트 캡 질화막(13)을 포함한 반도체 기판(11)상에 BPSG층(15)을 형성한다.The BPSG layer 15 is formed on the semiconductor substrate 11 including the gate 12 and the gate cap nitride film 13 as shown in FIG.
도 1c에서와 같이, 상기 BPSG층(15)을 상기 게이트 캡 질화막(13)상측에 일정 두께로 남도록 에치백한다.As shown in FIG. 1C, the BPSG layer 15 is etched back to a predetermined thickness on the gate cap nitride film 13.
종래의 반도체 소자의 제조 방법은 하나의 게이트 캡 절연막을 사용하므로 평탄화를 위한 에치백 공정시 게이트에 손상을 주지 않기 위해서 에치백량을 정확하게 제어해야 하고, 이로 인하여 셀 단차가 커지는 문제점이 있었다.In the conventional method of manufacturing a semiconductor device, since one gate cap insulating film is used, the etch back amount must be accurately controlled in order to prevent damage to the gate during the etch back process for planarization, thereby increasing the cell pitch.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 두층의 게이트 캡 절연막을 형성하므로 평탄화를 위한 에치백 공정시 게이트에 손상을 주지 않으며, 셀 단차가 작아지는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a gate cap insulation layer is formed in two layers, .
제1a,1c도의 종래의 반도체 소자의 제조 방법을 나타낸 공정 단면도1A and 1C are cross-sectional views showing the steps of a conventional method of manufacturing a semiconductor device
제2a,2c도는 본 발명의 실시에에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도Figs. 2a and 2c are process sectional views showing a method for manufacturing a semiconductor device according to the embodiment of the present invention
도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
31 : 반도체 기판 32 : 게이트31: semiconductor substrate 32: gate
33 : 게이트 캡 질화막 34 : 게이트 캡 산화막33: gate cap nitride film 34: gate cap oxide film
35 : 감광막 36 : BPSG35: photosensitive film 36: BPSG
본 발명에 따른 반도체 소자의 제조 방법은 기판상에 제 1, 제 2 캡 절연막을 구비한 게이트 전극을 형성하는 단계, 전면에 제 3 절연막을 형성하는 단계와 상기 제 3 절연막과 제 2 캡 절연막을 에치백하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a gate electrode having first and second cap insulating films on a substrate, forming a third insulating film on the entire surface, And performing an etch-back process.
상기와 같은 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 2a에서와 같이, 반도체 기판(31)상에 차례로 제 1 산화막, 다결정 실리콘, 질화막, 제 2 산화막, 감광막(35)을 형성한 다음, 상기 감광막(35)을 게이트가 형성될 부위만 남도록 선택적으로 노광 및 현상한다.2A, a first oxide film, a polycrystalline silicon film, a nitride film, a second oxide film, and a photoresist film 35 are sequentially formed on a semiconductor substrate 31, and then the photoresist film 35 is selectively As shown in FIG.
여기서 상기 질화막을 100∼2000Å의 두께로, 제 2 산화막을 1000∼5000Å의 두께로 형성한다. 상기 선택적으로 노광 및 현상된 감광막(35)을 마스크로 이용하여 차례로 상기 제 1 산화막, 다결정 실리콘과, 질화막과, 제 2 산화막을 선택적으로 식각하여 게이트 산화막(37), 게이트 캡 질화막(33)과 게이트 캡 산화막(34)을 구비한 다수개의 게이트(32)들을 형성한 후, 상기 감광막(35)을 제거한다.Here, the nitride film is formed to a thickness of 100 to 2000 ANGSTROM, and the second oxide film is formed to a thickness of 1000 to 5000 ANGSTROM. The first oxide film, the polycrystalline silicon film, the nitride film, and the second oxide film are selectively etched by using the selectively exposed and developed photoresist film 35 as a mask to sequentially form the gate oxide film 37, the gate cap nitride film 33, After forming the plurality of gates 32 having the gate cap oxide film 34, the photoresist film 35 is removed.
도 2b에서와 같이, 상기 게이트(32)와 게이트 캡 질화막(33)과 게이트 캡 산화막(34)을 포함한 반도체 기판(31)상에 5000∼12,000Å의 두께를 갖는 BPSG층(36)을 형성한다.2B, a BPSG layer 36 having a thickness of 5000 to 12,000 ANGSTROM is formed on the semiconductor substrate 31 including the gate 32, the gate cap nitride film 33, and the gate cap oxide film 34 .
도 2c에서와 같이, 상기 BPSG층(36)과 게이트 캡 산화막(34)을 벌크 에치백(Bulk Etch Back)한다.As shown in FIG. 2C, the BPSG layer 36 and the gate cap oxide film 34 are bulk etched back to the bulk.
여기서 식각조건은 균일도를 2%이하로 하고, 질화막과의 선택비를 20:1이상으로 유지하며 CH3F/C3F8/CO 가스를 이용하여 식각한다. 또 상기 게이트 캡 질화막(33)을 종말점 검출로 사용하여 상기 게이트 캡 질화막(33)에서 에치스톱(Etch Stop)한다.In this case, the etching condition is to etch using CH 3 F / C 3 F 8 / CO gas with a uniformity of 2% or less and a selectivity ratio to the nitride film of 20: 1 or more. Etch stop is performed on the gate cap nitride film 33 by using the gate cap nitride film 33 as the end point detection.
본 발명의 반도체 소자의 제조 방법은 두층의 게이트 캡 절연막을 형성하므로 평탄화를 위한 에치백 공정시 게이트에 손상을 주지 않으면서 깊게 에치백을 하여 셀 단차가 적기 때문에 칩의 두께를 작게하는 효과가 있다.Since the method of manufacturing a semiconductor device of the present invention forms a gate cap insulating film of two layers, the etch-back process for planarization does not damage the gate, and etch back is performed deeply to reduce the thickness of the chip .
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960043852A KR100226767B1 (en) | 1996-10-04 | 1996-10-04 | Method of manufacturing semiconductor device |
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|---|---|---|---|
| KR1019960043852A KR100226767B1 (en) | 1996-10-04 | 1996-10-04 | Method of manufacturing semiconductor device |
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| Publication Number | Publication Date |
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| KR19980025631A KR19980025631A (en) | 1998-07-15 |
| KR100226767B1 true KR100226767B1 (en) | 1999-10-15 |
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| KR1019960043852A KR100226767B1 (en) | 1996-10-04 | 1996-10-04 | Method of manufacturing semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169828A (en) * | 2011-03-10 | 2011-08-31 | 上海宏力半导体制造有限公司 | Method for forming grid electrode structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000077625A (en) * | 1998-08-31 | 2000-03-14 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930011298A (en) * | 1991-11-16 | 1993-06-24 | 문정환 | MOSFET manufacturing method and structure |
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- 1996-10-04 KR KR1019960043852A patent/KR100226767B1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930011298A (en) * | 1991-11-16 | 1993-06-24 | 문정환 | MOSFET manufacturing method and structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169828A (en) * | 2011-03-10 | 2011-08-31 | 上海宏力半导体制造有限公司 | Method for forming grid electrode structure |
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| KR19980025631A (en) | 1998-07-15 |
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