KR100524812B1 - A forming method of bitline using ArF photolithography - Google Patents
A forming method of bitline using ArF photolithography Download PDFInfo
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- KR100524812B1 KR100524812B1 KR10-2001-0037411A KR20010037411A KR100524812B1 KR 100524812 B1 KR100524812 B1 KR 100524812B1 KR 20010037411 A KR20010037411 A KR 20010037411A KR 100524812 B1 KR100524812 B1 KR 100524812B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 불화아르곤 전사법을 이용한 비트라인 형성 방법에 관한 것이다. 본 발명은, 비트라인 형성시 ArF 전사법을 이용하여 PR 패턴을 형성한 후 전자빔 조사 등을 이용하여 PR 패턴을 경화시켜 식각 내성을 향상시킨 후 PR 패턴 상에 일정 두께의 폴리머를 형성시켜 PR 패턴을 보호함으로써, PR 패턴의 변형을 방지하여 좁은 패턴을 형성할 수 있는 ArF 전사법을 이용한 비트라인 형성 방법을 제공하는데 그 목적이 있다. 이를 위해 본 발명은, 소정 공정이 완료된 기판 상에 비트라인 콘택 플러그를 형성하는 제1단계; 상기 비트라인 콘택 플러그 상에 층간절연막과 불화아르곤 전사법을 이용한 포토레지스트 패턴을 차례로 형성하는 제2단계; 상기 포토레지스트 패턴 표면을 경화시키는 제3단계; 상기 경화된 포토레지스트 패턴 상에 가스를 이용하여 일정 두께의 폴리머를 형성하는 제4단계; 상기 폴리머가 형성된 포토레지스트 패턴을 마스크로하여 상기 층간절연막을 선택적으로 식각하여 상기 콘택 플러그 표면을 노출시키는 콘택홀을 형성하는 제5단계; 및 상기 콘택홀에 콘택된 비트라인을 형성하는 제6단계를 포함하여 이루어지는 불화아르곤 전사법을 이용한 비트라인 형성 방법을 제공한다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a bit line forming method using an argon fluoride transfer method. In the present invention, the PR pattern is formed by using an ArF transfer method when forming a bit line, and then the PR pattern is cured by using electron beam irradiation to improve etching resistance, and then a polymer having a predetermined thickness is formed on the PR pattern. The purpose of the present invention is to provide a method for forming a bit line using an ArF transfer method capable of forming a narrow pattern by preventing deformation of a PR pattern. To this end, the present invention, the first step of forming a bit line contact plug on the substrate is completed a predetermined process; A second step of sequentially forming an interlayer insulating film and a photoresist pattern using an argon fluoride transfer method on the bit line contact plugs; Hardening the surface of the photoresist pattern; A fourth step of forming a polymer having a predetermined thickness by using a gas on the cured photoresist pattern; A fifth step of forming a contact hole exposing the surface of the contact plug by selectively etching the interlayer insulating layer using the photoresist pattern on which the polymer is formed as a mask; And a sixth step of forming a bit line contacted to the contact hole.
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로 특히, ArF 포토레지스트를 이용한 비트라인(Bitline) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a bitline using ArF photoresist.
반도체 소자의 집적도가 증가함에 따라 전사법(Photo lithography) 공정의 오정렬(Mis-alignment) 마진 감소로 인해 직접 콘택(Direct contact) 방식에 의해서는 효과적으로 액티브 오픈 영역(Active open area)을 확보하는데 어려움이 있다. 이를 개선하기 위해 이종의 절연막질간 예컨대, 산화막과 질화막등의 식각선택비 차이를 이용하는 자기 정렬 콘택(Self Align Contact;이하 SAC라 함) 공정 방법이 개발되었다.As the degree of integration of semiconductor devices increases, it is difficult to effectively secure an active open area by the direct contact method due to the decrease in misalignment margin of the photo lithography process. have. In order to improve this problem, a self-aligned contact process (hereinafter referred to as SAC) using a difference in etching selectivity between heterogeneous insulating films, for example, an oxide film and a nitride film, has been developed.
한편, 반도체 소자의 진전을 지지해 온 미세 가공 기술은 광 전사법 기술이다. 즉, 이 기술의 해상력 향상이 반도체 소자의 고집적화의 장래를 맞고 있다고 해도 과언은 아니다On the other hand, the microfabrication technique which has supported the progress of the semiconductor element is the optical transfer technique. In other words, it is no exaggeration to say that the improvement in resolution of this technology is facing the future of high integration of semiconductor devices.
그러나, 디자인 룰의 감소에 따라 기존에 사용하던 KrF 포토레지스트(Photo Resist; 이하 PR이라 함)로는 해상도의 한계에 부딪히게 되어 이를 보완하기 위해 최근 ArF PR을 사용하고자 하는 일련의 연구가 진행되고 있다. However, with the reduction of design rules, the KrF photoresist (PR) (hereinafter referred to as PR), which has been used previously, encounters a limitation in resolution, and a series of studies are recently underway to use ArF PR to compensate for this. .
통상적인 비트라인 형성 공정은 설명하면, 도전층 패턴 즉, 게이트 전극 사이에 SAC 공정을 이용하여 콘택홀을 형성하고 콘택홀 내부에 폴리실리콘 플러그를 증착 및 에치 백(Etch back) 공정을 실시한 다음, 절연막을 증착하고 폴리시리콘 플러그 배선과 비트라인간의 통전을 위한 비트라인 콘택 공정을 실시한다.In the conventional bit line forming process, a contact hole is formed using a conductive layer pattern, that is, a SAC process between gate electrodes, and a polysilicon plug is deposited and etched back inside the contact hole. An insulating film is deposited and a bit line contact process for conducting electricity between the polysilicon plug wiring and the bit line is performed.
비트라인 콘택 공정시 일반적인 콘택홀 형성 공정에 의해 공정을 진행할 경우 전사법(Lithigraphy)의 한계에 의해 ArF를 이용한 전사법을 이용하더라도 0.1㎛ 이하의 콘택홀을 형성하는 것은 한계로 여겨진다.In the case of the bit line contact process, when the process is performed by a general contact hole forming process, it is considered to form a contact hole of 0.1 μm or less due to the limitation of lithigraphy even if a transfer method using ArF is used.
도 1은 상기한 바와 같은 문제점을 도시한 사진으로, 종래의 ArF 전사법을 이용한 콘택 형성시 식각 단계가 진행됨에 따라 콘택홀 모양이 매우 불규칙하게 되는 과정을 도시한다.FIG. 1 is a photograph illustrating a problem as described above, and illustrates a process in which a contact hole shape becomes very irregular as an etching step is performed when forming a contact using a conventional ArF transfer method.
도 1을 참조하면, 활성층(1)이 형성되어 있고, 활성층(1)과 교차하는 방향으로 워드라인(3)이 형성되어 있으며, 워드라인(3)에 교차 중첩되며 활성층과 오버랩되는 비트라인(2) 형성되어 있다. 비트라인(2)은 비트라인 콘택(4)을 통해 활성층에 통전되어 있다.Referring to FIG. 1, an active layer 1 is formed, a word line 3 is formed in a direction crossing the active layer 1, and a bit line that overlaps the word line 3 and overlaps the active layer ( 2) is formed. The bit line 2 is energized to the active layer via the bit line contact 4.
한편, 이러한 문제점을 해결하기 위해 PR 패턴 형성 후 리플로우를 실시하여 콘택 형성 예정 영역보다 작은 콘택을 형성하는 방법을 시도하고 있는 바, 포토레지스트 패턴 임계치수(Develop Inspection Critical Dimention; 이하 DiCD라 함)의 감쇠 정도를 통해 DICD의 향상은 도모할 수는 있으나, 리플로우에 따른 PR 두께의 감소에 따라 재현성이 떨어지며, ArF PR을 사용하더라도 90㎚ 정도가 한계이다.In order to solve this problem, a method of forming a contact smaller than a contact formation area by performing a reflow after forming a PR pattern has been attempted, and thus a photoresist pattern critical dimension (hereinafter referred to as DiCD) The improvement of DICD can be achieved by the degree of attenuation of, but the reproducibility decreases as the PR thickness decreases due to reflow, and even 90 nm is limited even when ArF PR is used.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 비트라인 형성시 ArF 전사법을 이용하여 PR 패턴을 형성한 후 전자빔 조사 등을 이용하여 PR 패턴을 경화시켜 식각 내성을 향상시킨 후 PR 패턴 상에 일정 두께의 폴리머를 형성시켜 PR 패턴을 보호함으로써, PR 패턴의 변형을 방지하여 좁은 패턴을 형성할 수 있는 ArF 전사법을 이용한 비트라인 형성 방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, after forming the PR pattern by using the ArF transfer method when forming the bit line after curing the PR pattern by using electron beam irradiation, etc. to improve the etching resistance It is an object of the present invention to provide a bit line forming method using an ArF transfer method capable of forming a narrow pattern by preventing a deformation of a PR pattern by forming a polymer having a predetermined thickness on the PR pattern to protect the PR pattern.
상기와 같은 문제점을 해결하기 위해 본 발명은, 소정 공정이 완료된 기판 상에 비트라인 콘택 플러그를 형성하는 제1단계; 상기 비트라인 콘택 플러그 상에 층간절연막과 불화아르곤 전사법을 이용한 포토레지스트 패턴을 차례로 형성하는 제2단계; 상기 포토레지스트 패턴 표면을 경화시키는 제3단계; 상기 경화된 포토레지스트 패턴 상에 가스를 이용하여 일정 두께의 폴리머를 형성하는 제4단계; 상기 폴리머가 형성된 포토레지스트 패턴을 마스크로하여 상기 층간절연막을 선택적으로 식각하여 상기 콘택 플러그 표면을 노출시키는 콘택홀을 형성하는 제5단계; 및 상기 콘택홀에 콘택된 비트라인을 형성하는 제6단계를 포함하여 이루어지는 불화아르곤 전사법을 이용한 비트라인 형성 방법을 제공한다.In order to solve the above problems, the present invention, the first step of forming a bit line contact plug on the substrate is completed a predetermined process; A second step of sequentially forming an interlayer insulating film and a photoresist pattern using an argon fluoride transfer method on the bit line contact plugs; Hardening the surface of the photoresist pattern; A fourth step of forming a polymer having a predetermined thickness by using a gas on the cured photoresist pattern; A fifth step of forming a contact hole exposing the surface of the contact plug by selectively etching the interlayer insulating layer using the photoresist pattern on which the polymer is formed as a mask; And a sixth step of forming a bit line contacted to the contact hole.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도 2a 내지 도 2e를 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 ArF 전사법을 이용한 비트라인 형성 공정을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a bit line forming process using an ArF transfer method according to an embodiment of the present invention.
먼저 도 2a에 도시된 바와 같이, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(10) 상에 소스/드레인 등의 활성층(11)을 형성한 후, 층간절연막(12)을 형성한 다음, 층간절연막(12)을 선택적으로 식각하여 활성층(11)에 콘택되는 비트라인 콘택 플러그(13)를 형성한 후, 평탄화 공정을 실시한다. 이어서, 결과물 상부에 층간절연막(14)을 형성한다.First, as shown in FIG. 2A, an active layer 11, such as a source / drain, is formed on a substrate 10 on which various elements for forming a semiconductor device are formed, and then an interlayer insulating film 12 is formed. After the insulating film 12 is selectively etched to form the bit line contact plug 13 contacting the active layer 11, a planarization process is performed. Next, an interlayer insulating film 14 is formed on the resultant.
여기서, 비트라인 콘택 플러그(13)는, 단결정 폴리실리콘(SEG: Selective epitaxy growth) 또는 다결정 폴리실리콘(tube polysilicon) 등을 이용하며, 층간절연막(12, 14)은 APL(Advanced Planarization Layer) 산화막, BPSG(Boro Phospho Silicate Glass), SOG(Spin On Glass), HDP(High Density Plasma) 산화막 또는 질화막 등을 이용한다.Here, the bit line contact plug 13 may be formed of monocrystalline polysilicon (SEG), polycrystalline polysilicon (tube polysilicon), or the like, and the interlayer insulating films 12 and 14 may include an APL (Advanced Planarization Layer) oxide film, BPSG (Boro Phospho Silicate Glass), SOG (Spin On Glass), HDP (High Density Plasma) oxide film or nitride film is used.
다음으로 도 2b에 도시된 바와 같이, 비트라인 콘택 플러그(13) 상에 PR을 도포한 후, ArF 전사법을 이용하여 PR 패턴(15)을 형성한 후, PR 패턴(15)의 표면을 경화시켜 식각 내성을 향상시킨다.Next, as shown in FIG. 2B, after the PR is applied on the bit line contact plug 13, the PR pattern 15 is formed by using an ArF transfer method, and then the surface of the PR pattern 15 is cured. To improve the etching resistance.
여기서, PR은 아트릴레이드(Acrylate) 또는 COMA(CycloOlefin-maleic Anhydride)를 이용하며, 경화시, Ar 이온주입 또는 전자빔 주사 등을 이용한다. 한편, 전자빔 주사시 PR 패턴(15)의 수축에 따른 패턴 변형을 초래할 수 있으므로 적절한 에너지를 이용하는 바, 400 uC/㎤ ∼ 3000 uC/㎤ 범위로 한다.Here, the PR uses Acrylate or COMA (CycloOlefin-maleic Anhydride), and during curing, Ar ion implantation or electron beam scanning is used. On the other hand, since the pattern deformation due to shrinkage of the PR pattern 15 may be caused during electron beam scanning, an appropriate energy is used, so that the range is 400 uC / cm 3 to 3000 uC / cm 3.
다음으로 도 2c에 도시된 바와 같이, PR 패턴(15) 상에 일정 두께의 폴리머(16)를 형성한다.Next, as shown in FIG. 2C, a polymer 16 having a predetermined thickness is formed on the PR pattern 15.
구체적으로, 5 SCCM 내지 20 SCCM의 C4F6, 5 SCCM 내지 20 SCCM의 C4F8, 5 SCCM 내지 20 SCCM의 CH2F2, 100 SCCM 내지 1000 SCCM의 Ar 또는 이들의 혼합 가스를 이용하여 50Å 내지 500Å의 두께가 되도록 한다. 이 때, 25℃ 내지 80℃의 온도와 10 mTorr 내지 50 mTorr의 압력 및 1000W 내지 2000W의 파워 하에서 10초 내지 60초 동안 실시하며, 이렇게 생성된 폴리머(16)는 탄소와 불소, 수소기체가 함유된 것을 특징으로 하며 식각시 PR 패턴(15)을 보호하여 재현성을 높여주며, 그 두께 증가분만큼 좁은 콘택 영역 형성을 할 수 있도록 한다.Specifically, the thickness of 50 kPa to 500 kPa is set using 5 SCCM to 20 SCCM of C4F6, 5 SCCM to 20 SCCM of C4F8, 5 SCCM to 20 SCCM of CH2F2, 100 SCCM to 1000 SCCM of Ar, or a mixed gas thereof. . At this time, it is carried out for 10 seconds to 60 seconds at a temperature of 25 ℃ to 80 ℃, a pressure of 10 mTorr to 50 mTorr and a power of 1000W to 2000W, the polymer 16 thus produced contains carbon, fluorine, hydrogen gas Characterized in that it protects the PR pattern 15 during etching to increase the reproducibility, it is possible to form a narrow contact area by the thickness increase.
다음으로 도 2d에 도시된 바와 같이, PR 패턴(15)을 마스크로하여 층간절연막(14)을 선택적으로 식각하여 콘택 플러그(13) 표면을 노출시키는 콘택홀(17)을 형성한 후, 폴리머(16) 및 PR 패턴(15)을 제거한다.Next, as illustrated in FIG. 2D, the interlayer insulating film 14 is selectively etched using the PR pattern 15 as a mask to form a contact hole 17 exposing the surface of the contact plug 13, and then a polymer ( 16) and PR pattern 15 are removed.
다음으로 도 2e에 도시된 바와 같이, 콘택홀(17)에 콘택되는 비트라인(18)을 형성한다. 여기서 비트라인(18)은, W, Ti 또는 Co 등을 이용한다.Next, as shown in FIG. 2E, a bit line 18 contacting the contact hole 17 is formed. Here, the bit line 18 uses W, Ti, Co, or the like.
여기서, 비트라인(18)은 플러그(13)와의 접촉 계면에 배리어막(도시하지 않음)을 갖는 바, 배리어막(도시하지 않음)은 화학기상 증착법(CVD) 또는 물리기상 증착법(PVD)에 의한 Ti, TiN 또는 이들이 적층된 것을 이용한다.Here, the bit line 18 has a barrier film (not shown) at the contact interface with the plug 13, and the barrier film (not shown) is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Ti, TiN, or a laminate of these are used.
상기한 바와 같이 이루어지는 본 발명은, ArF PR을 이용한 비트라인 형성시, ArF를 리플로우 시킨 후 그 상부에 폴리머를 형성함으로써, 좁은 패턴을 형성할 수 있으며, 재현성을 향상시킬 수 있음을 실시예를 통해 알아 보았다.In the present invention made as described above, when forming a bit line using ArF PR, by reflowing ArF and then forming a polymer thereon, a narrow pattern can be formed and reproducibility can be improved. I found out.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은, 불화아르곤 전사법에 의해 형성된 포토레지스트 패턴 상에 폴리머를 형성함으로써, 포토레지스트 패턴의 변형을 방지하며 좁은 패턴 형성과 재현성을 향상시킬 수 있도록 하여, 긍극적으로 소자의 집적도를 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above, by forming a polymer on the photoresist pattern formed by the argon fluoride transfer method, it is possible to prevent the deformation of the photoresist pattern and to improve the narrow pattern formation and reproducibility, ultimately improve the integration degree of the device You can expect an excellent effect that can be improved.
도 1은 종래의 ArF 전사법을 이용한 콘택 형성시 식각 단계가 진행됨에 따라 콘택홀 모양이 매우 불규칙하게 되는 과정을 도시한 사진,1 is a photograph showing a process in which the contact hole shape becomes very irregular as the etching step proceeds when forming a contact using a conventional ArF transfer method;
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 ArF 전사법을 이용한 비트라인 형성 공정을 도시한 단면도.2A to 2E are cross-sectional views illustrating a bit line forming process using an ArF transfer method according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 기판10: substrate
11 : 활성층11: active layer
12, 14 : 층간절연막12, 14: interlayer insulating film
13 : 비트라인 콘택 플러그13: bitline contact plug
18 : 비트라인18: bit line
Claims (9)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0037411A KR100524812B1 (en) | 2001-06-28 | 2001-06-28 | A forming method of bitline using ArF photolithography |
| US10/166,421 US7125496B2 (en) | 2001-06-28 | 2002-06-10 | Etching method using photoresist etch barrier |
| DE10225925A DE10225925B4 (en) | 2001-06-28 | 2002-06-11 | Etching process using a photoresist etching barrier |
| JP2002184629A JP4389242B2 (en) | 2001-06-28 | 2002-06-25 | Etching method using photoresist pattern as mask |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0037411A KR100524812B1 (en) | 2001-06-28 | 2001-06-28 | A forming method of bitline using ArF photolithography |
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| KR20030001081A KR20030001081A (en) | 2003-01-06 |
| KR100524812B1 true KR100524812B1 (en) | 2005-11-02 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970018057A (en) * | 1995-09-26 | 1997-04-30 | 김광호 | Fine Pattern Formation Method of Semiconductor Device |
| KR970023633A (en) * | 1995-10-16 | 1997-05-30 | 김광호 | Pattern Forming Method of Semiconductor Device Using Negative Photoresist |
| KR19990069618A (en) * | 1998-02-11 | 1999-09-06 | 윤종용 | Method of forming fine contact hole in semiconductor device |
| KR20000001567A (en) * | 1998-06-12 | 2000-01-15 | 윤종용 | Method of forming a pattern which is capable of minimizing a size affect according to a resolution limit of photo masking process and a structure thereof |
| KR20000009374A (en) * | 1998-07-23 | 2000-02-15 | 윤종용 | Fabrication method of semiconductor devices for reducing a space between pattekun |
| JP2000356850A (en) * | 1999-04-21 | 2000-12-26 | Samsung Electronics Co Ltd | Resist composition and fine pattern forming method using same |
| KR20010005154A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fine pattern forming method using resist flow process |
| KR20010047179A (en) * | 1999-11-18 | 2001-06-15 | 박종섭 | Manufacturing method for contact hole in semiconductor device |
-
2001
- 2001-06-28 KR KR10-2001-0037411A patent/KR100524812B1/en not_active IP Right Cessation
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970018057A (en) * | 1995-09-26 | 1997-04-30 | 김광호 | Fine Pattern Formation Method of Semiconductor Device |
| KR970023633A (en) * | 1995-10-16 | 1997-05-30 | 김광호 | Pattern Forming Method of Semiconductor Device Using Negative Photoresist |
| KR19990069618A (en) * | 1998-02-11 | 1999-09-06 | 윤종용 | Method of forming fine contact hole in semiconductor device |
| KR20000001567A (en) * | 1998-06-12 | 2000-01-15 | 윤종용 | Method of forming a pattern which is capable of minimizing a size affect according to a resolution limit of photo masking process and a structure thereof |
| KR20000009374A (en) * | 1998-07-23 | 2000-02-15 | 윤종용 | Fabrication method of semiconductor devices for reducing a space between pattekun |
| JP2000356850A (en) * | 1999-04-21 | 2000-12-26 | Samsung Electronics Co Ltd | Resist composition and fine pattern forming method using same |
| KR20010005154A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fine pattern forming method using resist flow process |
| KR20010047179A (en) * | 1999-11-18 | 2001-06-15 | 박종섭 | Manufacturing method for contact hole in semiconductor device |
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| KR20030001081A (en) | 2003-01-06 |
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