KR100200308B1 - Method for forming a contact hole of a semiconductor device - Google Patents
Method for forming a contact hole of a semiconductor device Download PDFInfo
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- KR100200308B1 KR100200308B1 KR1019960025728A KR19960025728A KR100200308B1 KR 100200308 B1 KR100200308 B1 KR 100200308B1 KR 1019960025728 A KR1019960025728 A KR 1019960025728A KR 19960025728 A KR19960025728 A KR 19960025728A KR 100200308 B1 KR100200308 B1 KR 100200308B1
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- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 반도체기판 상부에 게이트전극을 형성하고 상기 반도체기판의 전체표면상부에 자기정렬 콘택공정의 식각장벽층인 탄화막을 형성한 다음, 상기 반도체기판의 전체표면상부를 평탄화시키는 하부절연층을 형성하고 상기 하부절연층 상부에 PECVD 산화막을 일정두께 형성한 다음, 상기 PECVD 산화막 상부에 콘택마스크를 이용하여 감광막패턴을 형성하고 상기 감광막패턴을 마스크로하여 상기 PECVD 산화막과 하부절연층을 식각함으로써 상기 탄화막을 노출시킨 다음, 상기 감광막패턴을 마스크로하여 상기 탄화막을 식각함으로써 상기 감광막패턴을 제거하는 동시에 상기 반도체기판을 노출시키는 콘택홀을 형성하여 공정을 단순화시키며 자기정렬적으로 콘택홀을 형성함으로써 후속공정을 용이하게 하여 반도체소자의 생산성을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 다른 반도체소자의 고집적화를 향상시키는 기술이다.The present invention relates to a method for forming a contact hole in a semiconductor device, comprising forming a gate electrode on an upper surface of a semiconductor substrate, and forming a carbonization film as an etch barrier layer of a self-aligned contact process on an entire surface of the semiconductor substrate, A lower insulating layer is formed to planarize the entire upper surface, and a PECVD oxide film is formed to a predetermined thickness on the lower insulating layer. Then, a photoresist pattern is formed on the PECVD oxide layer using a contact mask, and the photoresist pattern is used as a mask. The PECVD oxide layer and the lower insulating layer are etched to expose the carbide layer, and the photoresist pattern is used as a mask to etch the carbide layer to remove the photoresist pattern and to form a contact hole for exposing the semiconductor substrate, thereby simplifying the process. Self-aligning contact holes facilitate subsequent processing As a result, it is a technology for improving the productivity of semiconductor devices, improving the characteristics and reliability of semiconductor devices, and improving the integration of other semiconductor devices.
Description
제1a도 내지 제1c도는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 게이트산화막11: semiconductor substrate 13: gate oxide film
15 : 게이트전극 17 : 마스크산화막15 gate electrode 17 mask oxide film
19 : 절연막 스페이서 21 : 중온산화막19 insulating film spacer 21 medium temperature oxide film
23 : 실리콘탄화막 25 : 하부절연층23 silicon carbide film 25 lower insulating layer
27 : PECVD 산화막 29 : 감광막패턴27 PECVD oxide film 29 Photosensitive film pattern
31 : 콘택홀31: contact hole
본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 특히 자기정렬적인 콘택과 자기정렬적인 접합을 형성하는 기술에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a technique for forming a self-aligned contact and a self-aligned junction.
반도체 메모리소자 중에서 디램은 반도체기판 상부에 게이트전극을 형성하고 상기 게이트전극과 게이트전극 사이에 형성된 소오스/드레인접합을 노출시키는 콘택홀을 형성한 다음, 상기 콘택홀을 통하여 상기 소오스/드레인접합에 접속되는 비트라인과 캐패시터를 형성하였다.Among semiconductor memory devices, a DRAM forms a gate electrode on a semiconductor substrate and forms a contact hole exposing a source / drain junction formed between the gate electrode and the gate electrode, and then connected to the source / drain junction through the contact hole. Bit lines and capacitors were formed.
최초에는 상기 게이트전극간의 폭이 넓어 상기 게이트전극과 비트라인 또는 상기 게이트전극과 캐패시터의 단락이 거의 없었다. 그러나, 반도체소자가 집적화됨에 따라 도전층 간의 단락현상이 발생하여 상기 게이트전극의 측벽에 산화막 스페이서를 형성하였다. 그리고, 반도체소자가 고집적화됨에 따라 상기 산화막 스페이서만으로는 상기 게이트전극의 절연을 충분하게 할 수 없게 됨으로써 상기 게이트전극의 사이에 형성되며 측벽에 질화막 스페이서가 형성되는 콘택홀을 자기정렬적으로 형성하게 되었다.Initially, the width between the gate electrodes was wide so that there was almost no short circuit between the gate electrode and bit line or the gate electrode and capacitor. However, as semiconductor devices are integrated, a short circuit between conductive layers occurs to form oxide spacers on sidewalls of the gate electrode. As the semiconductor device is highly integrated, insulation of the gate electrode cannot be sufficiently performed using only the oxide film spacers, thereby forming contact holes formed between the gate electrodes and having nitride spacers formed on sidewalls.
여기서, 상기 자기정렬적인 콘택홀 형성공정은 산화막 대 질화막의 식각선택비 차이가 15 이상이고 상기 질화막 대 산화막의 식각선택비 차이가 10 이상으로 구현될 때, 상기 식각선택비 차이를 이용하여 공정을 진행하였다.The self-aligned contact hole forming process may be performed by using an etching selectivity difference when an etching selectivity difference between an oxide layer and a nitride layer is 15 or more and an etching selectivity difference between the nitride layer and an oxide layer is 10 or more. Proceeded.
그러나, 상기 식각선택비 차이를 구현하기 어려워 실제공정에 적용하기 어렵고, 이로 인하여 상기 자기정렬적인 콘택홀 형성공정을 실시하기 어렵게 되었다.However, since it is difficult to implement the difference in the etching selectivity, it is difficult to apply to the actual process, thereby making it difficult to perform the self-aligned contact hole forming process.
상기한 현상으로 인하여, 고집적화된 반도체소자를 형성하기가 어렵게 되고, 상기 반도체소자의 고집적화에 따른 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.Due to the above phenomenon, it is difficult to form a highly integrated semiconductor device, and there is a problem in that the characteristics and reliability of the semiconductor device are degraded due to the high integration of the semiconductor device.
따라서, 본 발명은 상기한 문제점들을 해결하기 위하여, 산화막과 식각선택비 차이를 갖는 실리콘탄화막으로 식각장벽층을 형성하고 이를 이용하여 자기정렬적으로 콘택홀을 형성함으로써 후속공정을 용이하게 하는 반도체소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problems, the present invention provides a semiconductor barrier layer formed of a silicon carbide film having a difference in etching selectivity from an oxide layer and a contact hole in a self-aligned manner, thereby facilitating subsequent processes. It is an object of the present invention to provide a method for forming contact holes in a device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 콘택홀 형성방법의 특징은, 반도체기판 상부에 게이트전극을 형성하는 공정과, 상기 반도체기판의 전체표면상부에 자기정렬 콘택공정의 식각장벽층인 탄화막을 형성하는 공정과, 상기 반도체기판의 전체표면상부를 평탄화시키는 하부절연층을 형성하는 공정과, 상기 하부절연층 상부에 플라즈마 화학기상증착(Plasma Enhanced Chemical Vapor Deposition, 이하에서 PECVD라 함) 산화막을 일정두께 형성하는 공정과, 상기 PECVD 산화막 상부에 콘택마스크를 이용하여 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 PECVD 산화막과 하부절연층을 식각함으로써 상기 탄화막을 노출시키는 공정과, 상기 감광막패턴을 마스크로하여 상기 탄화막을 식각하므로써 상기 반도체기판을 노출시키는 콘택홀을 형성하는 동시에 상기 감광막패턴을 제거하는 공정을 포함하는 것이다.In order to achieve the above object, a method of forming a contact hole of a semiconductor device according to the present invention is a process of forming a gate electrode on an upper surface of a semiconductor substrate and an etching barrier layer of a self-aligned contact process on an entire surface of the semiconductor substrate. Forming a carbide film, forming a lower insulating layer to planarize the entire upper surface of the semiconductor substrate, and plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD) oxide film on the lower insulating layer. Forming a predetermined thickness, forming a photoresist pattern on the PECVD oxide layer using a contact mask, exposing the carbide film by etching the PECVD oxide layer and the lower insulating layer using the photoresist pattern as a mask; The semiconductor substrate is exposed by etching the carbonization film using the photoresist pattern as a mask. The method includes forming a contact hole and simultaneously removing the photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1c도는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 게이트 산화막(13), 게이트 전극(15), 마스크산화막(17) 및 절연막 스페이서(19)를 형성한다.First, the gate oxide film 13, the gate electrode 15, the mask oxide film 17, and the insulating film spacer 19 are formed on the semiconductor substrate 11.
그리고, 상기 전체표면상부에 완충막인 중온산화막(Middle Temperature Oxide, 이하에서 MTO 라 함)(21)을 일정두께 형성한다.Then, a middle temperature oxide film (hereinafter referred to as MTO) 21 is formed to have a predetermined thickness on the entire surface.
그리고, 상기 MTO(21) 상부에 자기정렬적인 콘택공정의 식각장벽층인 실리콘탄화막(SiC)(23)을 일정두께 형성한다.A silicon carbide film (SiC) 23, which is an etch barrier layer of a self-aligned contact process, is formed on the MTO 21.
이때, 상기 실리콘탄화막(23)은 SiH4와 CH4를 이용하여 형성한다.In this case, the silicon carbide film 23 is formed using SiH 4 and CH 4 .
여기서, 상기 실리콘탄화막(23)은 상기 반도체기판(11)을 구성하는 실리콘과의 계면에서 높은 격자결함을 유발하지 않아 상기 중온산화막(21)과 같은 별도의 완충막을 사용하지 않아도 된다.Here, the silicon carbide film 23 does not cause a high lattice defect at the interface with the silicon constituting the semiconductor substrate 11, so it is not necessary to use a separate buffer film such as the intermediate temperature oxide film 21.
그 다음에, 전체표면상부를 평탄화시키는 하부절연층(25)을 형성한다. 이때, 상기 하부절연층(25)은 비.피.에스.지.(Boro Phospho Sillicate Galss, 이하에서 BPSG라 함)와 같이 유동성이 우수한 절연물질로 형성한다.Next, a lower insulating layer 25 is formed to planarize the entire upper surface portion. At this time, the lower insulating layer 25 is formed of an insulating material having excellent fluidity, such as B.P.G. (Boro Phospho Sillicate Galss, hereinafter referred to as BPSG).
그리고, 상기 하부절연층(25) 상부에 PECVD 산화막(27)을 일정두께 형성한다.In addition, a PECVD oxide layer 27 is formed on the lower insulating layer 25 to have a predetermined thickness.
그리고, 상기 PECVD 산화막(27) 상부에 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(29)을 형성한다. (제1a도)The photoresist pattern 29 is formed on the PECVD oxide layer 27 by an exposure and development process using a contact mask (not shown). (Figure 1a)
그 다음에, 상기 감광막패턴(29)을 마스크로하여 상기 PECVD 산화막(27)과 하부절연층(25)을 순차적으로 식각함으로써 상기 실리콘탄화막(23)을 노출시킨다.Next, the silicon carbide film 23 is exposed by sequentially etching the PECVD oxide layer 27 and the lower insulating layer 25 using the photoresist pattern 29 as a mask.
이때, 상기 하부절연층(25) 식각공정은, 전원전압(source power) 1000 ~ 3000 와트(watt), 바이어스 전압(bias power) 0 ~ 1500 와트, C3F8가스유량 0 ~ 50 sccm, CO 가스유량 0 ~ 50sccm 그리고 Ar 가스유량을 0 ~ 50 sccm 으로 하여 실시한다.In this case, the etching process of the lower insulating layer 25, the source power (source power) 1000 ~ 3000 watts (watt), the bias voltage (bias power) 0 ~ 1500 watts, C 3 F 8 gas flow rate 0 ~ 50 sccm, CO The gas flow rate is 0 to 50 sccm and the Ar gas flow rate is 0 to 50 sccm.
여기서, 상기 C3F8가스는 상기 하부절연층(25)과 실리콘탄화막(23)의 높은 식각선택비 차이를 갖게 하기 위한 것으로서, CH4, C2F6, CHF3, C3F8또는 C4F8등의 가스로 대신할 수 있다. (제1b도)Here, the C 3 F 8 gas is to have a high etch selectivity difference between the lower insulating layer 25 and the silicon carbide film 23, and CH 4 , C 2 F 6 , CHF 3 , C 3 F 8 Or a gas such as C 4 F 8 . (Figure 1b)
그 다음에, 상기 감광막패턴(29)을 마스크로하여 상기 실리콘탄화막(23)과 중온산화막(21)을 식각함으로써 상기 반도체기판(11)을 노출시키는 콘택홀(31)을 형성한다.Thereafter, the silicon carbide film 23 and the warm oxide film 21 are etched using the photosensitive film pattern 29 as a mask to form a contact hole 31 exposing the semiconductor substrate 11.
이때, 상기 실리콘탄화막(23)과 중온산화막(21) 식각공정은, 산소가스를 이용하는 다음과 같은 식각조건으로 인하여 상기 감광막패턴(29) 역시 식각한다.At this time, in the etching process of the silicon carbide film 23 and the mesophilic oxide film 21, the photosensitive film pattern 29 is also etched due to the following etching conditions using oxygen gas.
여기서, 상기 실리콘탄화막(23)과 중온산화막(21) 식각조건은, 전원전압 1000 ~ 2000 와트, 바이어스 전압 0 ~ 1000 와트, CH3F 가스유량 0 ~ 50 sccm, O2가스유량 0 ~ 200 sccm 그리고 Ar 가스유량을 0 ~ 50sccm 으로 한다. (제1c도)Here, the etching conditions of the silicon carbide film 23 and the mesophilic oxide film 21 include a power supply voltage of 1000 to 2000 watts, a bias voltage of 0 to 1000 watts, a CH 3 F gas flow rate of 0 to 50 sccm, and an O 2 gas flow rate of 0 to 200. sccm and Ar gas flow rate is 0-50sccm. (Figure 1c)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 콘택홀 형성방법은, 자기정열적인 콘택홀 형성공정시 식각장벽층으로 실리콘탄화막을 사용함으로써 산화막과의 높은 식각선택비 차이를 가질 수 있어 자기정렬 콘택공정을 용이하게 실시하며 공정을 단순화시켜 반도체소자의 생산성을 향상시키고, 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 향상시키는 잇점이 있다.As described above, in the method of forming a contact hole of a semiconductor device according to the present invention, a silicon etch film is used as an etch barrier layer in a self-aligned contact hole forming process, and thus a high etch selectivity difference with an oxide film can be obtained. The process can be easily performed and the process can be simplified to improve the productivity of the semiconductor device, to improve the characteristics and reliability of the semiconductor device, and thus to improve the high integration of the semiconductor device.
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| KR1019960025728A KR100200308B1 (en) | 1996-06-29 | 1996-06-29 | Method for forming a contact hole of a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100431822B1 (en) * | 1999-12-28 | 2004-05-20 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100431822B1 (en) * | 1999-12-28 | 2004-05-20 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
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