KR20000045442A - Fabrication method of contacts for semiconductor device - Google Patents
Fabrication method of contacts for semiconductor device Download PDFInfo
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- KR20000045442A KR20000045442A KR1019980062000A KR19980062000A KR20000045442A KR 20000045442 A KR20000045442 A KR 20000045442A KR 1019980062000 A KR1019980062000 A KR 1019980062000A KR 19980062000 A KR19980062000 A KR 19980062000A KR 20000045442 A KR20000045442 A KR 20000045442A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 자기 정렬 콘택(self-alligned contact) 식각기술을 개선하여 고집적 소자의 콘택 형성시에 적합하도록한 반도체소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device, which is suitable for forming a highly integrated device by improving a self-alligned contact etching technique.
종래의 반도체소자의 콘택홀을 질화막(또는 oxynitride)을 사용하는 자기 정렬 콘택홀 형성방법(self-alligned contact)으로 형성함에 있어서 산화막 식각시 질화막에 대하여 매우 식각선택비를 확보하기 위하여 다량의 폴리머를 사용하는데, 이는 다음과 같이 설명되어진다.In forming a contact hole of a conventional semiconductor device using a self-alligned contact using a nitride film (or oxynitride), a large amount of polymer is used to secure an etch selectivity with respect to the nitride film during oxide etching. It is used as described below.
즉, 산화막의 경우 폴리머가 증착되면 산화막 식각시에 발생하는 부산물의 하나인 산소에 의하여 폴리머가 제거되므로써 식각이 계속 진행된다.That is, in the case of the oxide film, when the polymer is deposited, the etching continues by removing the polymer by oxygen, which is a by-product generated during the etching of the oxide film.
그러나, 질화막의 경우, 폴리머가 증착되면 폴리머를 제거할 수 있는 산소가 없기 때문에 질화막이 식각되는 것을 방해하므로써 식각이 산화막에 대하여 현저히 느리게 진행되어 산화막/질화막의 매우 높은 식각 선택비를 확보할 수 있다.However, in the case of the nitride film, since the deposition of the polymer does not have oxygen to remove the polymer, the nitride film is prevented from being etched, so that the etching proceeds significantly slower with respect to the oxide film, thereby obtaining a very high etching selectivity of the oxide film / nitride film. .
그러나, 폴리머를 사용한 산화막 식각시 콘택 코너 (질화막이 배선을 감싸고 있어 장벽역할을 하는 부분)에서의 질화막에 대한 식각 선택비가 콘택바닥(콘택이 열려야 하는 부분)보다 낮은 문제가 있어 장벽 역할을 하는 질화막이 손상되어 배선간 단락 문제가 발생할 수 있다.However, there is a problem that the etching selectivity for the nitride film at the contact corner (the part where the nitride film surrounds the wiring to act as a barrier) is lower than that of the contact floor (the part where the contact should open) when the oxide is etched using the polymer. This damage can cause short-circuit problems.
이러한 식각 특성으로인해 자기정렬 콘택 형성방법에 있어 산화막 식각시 콘택 코너에서 질화막에 대한 선택비를 확보하는 것이 무엇보다 중요하다.Due to these etching characteristics, it is important to secure the selectivity for the nitride film at the contact corner when the oxide film is etched in the self-aligned contact forming method.
이를 지향함에 따라 산화막 식각시 콘택 코너에서 질화막에 대한 선택비가 높은 콘택 바닥에서 질화막 식각이 미미하게 진행되므로 산화막 식각후 반드시 질화막 식각 단계가 요구된다.To this end, since the etching of the nitride film proceeds slightly at the contact bottom where the selectivity to the nitride film is high at the contact corner when the oxide is etched, the nitride etching step is required after the oxide etching.
질화막 식각시에도 콘택 코너에서의 질화막의 식각속도가 콘택바닥에서 보다 빠르기 때문에 콘택코너의 질화막 손상으로 인해 배선간 단락에 취약해지는 문제점이 발생한다.Even when the nitride film is etched, the etching speed of the nitride film at the contact corner is faster than that at the bottom of the contact, so that the short circuit between wires is vulnerable due to the nitride film damage of the contact corner.
이러한 관점에서, 종래 기술에 따른 반도체소자의 콘택 형성시의 콘택코너에서의 질화막의 식각 메커니즘을 도 1 및 도 2 를 참조하여 상세히 설명하면 다음과 같다.In this regard, the etching mechanism of the nitride film in the contact corner during contact formation of the semiconductor device according to the prior art will be described in detail with reference to FIGS. 1 and 2 as follows.
도 1 및 도 2 는 종래기술에 따른 반도체소자의 콘택 형성시에 질화막측벽이 식각되는 것을 설명하기 위한 공정단면도이다.1 and 2 are process cross-sectional views for explaining the etching of the nitride film side wall when forming a contact of a semiconductor device according to the prior art.
먼저 도 1 에 도시된 바와같이, 실리콘기판(미도시)상에 형성된 워드라인(1)상부와 측면에 하드마스크용 산화막패턴(2)와 스페이서(3)가 형성되어 있고, 전체 구조의 상부에는 질화막(4)이 증착되어 있으며, 그위에는 BPSG 산화막(5)이 증착되어 패터닝공정에 의해 콘택홀(6)이 형성된다.First, as shown in FIG. 1, an oxide film pattern 2 and a spacer 3 for a hard mask are formed on an upper side and a side of a word line 1 formed on a silicon substrate (not shown). The nitride film 4 is deposited, and the BPSG oxide film 5 is deposited thereon, and the contact hole 6 is formed by a patterning process.
이상과 같은 콘택 형성에 있어서, 기존의 산화막 식각방법의 경우에, 질화막에 대하여 고선택비를 갖는 조건으로 식각할때 도 1 에 도시된 "A"부분과 같이 콘택코너 부위의 질화막이 많이 손상되기 때문에 질화막식각시 도 2 의 "B" 부분과 같이 코너 스페이서가 더욱 많이 식각되어 배선간의 단락 문제를 야기할수 있다.In the formation of the contacts as described above, in the case of the conventional oxide film etching method, the nitride film of the contact corner portion as shown in FIG. 1 is damaged when etching under conditions having a high selectivity with respect to the nitride film. Therefore, when the nitride film is etched, the corner spacers are more etched as in the portion “B” of FIG. 2, which may cause a short circuit problem between wires.
또한, 기존의 신화막 식각후 질화막 식각에 있어서, 질화막식각은 산화막식각후 연속하여 질화막을 식각하는 방법과 산화막 식각후 감광막 마스크를 제거한후 식각하는 방법이 있다.In addition, in the conventional etching of the nitride film after the etching of the nitride film, the nitride film etching method includes etching the nitride film continuously after the oxide film etching and etching after removing the photoresist mask after the oxide film etching.
통상 질화막 식각은 산화막에 대하여 2∼5 정도의 식각 선택비를 갖고 있으며, 이방성식각의 경우 콘택 바닥지역에 질화막 스페이서가 존재한다.In general, nitride etching has an etching selectivity of about 2 to 5 with respect to an oxide film, and in anisotropic etching, nitride spacers exist in a contact bottom region.
콘택코너부위의 질화막은 산화막 식각시 손상되어 콘택바닥 지역의 질화막보다 두께가 얇기 때문에 콘택을 열기 위해 콘택바닥지역의 질화막 두께를 기준으로 질화막을 식각할때 코너부위에서는 질화막의 식각량이 상당히 증가하여 산화막 스페이서의 손상을 발생시킨다.Since the nitride layer of the contact corner is damaged during the etching of the oxide layer and is thinner than the nitride layer of the contact bottom region, when the nitride layer is etched based on the thickness of the nitride layer of the contact bottom region to open the contact, the etching amount of the nitride layer is significantly increased at the corner region. It causes damage to the spacer.
이러한 산화막 스페이서의 손상은 배선간의 단락을 야기하므로 질화막식각시 이를 최대한으로 줄이는 것이 질화막장벽의 자기정렬콘택 구조에서는 필연적이라 할 수 있다.Since the damage of the oxide spacer causes a short circuit between the wirings, it is inevitable to reduce the maximum etching time of the nitride layer in the self-aligned contact structure of the nitride barrier.
이에, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 산화막을 식각하면서 별도의 추가공정없이 질화막 식각이 가능하므로써 공정을 단순화시킬 수 있는 반도체소자의 콘택 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, it is possible to provide a method for forming a contact of a semiconductor device that can simplify the process by etching the oxide film without additional process while etching the oxide film. There is this.
또한, 본 발명의 다른 목적은 콘택식각시에 질화막의 손상이 적어 배선간 단락 확률이 낮아지므로 소자수율을 증가시킬 수 있는 반도체소자의 콘택 형성방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for forming a contact of a semiconductor device which can increase the device yield since the damage of the nitride film during contact etching is reduced and the probability of short circuit between wirings is reduced.
그리고, 본 발명의 또다른 목적은 한번의 공정으로 산화막과 질화막을 식각하여 콘택홀 형성이 가능하여 별도의 추가 장비가 필요없어 제조비용을 절감시킬 수 있는 반도체소자의 콘택 형성방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for forming a contact of a semiconductor device capable of forming a contact hole by etching an oxide film and a nitride film in a single process, thereby eliminating the need for additional equipment.
상기 목적을 달성하기 위한 본 발명은, 실리콘기판상에 워드라인과 그 위에 하드마스크용 산화막패턴을 형성하는 공정과;The present invention for achieving the above object comprises the steps of: forming a word line and a hard mask oxide film pattern thereon on a silicon substrate;
상기 워드라인과 산화막패턴을 포함한 전체 구조의 상부에 질화막을 형성하는 공정과;Forming a nitride film over the entire structure including the word line and the oxide film pattern;
상기 질화막 상부에 BPSG막을 형성하고 그 위에 콘택마스크용 감광막패턴을 형성하는 공정과;Forming a BPSG film on the nitride film and forming a contact mask photoresist pattern thereon;
상기 감광막패턴을 마스크로 상기 BPSG막과 상기 질화막의 바닥부분을 동시에 제거하여 콘택홀을 형성하는 공정을 포함하여 구성되는 것을 제1 특징으로한다.And forming a contact hole by simultaneously removing the bottom portion of the BPSG film and the nitride film using the photoresist pattern as a mask.
또한, 본 발명에 따른 반도체소자의 콘택 형성방법은, 실리콘기판상에 워드라인과 하드마스크용 산화막패턴을 형성하는 공정과;In addition, the method for forming a contact of a semiconductor device according to the present invention comprises the steps of forming a word line and a hard mask oxide film pattern on a silicon substrate;
상기 워드라인과 실리콘리치산화막패턴의 측면에 산화막스페이서를 형성하는 공정과;Forming an oxide film spacer on side surfaces of the word line and the silicon rich oxide film pattern;
상기 산화막스페이서와 산화막패턴상부를 포함한 전체 구조의 상부에 질화막을 형성하는 공정과;Forming a nitride film over the entire structure including the oxide film spacer and the oxide film pattern upper portion;
상기 질화막상부에 BPSG막을 증착하고 평탄화시킨후 상기 BPSG막 상부에 콘택마스크용 감광막패턴을 형성하는 공정과;Depositing and planarizing a BPSG film on the nitride film and forming a contact mask photoresist pattern on the BPSG film;
상기 감광막패턴을 마스크로 상기 BPSG막과 질화막의 바닥부분을 동시에 제거하여 콘택홀을 형성하는 공정을 포함하여 구성되는 것을 특징으로한다.And forming a contact hole by simultaneously removing the bottom portion of the BPSG film and the nitride film using the photoresist pattern as a mask.
본 발명의 기술적 요지는, 자기 정렬 콘택 형성공정에서 산화막 식각시에 질화막에 대해 콘택 바닥에서 보다 콘택 코너에서 식각 선택비가 높은 조건을 갖는 C4F8/CH2F2/Ar 또는 C4F8/CH3F/Ar 등의 식각가스를 사용하여 산화막을 식각하면서 콘택코너의 질화막 손상이 없이 콘택 바닥의 질화막을 제거할 수 있다.The technical gist of the present invention provides an etching gas such as C4F8 / CH2F2 / Ar or C4F8 / CH3F / Ar having a high etching selectivity at the contact corner with respect to the nitride film during the oxide film etching in the self-aligned contact forming process. Can be used to etch the oxide layer and remove the nitride layer at the bottom of the contact without damaging the nitride layer of the contact corner.
도 1 및 도 2 는 종래 기술에 따른 반도체소자의 콘택 형성시에 질화막측벽부분이 식각되는 것을 설명하기 위한 공정단면도이다.1 and 2 are process cross-sectional views for explaining the etching of the nitride film side wall portion during contact formation of a semiconductor device according to the prior art.
도 3 내지 도 5 는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정을 설명하기 위한 단면도이다.3 to 5 are cross-sectional views illustrating a process for forming a contact of a semiconductor device according to a first embodiment of the present invention.
도 6 은 본 발명의 제2실시예에 따른 반도체소자의 콘택 형성을 설명하기 위한 단면도이다.6 is a cross-sectional view illustrating a contact formation of a semiconductor device in accordance with a second embodiment of the present invention.
도 7 은 본 발명의 제3실시예에 따른 반도체소자의 콘택 형성을 설명하기 위한 단면도이다.7 is a cross-sectional view illustrating a contact formation of a semiconductor device in accordance with a third embodiment of the present invention.
도 8 은 본 발명에 따른 반도체소자의 콘택형성방법에 있어서, 자기정렬방식을 이용한 콘택홀 형성에서 C4F8/CH2F2/Ar 가스를 사용하여 산화막 식각을 진행한 결과를 나타낸 도면이다.FIG. 8 is a view illustrating a result of etching an oxide layer using C 4 F 8 / CH 2 F 2 / Ar gas in forming a contact hole using a self-aligning method in the method for forming a contact of a semiconductor device according to the present invention.
도 9 는 본 발명에 따른 반도체소자의 콘택형성방법에 있어서의 식각 메커니즘을 설명하기 위한 단면도이다.9 is a cross-sectional view for describing an etching mechanism in the method for forming a contact of a semiconductor device according to the present invention.
도 10 은 본 발명에 따른 반도체소자의 콘택 형성방법에 있어서, 바이어스 전압을 크게 설정하여야 가능한 공정으로 재현성측면에서도 양호하게 나타나는 결과를 나타낸 도면이다.FIG. 10 is a view showing a good result in terms of reproducibility in a process in which a bias voltage must be set large in the method for forming a contact of a semiconductor device according to the present invention.
＜도면의주요부분에대한부호설명＞<Description of Signs of Main Parts of Drawings>
11 : 워드라인 12 : 산화막패턴11 word line 12 oxide film pattern
13 : 질화막 14 : BPSG막13 nitride film 14 BPSG film
15 : 제2감광막패턴 16 : 콘택홀15: second photosensitive film pattern 16: contact hole
이하, 본 발명에 따른 반도체소자의 콘택 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 5 는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정을 설명하기 위한 단면도이다.3 to 5 are cross-sectional views illustrating a process for forming a contact of a semiconductor device according to a first embodiment of the present invention.
도 6 은 본 발명의 제2실시예에 따른 반도체소자의 콘택 형성을 설명하기 위한 단면도이다.6 is a cross-sectional view illustrating a contact formation of a semiconductor device in accordance with a second embodiment of the present invention.
도 7 은 본 발명의 제3실시예에 따른 반도체소자의 콘택 형성을 설명하기 위한 단면도이다.7 is a cross-sectional view illustrating a contact formation of a semiconductor device in accordance with a third embodiment of the present invention.
도 8 은 본 발명에 따른 반도체소자의 콘택형성방법에 있어서, 자기정렬방식을 이용한 콘택홀 형성에서 C4F8/CH2F2/Ar 가스를 사용하여 산화막 식각을 진행한 결과를 나타낸 도면이다.FIG. 8 is a view illustrating a result of etching an oxide layer using C 4 F 8 / CH 2 F 2 / Ar gas in forming a contact hole using a self-aligning method in the method for forming a contact of a semiconductor device according to the present invention.
도 9 는 본 발명에 따른 반도체소자의 콘택형성방법에 있어서의 식각 메카니즘을 설명하기 위한 단면도이다.9 is a cross-sectional view illustrating an etching mechanism in the method for forming a contact of a semiconductor device according to the present invention.
도 10 은 본 발명에 따른 반도체소자의 콘택 형성방법에 있어서, 바이어스 전압을 크게 설정하여야 가능한 공정으로 재현성측면에서도 양호하게 나타나는 결과를 나타낸 도면이다.FIG. 10 is a view showing a good result in terms of reproducibility in a process in which a bias voltage must be set large in the method for forming a contact of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 콘택 형성방법은, 먼저 도 3 에 도시된 바와같이, 실리콘기판(미도시)상에 워드라인용 폴리실리콘층과 하드마스크용 산화막을 순차적으로 증착하고 그위에 워드라인마스크용 감광막패턴(미도시)을 형성한다.In the method for forming a contact of a semiconductor device according to the present invention, as shown in FIG. 3, a polysilicon layer for a word line and an oxide film for a hard mask are sequentially deposited on a silicon substrate (not shown), and a word line mask is formed thereon. A photosensitive film pattern (not shown) is formed.
그다음, 상기 제1감광막패턴(미도시)을 마스크로 상기 산화막과 폴리실리콘층을 노광 및 현상공정을 진행한후 이를 선택적으로 패터닝하여 워드라인(11)과 하드마스크용 산화막패턴(12)을 형성한다.Next, the oxide film and the polysilicon layer are exposed and developed using the first photoresist pattern (not shown) as a mask, and then selectively patterned to form a word line 11 and an oxide film pattern 12 for a hard mask. do.
이어서, 상기 제1감광막패턴(미도시)을 제거하고, 도 4 에 도시된 바와같이, 상기 상기 워드라인(11)과 산화막패턴(12)을 포함한 전체 구조의 상부에 산화막 식각시의 식각장벽으로 사용하기 위해 질화막(13)을 형성한다.Subsequently, the first photoresist layer pattern (not shown) is removed, and as shown in FIG. 4, an etch barrier for etching the oxide layer is formed on the entire structure including the word line 11 and the oxide layer pattern 12. The nitride film 13 is formed for use.
그다음, 도 4 에 도시된 바와같이, 전체 구조의 상부에 BPSG막(14)을 형성하여 평탄화공정을 진행하고, 그 위에 콘택홀마스크용 제2감광막패턴(15)을 형성한다.Then, as shown in FIG. 4, the BPSG film 14 is formed on the entire structure to perform the planarization process, and the second photoresist film pattern 15 for the contact hole mask is formed thereon.
이어서, 도 5 에 도시된 바와같이, 상기 제2감광막패턴(15)을 마스크로 상기 BPSG막(14)을 패터닝하여 콘택홀(16)을 형성한다.Subsequently, as shown in FIG. 5, the BPSG film 14 is patterned using the second photoresist film pattern 15 to form a contact hole 16.
이때, 식각가스로는 C4F8/CH2F2 또는 C4F8/CH3F/Ar 등의 가스를 사용하여 식각공정을 진행한다.At this time, as an etching gas, an etching process is performed using gas such as C4F8 / CH2F2 or C4F8 / CH3F / Ar.
또한, 상기 질화막 식각시에 식각선택비가 콘택홀 코너에서는 높고 콘택홀바닥에서는 낙게 하기위해 CH2F2, CH3F, CHF3, H2, C2H2 등의 수소를 포함하는 가스중 하나를 사용한다.In addition, the etching selectivity during the etching of the nitride film is high at the contact hole corner and one of hydrogen-containing gases such as CH 2 F 2, CH 3 F, CHF 3, H 2, and C 2 H 2 is used to drop it at the bottom of the contact hole.
그리고, 상기 BPSG산화막 식각시에 질화막에 대해 고선택비를 확보하기 위해 필요한 폴리머를 용이하게 생성하는 C5F, C4F8, C3F8, C2F6 등 가스를 이용하여 식각공정을 진행한다.In addition, the etching process is performed using gases such as C5F, C4F8, C3F8, and C2F6, which easily generate a polymer necessary to secure a high selectivity for the nitride film during the BPSG oxide film etching.
또한, 상기 BPSG막 식각시에 Ar, Ne, He, Xe 등의 불활성 가스를 첨가하여 사용한다.In addition, an inert gas such as Ar, Ne, He, Xe, or the like is added to the BPSG film during etching.
그리고, 상기 콘택홀(16) 형성시에, 상기 질화막(13)에 대하여 콘택(16) 코너에서 고선택비를 확보하여 배선간 단락을 방지하면서 콘택(16) 바닥의 질화막(13)을 식각하여 콘택홀(16)을 열어 실리콘기판(미도시)을 노출시킨후, 콘택홀 마스크로 사용한 제2감광막패턴(15)을 제거한다.When the contact hole 16 is formed, the nitride film 13 at the bottom of the contact 16 is etched while ensuring a high selectivity with respect to the nitride film 13 at the corner of the contact 16 to prevent a short circuit between wires. After opening the contact hole 16 to expose a silicon substrate (not shown), the second photoresist pattern 15 used as the contact hole mask is removed.
이때, 상기 질화막(13)은 콘택홀(16)내에서 스페이서로 형성되어 워드라인을 절연시켜 준다.In this case, the nitride layer 13 is formed as a spacer in the contact hole 16 to insulate the word line.
또한, 본 발명의 제2실시예는, 도 6 에 도시된 바와같이, 실리콘기판(미도시)상에 워드라인용 폴리실리콘층과 하드마스크용 제1산화막을 순차적으로 증착하고 그위에 워드라인마스크용 감광막패턴(미도시)을 형성한다.In addition, according to the second embodiment of the present invention, as shown in FIG. 6, a polysilicon layer for a word line and a first oxide layer for a hard mask are sequentially deposited on a silicon substrate (not shown), and a word line mask is disposed thereon. A photosensitive film pattern (not shown) is formed.
그다음, 상기 제1감광막패턴(미도시)을 마스크로 상기 제1산화막과 폴리실리콘층을 노광 및 현상공정을 진행한후 이를 선택적으로 패터닝하여 워드라인(21)과 하드마스크용 제1산화막패턴(22)을 형성한다.Subsequently, the first oxide film and the polysilicon layer are exposed and developed using the first photoresist pattern (not shown) as a mask, and then selectively patterned to form a word line 21 and a first oxide film pattern for a hard mask. 22).
그다음, 상기 제1감광막패턴(미도시)을 제거하고, 상기 전체 구조의 상부에 제2산화막을 증착하고 이를 이방성식각공정을 통해 선택적으로 제거하여 상기 워드라인(21)과 하드마스크용 산화막패턴(22)의 측면에 제2산화막스페이서(23)을 형성한다.Next, the first photoresist layer pattern (not shown) is removed, and a second oxide layer is deposited on the entire structure, and then selectively removed through the anisotropic etching process to form the word line 21 and the oxide layer pattern for the hard mask ( A second oxide film spacer 23 is formed on the side surface of 22).
이어서, 상기 제2산화막스페이서(23)과 제1산화막패턴(22)의 상부면을 포함한 전체 구조의 상부에 산화막 식각시의 식각장벽으로 사용하기 위해 질화막(24)을 증착한다.Subsequently, a nitride layer 24 is deposited on the top of the entire structure including the second oxide layer spacer 23 and the upper surface of the first oxide layer pattern 22 as an etch barrier for etching the oxide layer.
그다음, 상기 질화막(24) 상부에 BPSG산화막(25)을 증착하여 평탄화공정을 진행한후 그위에 콘택홀마스크용 제2감광막패턴(미도시)을 형성한다.Next, a BPSG oxide layer 25 is deposited on the nitride layer 24 to perform a planarization process, and then a second photoresist layer pattern (not shown) for a contact hole mask is formed thereon.
이어서, 상기 제2감광막패턴(미도시)을 마스크로 상기 BPSG막(25)을 패터닝하여 콘택홀(26)을 형성한다.Subsequently, the BPSG layer 25 is patterned using the second photoresist layer pattern (not shown) to form a contact hole 26.
이때, 식각가스로는 실시예 1 에서 사용한 C4F8/CH2F2 또는 C4F8 / CH3F / Ar 등의 가스를 사용하여 식각공정을 진행한다.At this time, as an etching gas, an etching process is performed using gas such as C4F8 / CH2F2 or C4F8 / CH3F / Ar used in Example 1.
또한, 콘택홀(26) 형성시에, 상기 질화막(24)에 대하여 콘택(26) 코너에서 고선택비를 확보하여 배선간 단락을 방지하면서 콘택(26) 바닥의 질화막(24)을 식각하여 콘택홀(26)을 열어 실리콘기판(미도시)을 노출시킨다,In addition, when the contact hole 26 is formed, the nitride film 24 at the bottom of the contact 26 is etched while securing a high selectivity with respect to the nitride film 24 at the corner of the contact 26 to prevent a short circuit between wires. Open the hole 26 to expose a silicon substrate (not shown),
그다음, 콘택홀 마스크로 사용한 제2감광막패턴(미도시)을 제거한다. 이때, 상기 질화막(24)은 워드라인을 절연시켜 준다.Next, the second photosensitive film pattern (not shown) used as the contact hole mask is removed. In this case, the nitride film 24 insulates the word line.
그리고, 본 발명의 제3실시예에 따른 반도체소자의 콘택 형성방법은, 도 7 에 도시된 바와같이, 실리콘기판(미도시)상에 워드라인용 폴리실리콘층과 하드마스크용 제1산화막을 순차적으로 증착하고 그위에 워드라인마스크용 감광막패턴(미도시)을 형성한다.In the method for forming a contact of a semiconductor device according to the third embodiment of the present invention, as shown in FIG. 7, a polysilicon layer for a word line and a first oxide film for a hard mask are sequentially formed on a silicon substrate (not shown). And a photoresist pattern (not shown) for a word line mask is formed thereon.
그다음, 상기 제1감광막패턴(미도시)을 마스크로 상기 제1질화막과 폴리실리콘층을 노광 및 현상공정을 진행한후 이를 선택적으로 패터닝하여 워드라인(31)과 하드마스크용 제1질화막패턴(32)을 형성한다.Subsequently, the first nitride film and the polysilicon layer are exposed and developed using the first photoresist pattern (not shown) as a mask, and then selectively patterned to form a word line 31 and a first nitride film pattern for a hard mask. 32).
그다음, 상기 제1감광막패턴(미도시)을 제거하고, 상기 전체 구조의 상부에 제2질화막을 증착하고 이를 이방성식각공정을 통해 선택적으로 제거하여 상기 워드라인(31)과 하드마스크용 제1질화막패턴(32)의 측면에 제2질화막스페이서(33)을 형성한다.Next, the first photoresist layer pattern (not shown) is removed, and a second nitride layer is deposited on the entire structure, and then selectively removed through the anisotropic etching process to form the first nitride layer for the word line 31 and the hard mask. A second nitride film spacer 33 is formed on the side surface of the pattern 32.
이어서, 상기 제2질화막스페이서(33)과 제1질화막패턴(32)의 상부면을 포함한 전체 구조의 상부에 산화막 식각시의 식각장벽으로 사용하기 위해 제3질화막(34)을 증착한다.Subsequently, a third nitride layer 34 is deposited on the upper portion of the entire structure including the second nitride layer spacer 33 and the upper surface of the first nitride layer pattern 32 to serve as an etch barrier for etching the oxide layer.
그다음, 상기 제3질화막(34) 상부에 BPSG산화막(25)을 증착하여 평탄화공정을 진행한후 그위에 콘택홀마스크용 제2감광막패턴(미도시)을 형성한다.Next, a BPSG oxide layer 25 is deposited on the third nitride layer 34 to perform a planarization process, and then a second photoresist layer pattern (not shown) for a contact hole mask is formed thereon.
이어서, 상기 제2감광막패턴(미도시)을 마스크로 상기 BPSG막(35)을 패터닝하여 콘택홀(36)을 형성한다.Subsequently, the BPSG layer 35 is patterned using the second photoresist layer pattern (not shown) to form a contact hole 36.
이때, 식각가스로는 실시예1 에서 사용한 C4F8/CH2F2 또는 C4F8/CH3F/Ar 등의 가스를 사용하여 식각공정을 진행한다.At this time, as an etching gas, an etching process is performed using gas such as C4F8 / CH2F2 or C4F8 / CH3F / Ar used in Example 1.
또한, 콘택홀(36) 형성시에, 상기 제3질화막(34)에 대하여 콘택(36) 코너에서 고선택비를 확보하여 배선간 단락을 방지하면서 콘택(36) 바닥의 제3질화막(34)을 식각하여 콘택홀(36)을 열어 실리콘기판(미도시)을 노출시킨다.In addition, when forming the contact hole 36, the third nitride film 34 at the bottom of the contact 36 is prevented while ensuring a high selectivity with respect to the third nitride film 34 at the corner of the contact 36 to prevent a short circuit between wirings. Etching to open the contact hole 36 to expose a silicon substrate (not shown).
그다음, 콘택홀 마스크로 사용한 제2감광막패턴(미도시)을 제거한다. 이때, 상기 제3질화막(34)은 워드라인을 절연시켜 준다.Next, the second photosensitive film pattern (not shown) used as the contact hole mask is removed. In this case, the third nitride film 34 insulates the word line.
한편, 도 8 은 본 발명에 따른 반도체소자의 콘택형성방법에 있어서, 자기정렬방식을 이용한 콘택홀 형성에서 C4F8/CH2F2/Ar 가스를 사용하여 산화막 식각을 진행한 결과를 나타낸 도면이다.FIG. 8 is a view illustrating a result of etching an oxide layer using C4F8 / CH2F2 / Ar gas in forming a contact hole using a self-aligning method in the method for forming a contact of a semiconductor device according to the present invention.
도 8 에서 알 수 있는 바와같이, C4F8/CH2F2/Ar 가스를 사용하여 질화막에 대한 식각선택비가 콘택 코너에서는 높고 콘택코너에서는 낮게 하여 산화막 식각을 실시한 결과 콘택코너에서는 질화막에 대해 고식각선택비가 확보되어 질화막 손상이 미미한 반면에, 콘택바닥의 질화막은 식각되어 콘택이 열리는 것을 알수 있다.As can be seen in Figure 8, using the C4F8 / CH2F2 / Ar gas etch selectivity for the nitride film is high in the contact corner and low in the contact corner as a result of the oxide etching to ensure a high etching selectivity for the nitride film in the contact corner While the damage of the nitride film is minimal, it can be seen that the nitride film of the contact bottom is etched to open the contact.
한편, 본 발명의 콘택 형성방법에 따른 식각 메커니즘을 도 9 을 참조하여 구체적으로 설명하면 다음과 같다.Meanwhile, the etching mechanism according to the contact forming method of the present invention will be described in detail with reference to FIG. 9.
본 발명은 질화막장벽 자기정렬(NBSAC ; Nitride Barrier Self-Aligned Contact) 구조 또는 질화막장벽스페이서(NBSSAC ; Nitride Barrier Spacer Self-Aligned Contact) 구조에서 산화막 식각시 워드라인 코너부위의 질화막에 대해서는 높은 선택비를 갖고 콘택 바닥 지역의 질화막에 대해서는 선택비가 낮아 질화막이 식각되므로써 콘택이 형성한다.The present invention provides a high selectivity for the nitride film at the corner of the word line when the oxide is etched in the Nitride Barrier Self-Aligned Contact (NBSAC) structure or the Nitride Barrier Spacer Self-Aligned Contact (NBSSAC) structure. For the nitride film in the contact bottom region, the selectivity is low and the contact is formed by etching the nitride film.
따라서, 본 발명을 적용하는 경우에, 콘택코너 지역의 질화막 손상이 적어 배선간의 단락을 방지할 수 있으며, 산화막 식각공정만으로 바닥지역의 질화막까지 식각을 행할 수 있으므로 종래의 산화막식각후 별도로 질화막을 식각하는 공정을 단순화하여 산화막 식각 공정만으로도 콘택을 형성할 수 있다.Therefore, in the case of applying the present invention, since the damage of the nitride film in the contact corner area is small, it is possible to prevent a short circuit between the wirings and the etching of the nitride film separately after the conventional oxide film etching since the etching can be performed to the nitride film of the bottom region only by the oxide film etching process. The process may be simplified to form a contact using only an oxide film etching process.
즉, 도 9 와 같이 자기정렬구조를 갖는 콘택 형성시에 BPSG산화막(45)을 식각한다.That is, the BPSG oxide film 45 is etched at the time of forming a contact having a self-aligned structure as shown in FIG. 9.
이때 산화막이 식각되는 동안 콘택코너지역의 질화막(44)이 콘택에 노출되면 폴리머(47)가 질화막위에 증착되어 질화막이 손상되는 것을 방지한다.At this time, if the nitride film 44 in the contact corner region is exposed to the contact while the oxide film is etched, the polymer 47 is deposited on the nitride film to prevent the nitride film from being damaged.
한편, 식각이 계속 진행되어, 콘택바닥지역에 도달하면 이온의 산란으로 인한 콘택바닥지역으로의 집중현상으로 인하여 콘택바닥지역의 질화막이 H 또는 F 와 반응하므로써 질화막을 식각해 낸다.On the other hand, when the etching continues and reaches the contact bottom region, the nitride layer in the contact bottom region reacts with H or F due to the concentration phenomenon in the contact bottom region due to the scattering of ions, thereby etching the nitride film.
이렇게 산화막 식각시 콘택코너지역의 질화막이 노출되면 식화막 식각시 발생되는 폴리머(47)가 증착되어 질화막 손상을 방지한다. 산화막 식각이 계속해서 진행되어 콘택바닥지역의 질화막이 노출되어도 폴리머는 증착되지만 이온들이 산란으로 콘택바닥지역에서 집중되고, 수소 역시 콘택바닥지역에서 집중된다.When the nitride film in the contact corner region is exposed during the etching of the oxide layer, the polymer 47 generated during the etching layer is deposited to prevent the nitride layer from being damaged. Although the etching of the oxide continues and the nitride film in the contact bottom region is exposed, the polymer is deposited, but ions are concentrated in the contact bottom region by scattering, and hydrogen is also concentrated in the contact bottom region.
이때, 이온은 에너지를 제공하고 수소는 질화막을 식각하는데 사용된다. 물론, 콘택 코너부위에서도 이온과 수소가 도달하지만 콘택코너지역에서의 이온과 수소의 양은 적기때문에 폴리머를 제거하지 못하여 질화막 손상이 야기되지 않는다.At this time, ions provide energy and hydrogen is used to etch the nitride film. Of course, ions and hydrogen arrive at the contact corners, but the amount of ions and hydrogen in the contact corner region is small, so that the polymer cannot be removed and nitride film damage is not caused.
반면에 콘택바닥지역에서는 양이 커서 폴리머 제거가 가능하므로 질화막이 식각된다. 이는 반드시 수소가 존재하여야 하고 역전압을 크게 설정하여야 가능한 공정으로 재현성 측면에서도 도 10 과 같은 양호한 결과를 보인다.On the other hand, the nitride layer is etched because the amount of polymer can be removed in the contact area. This is a process that must be present in the hydrogen and the reverse voltage is set large, and shows good results as shown in Figure 10 in terms of reproducibility.
상기한 바와같이, 본 발명에 따른 반도체소자의 콘택 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the contact forming method of the semiconductor device according to the present invention has the following effects.
반도체 소자의 콘택 형성에 있어서, 종래의 자기정렬기술로 콘택홀을 형성하기 위해서는 산화막 식각후 별도로 질화막 식각을 진행해야 하지만, 본 발명에 있어서는 산화막 식각하면서 별도의 추가공정없이 질화막을 식각하므로써 공정을 단순화시킬 수 있다.In forming a contact hole in a semiconductor device, in order to form a contact hole using a conventional self-aligning technique, nitride etching must be performed separately after etching the oxide. However, in the present invention, the nitride film is etched without any additional process while etching the oxide, thereby simplifying the process. You can.
또한, 질화막의 식각에 있어서, 종래의 기술은 콘택코너에서 식각선택비가 콘택바닥보다 낮아 콘택코너에서 질화막의 손상으로 배선간 단락에 취약한데 반하여, 본 발명에서는 콘택코너에서의 식각선택비가 콘택바닥보다 높으므로 식각시 콘택코너에서 질화막의 손상이 적어 배선간 단락 확률이 낮아진다.Further, in etching the nitride film, the conventional technique has a lower etching selectivity at the contact corner than the contact bottom, so that the etching selectivity at the contact corner is more vulnerable to short circuit between wirings due to damage of the nitride film at the contact corner. As a result, the damage of the nitride film in the contact corner during etching is small, and the probability of short circuit between wirings is lowered.
따라서, 배선간 단락확률이 낮아지므로써 반도체제조에 있어서의 소자수율을 증가시킬 수 있다.Therefore, the probability of short circuit between wirings is lowered, so that the yield of devices in semiconductor manufacturing can be increased.
그리고, 본 발명에 있어서는, 한번의 공정으로 산화막과 질화막을 식각하여 콘택홀을 형성하므로 인해 질화막을 식각하기 위한 별도의 장비가 필요없게 된다.In the present invention, since the contact hole is formed by etching the oxide film and the nitride film in one process, no additional equipment for etching the nitride film is required.
Claims (9)
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| KR1019980062000A KR20000045442A (en) | 1998-12-30 | 1998-12-30 | Fabrication method of contacts for semiconductor device |
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| KR1019980062000A KR20000045442A (en) | 1998-12-30 | 1998-12-30 | Fabrication method of contacts for semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040041252A (en) * | 2002-11-09 | 2004-05-17 | 삼성전자주식회사 | Magnetic enhanced reactive ion etching process for manufacturing method of semiconductor device |
| KR100440776B1 (en) * | 2001-12-17 | 2004-07-21 | 주식회사 하이닉스반도체 | A fabricating method of semiconductor device using ArF photolithography |
| US6867145B2 (en) | 2001-12-17 | 2005-03-15 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser |
| KR100725713B1 (en) * | 2006-08-28 | 2007-06-07 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal line of semiconductor device |
| KR100910865B1 (en) * | 2002-12-26 | 2009-08-06 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
-
1998
- 1998-12-30 KR KR1019980062000A patent/KR20000045442A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100440776B1 (en) * | 2001-12-17 | 2004-07-21 | 주식회사 하이닉스반도체 | A fabricating method of semiconductor device using ArF photolithography |
| US6867145B2 (en) | 2001-12-17 | 2005-03-15 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser |
| KR20040041252A (en) * | 2002-11-09 | 2004-05-17 | 삼성전자주식회사 | Magnetic enhanced reactive ion etching process for manufacturing method of semiconductor device |
| KR100910865B1 (en) * | 2002-12-26 | 2009-08-06 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
| KR100725713B1 (en) * | 2006-08-28 | 2007-06-07 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal line of semiconductor device |
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