KR20000025686A - Method for forming contact hole of semiconductor devices - Google Patents
Method for forming contact hole of semiconductor devices Download PDFInfo
- Publication number
- KR20000025686A KR20000025686A KR1019980042849A KR19980042849A KR20000025686A KR 20000025686 A KR20000025686 A KR 20000025686A KR 1019980042849 A KR1019980042849 A KR 1019980042849A KR 19980042849 A KR19980042849 A KR 19980042849A KR 20000025686 A KR20000025686 A KR 20000025686A
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- etching
- forming
- film
- interlayer insulating
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 38
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000011065 in-situ storage Methods 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 20
- 229920000642 polymer Polymers 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- -1 O 2 Chemical compound 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 5
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- VKWMGUNWDFIWNW-UHFFFAOYSA-N 2-chloro-1,1-dioxo-1,2-benzothiazol-3-one Chemical compound C1=CC=C2S(=O)(=O)N(Cl)C(=O)C2=C1 VKWMGUNWDFIWNW-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 질화막을 산화막 식각시의 식각장벽으로 하고, 산화막 식각후 웨이퍼 전면에 증착된 질화막을 식각하여 콘택홀을 오픈시키고, 동시에 질화막 스페이서를 형성함에 의해 서로 다른 배선간 절연막으로 사용함으로써 콘택홀 제조공정을 단순화 및 소자의 동작특성을 향상시킬 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, using a nitride film as an etch barrier for etching an oxide film, opening a contact hole by etching a nitride film deposited on the entire surface of the wafer after etching the oxide film, and simultaneously forming a nitride film spacer. Therefore, the present invention relates to a method for forming a contact hole in a semiconductor device which can simplify contact hole manufacturing processes and improve device operation characteristics by using the insulating film as a wiring interlayer.
일반적으로 셀프 얼라인 콘택(Self-Aligned Contact ; 이하 'SAC' 라 함) 기술을 요구하는 0.30㎛ 이하의 콘택홀을 형성하기 위한 종래의 대표적인 기술로는 아래의 두가지가 있다.In general, there are two conventional techniques for forming a contact hole of 0.30 μm or less that requires a self-aligned contact (hereinafter, referred to as “SAC”) technology.
즉 도 1a 에 도시된 바와 같은 질화장벽 SAC(Nitride barrier SAC ; 이하 'NBSAC' 라 함)의 구조와 도 1b 에 도시된 질화 캐핑 SAC(Nitride Capping SAC ; 이하 'NCSAC' 라 함)의 구조가 있다.That is, there is a structure of a nitride barrier SAC (hereinafter referred to as 'NBSAC') as shown in FIG. 1A and a nitride capping SAC (hereinafter referred to as 'NCSAC') shown in FIG. 1B. .
상기 도 1a 에 도시된 NBSAC의 경우 다음과 같은 몇가지 문제점을 안고 있다.In the case of the NBSAC illustrated in FIG. 1A, there are some problems as follows.
첫째, 산화막(11) 식각시의 식각 장벽막으로 사용되는 질화막(9)의 두께를 두껍게 사용하면 워드라인(3) 사이가 좁아져 산화막(11) 식각공정이 어려우므로 질화막(9)의 두께를 가능한 얇게 사용하는데, 이 경우 질화막(9)에 대한 매우 높은 식각 선택비가 요구되어 매우 어려운 공정이 되는 문제점이 있다.First, when the thickness of the nitride film 9 used as an etch barrier layer during the etching of the oxide film 11 is used thicker, the thickness of the nitride film 9 may be reduced due to the narrowing between the word lines 3 and the etching process of the oxide film 11. To use as thin as possible, in this case there is a problem that a very high etching selectivity for the nitride film 9 is required, which is a very difficult process.
둘째로, 충분한 콘택홀 면적확보를 위해 등방성 질화막 식각이 요구되는데, 이 경우 추가의 등방성 식각 장비가 필요하고, 콘택홀 중 Si-기판(1)과 워드라인 폴리(3)가 주변회로지역에 동시에 드러나는 경우, 등방성 질화막 특성상 식각비가 Si-기판(1), 워드라인 폴리(3) > 질화막(9) > 산화막(5,7) 의 순서이기 때문에 Si-기판(1)과 워드라인 폴리(3)가 손상방지를 위해 주변회로 지역을 가리기 위한 추가의 감광막 마스크 공정이 필요하다.Secondly, isotropic nitride etching is required to secure sufficient contact hole area, in which case additional isotropic etching equipment is required, and Si-substrate (1) and wordline poly (3) of contact holes are simultaneously applied to the surrounding circuit area. If exposed, the Si-substrate (1) and the wordline poly (3) are etched because the etch ratio is in the order of Si-substrate (1), wordline poly (3)> nitride film (9)> oxide films (5,7). To prevent damage, an additional photoresist mask process is needed to cover the surrounding circuit area.
셋째로, 디자인 룰이 작아질 경우, 기본적으로 산화막 스페이서가 사용되어 질화막을 두껍게 사용하지 못하기 때문에 어느 한계이상 사용이 어렵다.Third, when the design rule is small, it is difficult to use more than a certain limit because the oxide spacer is basically used so that the nitride film cannot be used thickly.
다음, 상기 도 1b 에 도시된 NBSAC의 경우, 워드라인(3) 위의 절연막(6)을 질화막으로 사용하여야 하기 때문에 워드라인(3)에 대한 질화막(6)의 스트레스가 커 트랜지스터의 특성악화를 피할 수 없는 문제점이 있다.Next, in the case of the NBSAC shown in FIG. 1B, since the insulating film 6 on the word line 3 must be used as the nitride film, the stress of the nitride film 6 against the word line 3 is increased, thereby deteriorating the characteristics of the transistor. There is an unavoidable problem.
따라서 본 발명은 상기한 종래기술의 문제점을 해결하기 위한 것으로, 본 발명은 질화막을 산화막 식각시의 식각 장벽막으로 사용하는 SAC 공정으로서, 산화막 식각 후 웨이퍼에 전면 증착된 질화막을 식각하여 콘택홀을 오픈시키고, 동시에 스페이서를 형성하여 서로 다른 배선간 절연막으로 사용함으로써 공정의 단순화와 전기적 단락을 방지하여 소자의 동작특성을 향상시킬 수 있는 반도체 소자의 콘택홀 형성방법을 제공하에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems of the prior art, the present invention is a SAC process using a nitride film as an etch barrier film during the oxide film etching, etching the entire surface deposited on the wafer after etching the oxide film to contact holes It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device which can open and simultaneously form a spacer and use it as an insulating film between different wirings, thereby simplifying a process and preventing an electrical short, thereby improving the operation characteristics of the device.
도 1a 와 도 1b 는 종래 기술에 따라 콘택홀이 형성된 반도체 소자의 구조를 도시한 도면1A and 1B illustrate a structure of a semiconductor device in which contact holes are formed according to the related art.
도 2a 내지 도 2d 는 본 발명의 방법에 따른 반도체 소자의 콘택홀 형성 공정단계를 도시한 단면도2A through 2D are cross-sectional views illustrating a process of forming a contact hole in a semiconductor device according to the method of the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
1, 21 : 반도체 기판 3,23 : 워드라인1, 21: semiconductor substrate 3, 23: word line
5,7,25 : 절연 산화막 9,27 : 절연 질화막5,7,25 Insulation oxide film 9,27 Insulation nitride film
11,29 : 평탄화 절연막 13,33 : 콘택홀11,29 planarization insulating film 13,33 contact hole
31 : 감광막 마스크31: photosensitive film mask
상기 목적을 달성하기 위한 본 발명은,The present invention for achieving the above object,
반도체 기판 상부에 폴리실리콘을 증착하는 단계와,Depositing polysilicon on the semiconductor substrate;
상기 폴리실리콘 상부에 절연 산화막을 형성하는 단계와,Forming an insulating oxide film on the polysilicon;
워드라인 마스크를 이용하여 상기 절연 산화막과 폴리실리콘을 식각하여 패터닝하는 단계와,Etching and patterning the insulating oxide layer and the polysilicon using a word line mask;
전체 구조 상부에 산화막 식각 장벽막으로 사용되는 질화막과 층간 절연막을 차례로 증착하는 단계와,Depositing a nitride film and an interlayer insulating film which are used as an oxide etching barrier film on the entire structure in order;
상기 층간 절연막 상부에 감광막으로 콘택홀 마스크를 형성하는 단계와,Forming a contact hole mask on the interlayer insulating layer with a photoresist;
상기 콘택홀 마스크를 이용하여 하부 층간 절연막을 식각하되, 인스튜 공정으로 상기 질화막을 식각하여 콘택홀을 오픈하는 단계와,Etching the lower interlayer insulating layer using the contact hole mask, and opening the contact hole by etching the nitride layer by an in-situ process;
상부의 감광막 마스크를 제거하는 단계를 포함한 구성으로 되는 것을 특징으로 한다.Characterized in that the configuration including the step of removing the upper photosensitive film mask.
이하 첨부된 도면을 참조하여 본 발명에 대한 상세한 설명을 하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명의 방법에 따른 반도체 소자의 콘택홀 형성 공정단계를 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a process of forming a contact hole in a semiconductor device according to the method of the present invention.
도 2a를 참조하면, 반도체 기판(21) 상부에 폴리실리콘(23)을 증착하고, 상기 폴리실리콘(23) 상부에 절연막으로 사용될 산화막(25)을 증착한다.Referring to FIG. 2A, the polysilicon 23 is deposited on the semiconductor substrate 21, and the oxide film 25 to be used as an insulating film is deposited on the polysilicon 23.
다음, 워드라인 마스크(미도시)를 감광막으로 형성하고, 상기 워드라인 마스크를 이용하여 하부 산화막(25)과 폴리실리콘(23)을 식각한 후, 감광막 마스크를 제거한다.Next, a word line mask (not shown) is formed of a photoresist film, and the lower oxide layer 25 and the polysilicon 23 are etched using the word line mask, and then the photoresist mask is removed.
도 2b를 참조하면, 전체 구조 상부에 산화막 식각 장벽막으로 사용되는 질화막(27)과, 층간 절연막(29)을 증착한다. 이때 상기 층간 절연막(29)으로는 비.피.에스.지(Boro Phospho Siligate Glass ; 이하 'BPSG' 라 함) 산화막을 사용한다.Referring to FIG. 2B, a nitride film 27 and an interlayer insulating film 29 used as an oxide etch barrier film are deposited on the entire structure. In this case, the interlayer insulating layer 29 is a B. P. S. (Boro Phospho Siligate Glass; referred to as "BPSG") oxide film.
다음 감광막으로 콘택홀 마스크(31)를 형성한다.Next, the contact hole mask 31 is formed of a photosensitive film.
도 2c를 참조하면, 상기 콘택홀 마스크(31)를 이용하여 하부 층간 절연막(29)을 식각한다. 이때 상기 층간 절연막인 BPSG 산화막(29) 식각시 질화막(27)에 대하여 어느정도, 예컨데 워드라인(23)과 다른 배선간의 단락방지를 위한 최소두께를 확보하는 정도의 조건을 사용한다.Referring to FIG. 2C, the lower interlayer insulating layer 29 is etched using the contact hole mask 31. At this time, the etching conditions of the BPSG oxide layer 29, which is the interlayer insulating layer, are used to the extent that the thickness of the nitride layer 27 is secured to some extent, for example, a minimum thickness for preventing a short circuit between the word line 23 and another wiring.
상기 층간 절연막(29) 식각공정에 사용되는 식각 가스로는 C4F8/C3F8, C2F6, C2F4, C2HF5등의 주가스를 사용하고, 이들 가스에 CH3F, C2H2, CH2F2등의 H 함유 가스와 Ar, He, Xe, Ne등의 가스를 첨가한다.Main gases such as C 4 F 8 / C 3 F 8 , C 2 F 6 , C 2 F 4 , C 2 HF 5, and the like may be used as the etching gas used in the interlayer insulating layer 29. 3 F, C 2 H 2, and the gas is added, such as CH 2 F 2, etc. of the H-containing gas with Ar, He, Xe, Ne.
한편, 상기 층간 절연막(29) 식각공정 후 폴리머 제거 공정을 실시하는데, 상기 폴리머 제거 공정시 사용되는 식각가스로는 O2, CO2, CO 와 같은 산소를 포함하는 가스를 사용한다. 또한 상기 폴리머 제거시 사용되는 가스에 N2를 첨가하여 폴리머 제거효율을 높일 수 있다.Meanwhile, a polymer removal process is performed after the interlayer insulating layer 29 is etched. As an etching gas used in the polymer removal process, a gas containing oxygen such as O 2 , CO 2 , and CO is used. In addition, N 2 may be added to the gas used to remove the polymer to increase the polymer removal efficiency.
도 2d를 참조하면, 인스튜(In-Situ) 공정으로 질화막(27)을 식각하여 콘택홀(33)을 오픈한다. 이때 상기 질화막(27) 식각시 산화막(29)에 대하여 고선택비를 갖고, 또한 산화막 스페이서가 양호하게 형성되도록 한다.Referring to FIG. 2D, the contact hole 33 is opened by etching the nitride layer 27 by an in-situ process. In this case, the nitride film 27 may have a high selectivity with respect to the oxide film 29 and the oxide spacers may be satisfactorily formed.
질화막 식각 가스로는 CH3F, CHF3, CF4, C2F6, NF3등 플루오린(Fluorine)을 함유한 가스를 사용하고, 이들 가스에 CO, CO2, O2 등과 Ar, Xe, He, Ne 등의 가스를 첨가하여 Si-기판(1)이나 워드라인 폴리(23)의 손상을 최소화 한다.As the nitride etching gas, gases containing fluorine such as CH 3 F, CHF 3 , CF 4 , C 2 F 6 , and NF 3 are used, and these gases include CO, CO 2, O 2, and the like. The addition of a gas such as Ne minimizes damage to the Si-substrate 1 or the word line poly 23.
한편, 상기 질화막(27) 식각시 콘택홀(33)내의 질화막 스페이서를 원할히 형성시킬 수 있도록 바이어스 파워를 낮춤으로 이온 에너지를 적절히 줄이며, 분산(Scattering)이 일어나지 않도록 조절한다.On the other hand, when the nitride layer 27 is etched, the ion energy is appropriately reduced by lowering the bias power so that the nitride spacer in the contact hole 33 can be formed smoothly, and the scattering is prevented.
다음, 상부의 감광막 마스크(29)를 제거한다.Next, the upper photoresist mask 29 is removed.
이상 상술한 바와 같이, 산화막 식각 후 웨이퍼에 전면 증착된 질화막을 식각하여 콘택홀을 오픈시키고, 동시에 스페이서를 형성하여 서로 다른 배선간 절연막으로 사용하는 본 발명의 방법은 다음과 같은 효과를 가진다.As described above, the method of the present invention using the nitride film deposited on the wafer after etching the oxide film to open the contact hole, and at the same time forming a spacer to use different inter-wire insulating films, has the following effects.
첫째, 질화막을 두껍게 사용함으로써 산화막 식각시 공정 창(window)을 넓힐 수 있고,First, by using a thick nitride film, the process window can be widened during oxide etching.
둘째, 산화막 식각시 폴리머를 조절하여 수직의 식각단면을 갖는 식각을 행함으로서 넓은 콘택홀 면적을 확보하여 낮은 콘택홀 저항을 갖는 콘택홀을 형성할 수 있고,Second, by etching the oxide layer to etch the polymer having a vertical etching cross-section to secure a wide contact hole area to form a contact hole having a low contact hole resistance,
셋째, 산화막 식각에 이어 질화막 식각을 연속적으로 행함으로서 공정을 단순화 할수 있고,Third, the process can be simplified by performing nitride film etching subsequent to oxide film etching,
넷째, 워드라인 위에 절연막으로 산화막을 사용함으로써 질화막에 의한 스트레스를 트랜지스터의 동작특성 악화를 방지할 수 있다.Fourth, by using an oxide film as an insulating film on the word line, the stress caused by the nitride film can be prevented from deteriorating the operating characteristics of the transistor.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980042849A KR20000025686A (en) | 1998-10-13 | 1998-10-13 | Method for forming contact hole of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980042849A KR20000025686A (en) | 1998-10-13 | 1998-10-13 | Method for forming contact hole of semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000025686A true KR20000025686A (en) | 2000-05-06 |
Family
ID=19553944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980042849A KR20000025686A (en) | 1998-10-13 | 1998-10-13 | Method for forming contact hole of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000025686A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040041252A (en) * | 2002-11-09 | 2004-05-17 | 삼성전자주식회사 | Magnetic enhanced reactive ion etching process for manufacturing method of semiconductor device |
| KR100565481B1 (en) * | 2001-06-11 | 2006-03-30 | 엘지전자 주식회사 | production device and the method of thin film transistor- Liquid crystal display |
| KR100879745B1 (en) * | 2002-12-30 | 2009-01-21 | 주식회사 하이닉스반도체 | Method of forming contact for semiconductor device |
| KR100910865B1 (en) * | 2002-12-26 | 2009-08-06 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
-
1998
- 1998-10-13 KR KR1019980042849A patent/KR20000025686A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100565481B1 (en) * | 2001-06-11 | 2006-03-30 | 엘지전자 주식회사 | production device and the method of thin film transistor- Liquid crystal display |
| KR20040041252A (en) * | 2002-11-09 | 2004-05-17 | 삼성전자주식회사 | Magnetic enhanced reactive ion etching process for manufacturing method of semiconductor device |
| KR100910865B1 (en) * | 2002-12-26 | 2009-08-06 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
| KR100879745B1 (en) * | 2002-12-30 | 2009-01-21 | 주식회사 하이닉스반도체 | Method of forming contact for semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100458360B1 (en) | Etching high aspect contact holes in solid state devices | |
| US6660652B2 (en) | Method for fabricating semiconductor device | |
| US6878637B2 (en) | Method for fabricating semiconductor device capable of improving process margin of self align contact | |
| KR20000025686A (en) | Method for forming contact hole of semiconductor devices | |
| US20060110910A1 (en) | Method for forming landing plug poly of semiconductor device | |
| KR100275340B1 (en) | Method for manufacturing contact hole of semiconductor device | |
| KR20000045442A (en) | Fabrication method of contacts for semiconductor device | |
| KR100244426B1 (en) | Method of forming contact hole in semiconductor device | |
| KR100326260B1 (en) | A method for forming conductive line in semiconductor device using multi-step etch | |
| KR100585084B1 (en) | Self-align contact etch method of semiconductor device | |
| KR20030075745A (en) | Method of Forming Metal Gate in Semiconductor Device | |
| KR100600288B1 (en) | Method of forming a semiconductor device | |
| KR100430688B1 (en) | Method of forming contact hole of semiconductor device | |
| KR100861289B1 (en) | Method for manufacturing metal line in semiconductor device | |
| KR19990033881A (en) | Method for forming self-aligned contacts in semiconductor devices | |
| KR100276562B1 (en) | Method of forming a contact hole in a semiconductor device | |
| KR100431818B1 (en) | Forming method for self aligned contact of semiconductor device | |
| KR100386454B1 (en) | Method for forming the semiconductor device | |
| KR100310823B1 (en) | Contact hole formation method of semiconductor device | |
| KR20050002005A (en) | Method for fabricating semiconductor device capable of forming storage node contact hole and insulating spacer of bit line | |
| KR100403951B1 (en) | Method for forming contact hole of semiconductor device | |
| KR20040002228A (en) | A method for forming a semiconductor device | |
| KR19990057377A (en) | Self-aligned Contact Method of Semiconductor Devices | |
| KR20000043202A (en) | Method for forming contact of semiconductor device | |
| KR20030003425A (en) | Method for fabricating semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |