KR100244426B1 - Method of forming contact hole in semiconductor device - Google Patents

Method of forming contact hole in semiconductor device Download PDF

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KR100244426B1
KR100244426B1 KR1019970029676A KR19970029676A KR100244426B1 KR 100244426 B1 KR100244426 B1 KR 100244426B1 KR 1019970029676 A KR1019970029676 A KR 1019970029676A KR 19970029676 A KR19970029676 A KR 19970029676A KR 100244426 B1 KR100244426 B1 KR 100244426B1
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forming
contact hole
film
semiconductor device
interlayer insulating
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KR19990005478A (en
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김동석
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 제조 분야에 관한 것임.Regarding the field of semiconductor manufacturing.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

마스크 정렬 오차에 의하여 발생하는 쇼트 문제를 해결하며 콘택홀의 폭을 충분히 확보할 수 있는 반도체 장치의 콘택홀 형성 방법을 제공하고자 한다.It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device which solves a short problem caused by a mask alignment error and sufficiently secures a contact hole width.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

식각장벽막인 실리콘 질화막을 형성한 후 이온주입 방지막으로 사용되는 측벽 산화막을 형성하여 콘택홀 형성을 위한 층간절연막 식각 과정에서 측벽 산화막을 함께 제거한다.After forming the silicon nitride film as an etch barrier film, a sidewall oxide film used as an ion implantation prevention film is formed to remove the sidewall oxide film during the interlayer insulating film etching process for forming the contact hole.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 장치 제조 공정에 이용됨.Used in semiconductor device manufacturing process.

Description

반도체 장치의 콘택홀 형성 방법Method for forming contact hole in semiconductor device

본 발명은 반도체 장치 제조 방법에 관한 것으로 특히, 마스크 정렬 오차에 의하여 발생하는 소자의 신뢰도 저하를 방지하기 위한 반도체 장치의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for preventing a decrease in reliability of a device caused by a mask alignment error.

이하, 첨부된 도면을 참조하여 종래 기술에 따른 콘택홀 형성 방법을 설명한다Hereinafter, a method for forming a contact hole according to the related art will be described with reference to the accompanying drawings.

먼저, 도1a에 도시한 바와 같이 실리콘 기판(11) 상에 소자분리를 위한 절연막(12)을 형성한 후 게이트 산화막(13)을 형성한다. 다음으로 폴리실리콘막으로 게이트 전극(14)을 형성하고 이온주입 방지막으로 사용되는 측벽산화막(15)을 형성한다. 이어서, 소정의 공정을 실시한 후, 실리콘산화막으로 층간절연막(16)을 형성하고 선택적으로 식각하여 콘택홀(17)을 형성한다.First, as shown in FIG. 1A, an insulating film 12 for device isolation is formed on a silicon substrate 11, and then a gate oxide film 13 is formed. Next, a gate electrode 14 is formed of a polysilicon film and a sidewall oxide film 15 used as an ion implantation prevention film is formed. Subsequently, after performing a predetermined process, the interlayer insulating film 16 is formed of a silicon oxide film and selectively etched to form a contact hole 17.

상기와 같이 이루어지는 종래의 콘택홀 형성 방법은 소자의 집적도가 증가함에 따라 마스크 공정에서 발생하는 약간의 정렬 오차에 의해서도 콘택홀 내에 형성되는 전도막과 게이트 전극을 이루는 워드라인(word line)이 전기적으로 쇼트(short)되는 문제점이 있다.In the conventional method for forming a contact hole as described above, a word line forming a conductive film and a gate electrode electrically formed in the contact hole is electrically formed by a slight alignment error generated in the mask process as the degree of integration of the device increases. There is a problem of shorting.

상기 문제점을 해결하기 위하여 종래 기술로 실리콘질화막을 형성하여 식각 장벽막으로 사용하는 실리콘질화막 장벽 자기정렬 콘택홀(silicon nitride barrier self aligned contact hole) 형성 방법을 이용하기도 한다. 이하, 도1b를 참조하여 종래 기술에 따른 실리콘질화막 장벽 자기정렬 콘택홀 형성 방법을 설명한다.In order to solve the above problem, a method of forming a silicon nitride barrier self aligned contact hole using a silicon nitride layer and forming an etching barrier layer may be used. Hereinafter, a method of forming a silicon nitride film barrier self-aligned contact hole according to the prior art will be described with reference to FIG. 1B.

먼저, 도시한 바와 같이 게이트 전극(14) 상에 식각장벽으로 산화질화막(18)을 형성하고 전체 구조 상부에 실리콘질화막(19)을 형성한다. 이어서, 실리콘산화막으로 층간절연막(16)을 형성한 후 선택적으로 식각하여 콘택홀(17)을 형성한다. 이때 상기 층간절연막(16)과 식각율이 다른 실리콘질화막(19)은 제거되지 않고 남는다. 이어서, 상기 실리콘질화막(19)을 식각하여 반도체 기판(11)이 드러나도록 하는데 상기 실리콘질화막(19)과 식각율이 다른 상기 산화질화막(18)이 게이트 전극(14)이 노출되는 것을 방지하여 쇼트를 방지할 수 있다.First, as shown, an oxynitride film 18 is formed on the gate electrode 14 as an etch barrier, and a silicon nitride film 19 is formed on the entire structure. Subsequently, the interlayer insulating film 16 is formed of a silicon oxide film and then selectively etched to form a contact hole 17. At this time, the silicon nitride film 19 whose etching rate is different from that of the interlayer insulating film 16 is left without being removed. Subsequently, the silicon nitride layer 19 is etched to expose the semiconductor substrate 11. The oxynitride layer 18 having an etch rate different from that of the silicon nitride layer 19 is prevented from exposing the gate electrode 14. Can be prevented.

그러나, 상기 질화막 장벽 자기 정렬 콘택홀 형성 방법은 인접한 폴리실리콘막과의 전기적 쇼트는 방지할 수 있으나 콘택홀의 폭(a)이 좁아지는 단점이 있다.However, the method of forming the nitride barrier barrier self-aligned contact hole prevents electrical short with the adjacent polysilicon film, but has a disadvantage in that the width (a) of the contact hole is narrowed.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 이웃하는 전도막과의 쇼트를 방지하며 콘택홀의 폭을 충분히 확보할 수 있는 반도체 장치의 콘택홀 형성 방법을 제공하는 것을 그 목적으로 한다.An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of preventing a short with a neighboring conductive film and sufficiently securing the width of the contact hole.

도1a 내지 도1b는 종래 기술에 따른 반도체 장치의 콘택홀 형성 공정 단면도1A to 1B are cross-sectional views of a contact hole forming process of a semiconductor device according to the prior art

도2a 내지 도2b는 본 발명의 일실시예에 따른 반도체 장치의 콘택홀 형성 공정 단면도2A to 2B are cross-sectional views of a contact hole forming process of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

11, 21: 실리콘 기판 12, 22: 절연막11, 21: silicon substrate 12, 22: insulating film

13, 23: 게이트 산화막 14, 24: 게이트 전극13, 23: gate oxide film 14, 24: gate electrode

15, 27: 측벽 산화막 16, 28: 층간절연막15, 27: side wall oxide film 16, 28: interlayer insulating film

17, 29: 콘택홀 18, 25:산화질화막17, 29: contact hole 18, 25: oxynitride film

20, 26: 실리콘질화막20, 26: silicon nitride film

상기 목적을 달성하기 위한 본 발명은 반도체 장치의 콘택홀 형성 방법에 있어서, 반도체 기판 상에 형성된 게이트 전극 상부에 식각장벽막을 형성하는 단계; 전체 구조 상부에 제1 층간절연막을 형성하는 단계; 상기 게이트 전극 측벽에 스페이서를 형성한 후, 반도체 기판의 소정 영역에 이온주입 공정을 실시하는 단계; 상기 스페이서를 제거하는 단계; 전체 구조 상부에 제2 층간절연막을 형성하는 단계; 상기 제1 및 제2 층간절연막을 선택적으로 식각하여 상기 반도체 기판의 소정 영역을 노출하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: forming an etch barrier layer on a gate electrode formed on a semiconductor substrate; Forming a first interlayer insulating film over the entire structure; Forming a spacer on sidewalls of the gate electrode and then performing an ion implantation process on a predetermined region of the semiconductor substrate; Removing the spacers; Forming a second interlayer insulating film over the entire structure; Selectively etching the first and second interlayer insulating films to expose a predetermined region of the semiconductor substrate.

이하, 첨부된 도면을 참조하여 본 발명을 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.

도2a 내지 도2b는 본 발명의 일실시예에 따른 반도체 장치의 콘택홀 형성 공정 단면도이다.2A through 2B are cross-sectional views illustrating a process of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

먼저, 도2a에 도시한 바와 같이 실리콘 기판(21) 위해 소자 분리를 위한 절연막(22)과 게이트 산화막(23)을 형성한다. 다음으로, 폴리실리콘막으로 게이트 전극(24)을 형성하고 게이트 전극 상에 식각장벽막으로 산화질화막(25)을 형성한다. 다음으로, 식각장벽막으로 전체 구조 상부에 200 내지 800 Å 두께의 실리콘질화막(26)을 증착한 후 이온주입 방지막으로 측벽산화막(27)을 형성한다.First, as shown in FIG. 2A, an insulating film 22 and a gate oxide film 23 for device isolation are formed for the silicon substrate 21. Next, the gate electrode 24 is formed of a polysilicon film, and the oxynitride film 25 is formed of an etch barrier film on the gate electrode. Next, a silicon nitride film 26 having a thickness of 200 to 800 에 is deposited on the entire structure with an etch barrier film, and then a sidewall oxide film 27 is formed with an ion implantation prevention film.

다음으로, 도2b에 도시한 바와 같이 이온주입 공정 등의 소정의 공정을 실시한 후, 상기 실리콘질화막(26)을 식각 장벽막으로해서 상기 측벽 산화막을 습식 식각으로 제거한다. 이때 습식 식각에 사용되는 용액으로는 HF 용액 또는 NH4F와 HF가 혼합된 완충 산화 식각제(buffered oxide etchant, BOE)를 사용한다. 이어서, 층간절연막(28)으로 3000 내지 8000 Å 두께의 산화막을 형성하고 상기 층간절연막(28)과 상기 실리콘질화막(26)을 비등방 식각하여 콘택홀(29)을 형성한다. 이때 상기 비등방 식각은 실리콘 기판 또는 산화막과의 식각 선택비가 5:1 이상되는 질화막 식각 조건으로 이루어진다.Next, as shown in FIG. 2B, after a predetermined process such as an ion implantation process, the sidewall oxide film is removed by wet etching using the silicon nitride film 26 as an etch barrier film. In this case, as a solution used for wet etching, a buffered oxide etchant (BOE) mixed with HF solution or NH 4 F and HF is used. Subsequently, an oxide film having a thickness of 3000 to 8000 Å is formed as the interlayer insulating film 28, and the contact hole 29 is formed by anisotropically etching the interlayer insulating film 28 and the silicon nitride film 26. In this case, the anisotropic etching is made of a nitride film etching condition in which the etching selectivity with the silicon substrate or the oxide film is 5: 1 or more.

상기와 같이 이루어지는 본 발명은 이온주입 방지막인 측벽산화막을 제거하여 충분한 콘택홀의 면적을 확보해서 소자의 신뢰도를 향상 시킬 수 있다.According to the present invention, the sidewall oxide film, which is an ion implantation prevention film, is removed to secure a sufficient contact hole area, thereby improving reliability of the device.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 고집적 소자의 콘택홀 형성시 발생하는 마스크 정렬 오차를 보상할 수 있어 소자의 신뢰도를 향상시킬 수 있다.The present invention made as described above can compensate for the mask alignment error generated when forming the contact hole of the highly integrated device can improve the reliability of the device.

Claims (8)

반도체 기판 상에 형성된 게이트 전극 상부에 식각장벽막을 형성하는 단계;Forming an etch barrier layer on the gate electrode formed on the semiconductor substrate; 전체 구조 상부에 제1 층간절연막을 형성하는 단계;Forming a first interlayer insulating film over the entire structure; 상기 게이트 전극 측벽에 스페이서를 형성한 후, 반도체 기판의 소정 영역에 이온주입 공정을 실시하는 단계;Forming a spacer on sidewalls of the gate electrode and then performing an ion implantation process on a predetermined region of the semiconductor substrate; 상기 스페이서를 제거하는 단계;Removing the spacers; 전체 구조 상부에 제2 층간절연막을 형성하는 단계;Forming a second interlayer insulating film over the entire structure; 상기 제1 및 제2 층간절연막을 선택적으로 식각하여 상기 반도체 기판의 소정 영역을 노출하는 단계를 포함하여 이루어지는 반도체 장치의 콘택홀 형성 방법.Selectively etching the first and second interlayer insulating films to expose a predetermined region of the semiconductor substrate. 제 1 항에 있어서,The method of claim 1, 상기 식각장벽막을 산화질화막 및 실리콘질화막 중 어느 하나로 형성하는 반도체 장치의 콘택홀 형성 방법.And forming the etch barrier film into one of an oxynitride film and a silicon nitride film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제1 층간절연막을 실리콘질화막으로 형성하는 반도체 장치의 콘택홀 형성 방법.A method for forming a contact hole in a semiconductor device, wherein the first interlayer insulating film is formed of a silicon nitride film. 제 3 항에 있어서,The method of claim 3, wherein 상기 제2 층간절연막을 산화막으로 형성하는 반도체 장치의 콘택홀 형성 방법.A method for forming a contact hole in a semiconductor device, wherein the second interlayer insulating film is formed of an oxide film. 제 2 항에 있어서,The method of claim 2, 상기 스페이서는 산화막으로 형성되며 상기 스페이서 제거 단계는 습식식각으로 이루어지는 반도체 장치의 콘택홀 형성 방법.The spacer is formed of an oxide film and the spacer removing step is a wet etching method of forming a contact hole of a semiconductor device. 제 3 항에 있어서,The method of claim 3, wherein 상기 실리콘질화막을 200 내지 800 Å 두께로 형성하는 반도체 장치의 콘택홀 형성 방법.A method for forming a contact hole in a semiconductor device, wherein the silicon nitride film is formed to a thickness of 200 to 800 GPa. 제 4 항에 있어서,The method of claim 4, wherein 상기 산화막을 3000 내지 8000 Å 두께로 형성하는 반도체 장치의 콘택홀 형성 방법.A method for forming a contact hole in a semiconductor device, wherein the oxide film is formed to a thickness of 3000 to 8000 GPa. 제 5 항에 있어서,The method of claim 5, 상기 습식 식각은 HF 용액 및 NH4F와 HF가 혼합된 완충 산화 식각 용액 중 어느 하나를 사용하는 반도체 장치의 콘택홀 형성 방법.The wet etching method of forming a contact hole in a semiconductor device using any one of a HF solution and a buffered oxidation etching solution mixed with NH 4 F and HF.
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