KR20020011473A - The method of fabricating contacts in semiconductor device - Google Patents
The method of fabricating contacts in semiconductor device Download PDFInfo
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- KR20020011473A KR20020011473A KR1020000044752A KR20000044752A KR20020011473A KR 20020011473 A KR20020011473 A KR 20020011473A KR 1020000044752 A KR1020000044752 A KR 1020000044752A KR 20000044752 A KR20000044752 A KR 20000044752A KR 20020011473 A KR20020011473 A KR 20020011473A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910019142 PO4 Inorganic materials 0.000 claims 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 claims 1
- 239000010452 phosphate Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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Abstract
Description
본 발명은 콘택(contact)방법에 관한 것으로, 자세하게는 폴리층에 스페이서를 형성한 다음, 질화막으로 형성한 식각차단막에 습식식각을 실시하여, 콘택을 위한 금속과, 기판의 활성영역 및 폴리층간의 계면면적을 최대화시켜 콘택저항을 줄이고 콘택의 전기적 특성을 향상시키기 위한, 반도체소자의 콘택형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact method. In detail, a spacer is formed on a poly layer, and then wet etching is performed on an etch barrier film formed of a nitride film, and the metal for contact is formed between the active region and the poly layer of the substrate. The present invention relates to a method for forming a contact in a semiconductor device for maximizing an interfacial area to reduce contact resistance and improve electrical properties of a contact.
도 1은 반도체소자의 저항값을 설명하기 위한 종래의 콘택을 나타낸 도면이다.1 is a view showing a conventional contact for explaining a resistance value of a semiconductor device.
도 1에서, 도면부호 1은 반도체기판을, 2는 쉘로우트렌치(shallow trench)를, 3은 폴리실리콘층을, 4는 폴리실리콘층의 측벽에 형성된 스페이서(spacer)를, 5는 콘택된 금속을, 6은 절연층을 각각 나타낸다. 또한 점선은 반도체소자의 동작시 전류의 큰 흐름을 도시한 것으로서, 이러한 전류의 주된 흐름에서 각 계면간의 접촉부분 및, 전류가 흐르는 통로의 물질저항이 반도체소자의 저항값을 결정한다. 특히 반도체기판(1)상에 도시된 점선은 반도체소자의 동작영역(active)을 통해 흐르는 과정을 도식적으로 표현한 것이다.In Fig. 1, reference numeral 1 denotes a semiconductor substrate, 2 denotes a shallow trench, 3 denotes a polysilicon layer, 4 denotes a spacer formed on a sidewall of the polysilicon layer, and 5 denotes a contacted metal. And 6 represents an insulating layer, respectively. In addition, the dotted line shows a large flow of current in the operation of the semiconductor device. In the main flow of the current, the contact portion between the interfaces and the material resistance of the passage through which the current flows determine the resistance value of the semiconductor device. In particular, the dotted lines shown on the semiconductor substrate 1 schematically represent a process flowing through the active region of the semiconductor device.
도 1에 있어서 반도체소자의 저항값은, 콘택금속(5)과 반도체기판(1)간의 접촉계면, 콘택금속(5)과 폴리실리콘층(3)간의 접촉계면간의 접합특성에 따른 값을 포함하는 것은 물론, 반도체기판(1), 폴리실리콘층(3) 및 콘택금속(5)의 내부의 저항값도 포함하고 있다.In Fig. 1, the resistance value of the semiconductor element includes a value corresponding to the contact interface between the contact metal 5 and the semiconductor substrate 1 and the contact interface between the contact metal 5 and the polysilicon layer 3. Of course, it also includes resistance values inside the semiconductor substrate 1, the polysilicon layer 3, and the contact metal 5.
아울러 이러한 콘택공정도 메모리소자의 집적도가 증가함에 따라, 사이즈는 작아지고 깊이가 증가하고 있다. 또한 메모리소자의 제작에 있어서, 통상적으로 6개의 트랜지스터를 실리콘기판에 형성하는 풀-시모스(full CMOS) SRAM이나 플래시 메모리 등에서는, 금속콘택을 위해 스페이서나 식각차단막을 형성하여 이용한다.In addition, as the degree of integration of the memory device increases, the contact process also decreases in size and increases in depth. In the manufacture of memory devices, in general, a full CMOS SRAM or a flash memory in which six transistors are formed on a silicon substrate is used by forming a spacer or an etch barrier film for metal contact.
그러나, 전술한 종래의 콘택방법은 소자크기 등의 감소에 따라 다음과 같은 문제점이 있다.However, the conventional contact method described above has the following problems as the size of the device decreases.
즉, 종래의 콘택방법에서 건식식각(dry etch) 방식으로 콘택홀을 형성하는 경우, 콘택홀이 깊어짐에 따라 콘택바닥 면적의 확보가 어렵고 콘택홀의 식각지점의 설정이 곤란하다. 또한 콘택이 깊어짐에 따라 식각공정이 과도해지고 따라서 식각플라즈마에 의한 손상이 심각해지는 문제점이 있다. 또한 단락(short) 방지를 위해 스페이서를 형성하는 경우, 상대적으로 콘택홀의 바닥 면적이 감소하고 콘택저항이 증가하게 된다.That is, when the contact hole is formed by a dry etching method in the conventional contact method, as the contact hole becomes deep, it is difficult to secure the contact bottom area and it is difficult to set the etching point of the contact hole. In addition, as the contact deepens, there is a problem that the etching process is excessive, and therefore damage by the etching plasma is serious. In addition, when the spacer is formed to prevent short, the bottom area of the contact hole is relatively decreased and the contact resistance is increased.
아울러 식각차단용 질화막을 건식으로 식각하는 경우, 스페이서 형성영역에 질화막이 남아서 콘택면적을 감소시켜, 콘택저항을 증가시키는 문제점이 있다.In addition, when the etching barrier nitride layer is dry-etched, the nitride layer remains in the spacer formation region, thereby reducing the contact area, thereby increasing the contact resistance.
따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, 폴리-1층에 스페이서를 형성한 다음 질화막으로 형성시킨 식각차단막을 습식으로 식각하여, 콘택금속과 기판의 활성영역 및 폴리층간의 계면면적을 최대화시켜 콘택저항을 줄이고 콘택의 전기적 특성을 향상시키기 위한, 반도체소자의 콘택형성방법을 제공하는 데 있다.Accordingly, an object of the present invention for solving the above problems is to wet-etch an etch barrier film formed by forming a spacer on a poly-1 layer and then forming a nitride film, thereby reducing the interface area between the contact metal and the active region of the substrate and the poly layer. The present invention provides a method for forming a contact of a semiconductor device for maximizing contact resistance and improving contact electrical properties.
도 1은 반도체소자의 저항값을 설명하기 위한 종래의 콘택을 나타낸 도면.1 is a view showing a conventional contact for explaining a resistance value of a semiconductor device.
도 2a 내지 도 2f 본 발명의 실시예에 따른 반도체소자의 콘택형성방법을 설명하기 위한 공정도.2A to 2F are process drawings for describing a method for forming a contact in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 기판 12 : 소자분리막10 substrate 12 device isolation film
14 : 폴리층 16 : 스페이서14 poly layer 16 spacer
18 : 질화막 20 : IPO산화막18 nitride film 20 IPO oxide film
22 : 콘택홀 24 : 확산방지막22 contact hole 24 diffusion barrier
26 : 금속매립층26: metal buried layer
본 발명에 따른 반도체소자의 콘택형성방법은, 반도체 공정의 콘택에 있어서,The contact forming method of a semiconductor device according to the present invention, in the contact of the semiconductor process,
기판에 소자분리막 및 활성영역이 포함되도록 형성시키는 제1단계; 상기 형성된 소자분리막의 상부에, 상기 활성영역과 인접된 상태로 그 측벽이 절연되도록폴리층을 형성하는 제2단계; 상기 형성된 폴리층 및 기판의 전면에 식각을 차단하기 위한 식각차단막을 형성하는 제3단계; 상기 식각차단막의 상부에 산화막을 증착하는 제4단계; 상기 인접된 활성영역 및 폴리층의 상부가 개방되도록, 상기 산화막 및 식각차단막을 식각하여 콘택홀을 형성하는 제5단계; 상기 형성된 콘택홀의 내부표면 및 상기 산화막의 전면에 확산방지막을 형성하는 제6단계; 및, 상기 확산방지막이 형성된 콘택홀을 금속으로 매립하여 콘택을 형성하는 제7단계를 포함한다.Forming a device isolation film and an active region on the substrate; Forming a poly layer on the formed isolation layer, the sidewalls being insulated from the active region; A third step of forming an etch barrier layer for blocking etching on the formed poly layer and the entire surface of the substrate; Depositing an oxide layer on the etch barrier layer; A fifth step of forming a contact hole by etching the oxide layer and the etch barrier layer so that the upper portion of the adjacent active region and the poly layer is opened; A sixth step of forming a diffusion barrier on an inner surface of the formed contact hole and an entire surface of the oxide film; And a seventh step of forming a contact by filling the contact hole in which the diffusion barrier is formed with metal.
이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체소자의 콘택형성방법을 설명하기 위한 공정도이다.2A through 2F are process diagrams for describing a method for forming a contact in a semiconductor device according to an embodiment of the present invention.
콘택에서의 저항값은 금속콘택이 형성되는 위치나 형태에 따라 달라진다. 즉, 전류가 흐르는 통로에 콘택이 형성되어 있을 경우, 전류가 잘 흐를 수 있는 통로의 콘택과 접하고 있는 각 계면들의 특성에 따라서 콘택저항값이 결정된다. 일반적으로 반도체소자에 있어서 이러한 전류의 통로는 폴리층(poly), 트랜지스터의 활성영역(active) 그리고 콘택금속 등에 의해 형성된다. 따라서 이 폴리층(poly), 활성영역(active) 그리고 콘택금속이 인접하도록 형성되는 경우, 콘택저항값은 감소하게 되며, 본 발명은 이러한 인접특성이 적용되도록 콘택시키는 특징이 있다.The resistance value at the contact depends on the position or shape at which the metal contact is formed. That is, when the contact is formed in the passage through which the current flows, the contact resistance value is determined according to the characteristics of each interface contacting the contact of the passage through which the current can flow well. In general, in the semiconductor device, the current path is formed by a poly layer, an active region of a transistor, and a contact metal. Therefore, when the poly layer, the active region, and the contact metal are formed to be adjacent to each other, the contact resistance value is reduced, and the present invention has a feature of contacting such adjacent characteristics to be applied.
도 2a에 도시한 바와 같이, 본 실시예에서는 먼저 기판(10) 상부에 소자분리막(12, Field OXide ; Fox)을 형성한 후, 그 상부를 평탄화시킨다. 그리고 소자분리막(12, Fox)이 형성되지 않은 기판(10)의 소정부위에 이온을 주입하여 활성영역(10a, active)을 형성시킨다. 이 후 도시한 바와 같이, 소자분리막(12) 상부의 평탄화된 기판(10)에 폴리층(14)을 패터닝하고, 그 측면에 스페이서(16)를 형성시킨다. 이 스페이서(16)는 실리콘옥사이드를 이용하여 약 500∼1500Å두께로 형성한다. 이 후 형성된 구조물들의 상부에, 식각을 방지하기 위한 식각차단막으로서 약 200∼500Å 두께로 질화막(18)을 증착한다. 그리고 이 질화막(18)의 상부에 IPO(Inter Poly Oxide)를 증착하여 IPO산화막(20)을 형성한다.As shown in FIG. 2A, the device isolation film 12 (Field OXide; Fox) is first formed on the substrate 10, and then the top of the device is planarized. The active region 10a is formed by implanting ions into a predetermined portion of the substrate 10 on which the device isolation layers 12 and Fox are not formed. Thereafter, as illustrated in the drawing, the poly layer 14 is patterned on the planarized substrate 10 on the device isolation layer 12, and spacers 16 are formed on the side surface thereof. This spacer 16 is formed to a thickness of about 500 to 1500 kHz using silicon oxide. After that, the nitride film 18 is deposited to a thickness of about 200 to 500 Å as an etch barrier film to prevent etching. Then, an IPO (Inter Poly Oxide) is deposited on the nitride film 18 to form an IPO oxide film 20.
이 후 도 2b와 같이, IPO산화막(20)에 콘택홀(22)을 위한 마스킹을 실시한 후, 하부의 질화막(18)에서 식각이 차단되도록 IPO산화막(20)을 건식식각하여 콘택홀(22)을 형성한다.After that, as shown in FIG. 2B, after masking the contact hole 22 to the IPO oxide layer 20, the IPO oxide layer 20 is dry-etched to block etching from the lower nitride layer 18. To form.
이 후 도 2c와 같이, 인산용액으로 습식식각을 실시하여, 식각차단막으로 형성시킨 콘택홀(22)내부의 질화막(18)을 식각한다. 이렇게 하면 IPO산화막(20)하부의 질화막(18)은 움푹 패인 형태로 형성된다.Thereafter, as shown in FIG. 2C, the wet etching is performed using a phosphoric acid solution to etch the nitride film 18 inside the contact hole 22 formed by the etching barrier film. In this way, the nitride film 18 under the IPO oxide film 20 is formed in a recessed shape.
이후 BOE 클리닝(cleaing)을 실시하여 콘택홀(22)내부 및 IPO산화막(20)을 세정한다. 이 과정에서 IPO산화막(20)과 스페이서(16)용 산화막이 약간 식각되어 도 1d와 같은 형태로 형성된다.Thereafter, BOE cleaning is performed to clean the inside of the contact hole 22 and the IPO oxide layer 20. In this process, the IPO oxide film 20 and the oxide film for the spacer 16 are slightly etched to form the shape shown in FIG. 1D.
다음 도 2e와 같이, 확산방지를 위해 콘택홀(22)내부로부터 티타늄(Ti) 및 질화티타늄(TiN)을 연속적으로 증착하거나, 탄탈(Ta) 및 질화탄탈(TaN)을 연속적으로 증착하여 확산방지막(24)을 형성한다.Next, as shown in FIG. 2E, to prevent diffusion, titanium (Ti) and titanium nitride (TiN) are continuously deposited from the inside of the contact hole 22, or tantalum (Ta) and tantalum nitride (TaN) are continuously deposited. To form (24).
이 후 도 2f와 같이, 금속을 증착하여 확산방지막(24)이 형성된 콘택홀(22)을 매립하여 금속매립층(26)을 형성함으로써, 콘택저항이 감소된 본 발명에 따른 반도체소자의 콘택형성방법을 완료한다.Thereafter, as illustrated in FIG. 2F, the method for forming a contact of the semiconductor device according to the present invention, in which the contact resistance is reduced by depositing metal to fill the contact hole 22 having the diffusion barrier 24 formed therein to form the metal buried layer 26. To complete.
전술한 바와 같이, 본 발명은 기판의 활성영역 및 폴리층간의 계면면적을 최대화시켜 콘택저항을 줄이고 콘택의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention has the effect of maximizing the interfacial area between the active area of the substrate and the poly layer to reduce the contact resistance and improve the electrical properties of the contact.
Claims (12)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491458B1 (en) * | 2001-12-10 | 2005-05-25 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| US9496381B2 (en) | 2012-03-15 | 2016-11-15 | Samsung Electtonics Co., Ltd. | Semiconductor device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541434A (en) * | 1992-09-11 | 1996-07-30 | Inmos Limited | Semiconductor device incorporating a contact for electrically connecting adjacent portions within the semiconductor device |
| JPH09199589A (en) * | 1996-01-18 | 1997-07-31 | Sony Corp | Wiring pattern formation |
| KR19990005478A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Method for forming contact hole in semiconductor device |
| KR19990057377A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Self-aligned Contact Method of Semiconductor Devices |
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- 2000-08-02 KR KR1020000044752A patent/KR20020011473A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541434A (en) * | 1992-09-11 | 1996-07-30 | Inmos Limited | Semiconductor device incorporating a contact for electrically connecting adjacent portions within the semiconductor device |
| JPH09199589A (en) * | 1996-01-18 | 1997-07-31 | Sony Corp | Wiring pattern formation |
| KR19990005478A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Method for forming contact hole in semiconductor device |
| KR19990057377A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Self-aligned Contact Method of Semiconductor Devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491458B1 (en) * | 2001-12-10 | 2005-05-25 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| US9496381B2 (en) | 2012-03-15 | 2016-11-15 | Samsung Electtonics Co., Ltd. | Semiconductor device and method of fabricating the same |
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