KR19990057377A - Self-aligned Contact Method of Semiconductor Devices - Google Patents

Abstract

The present invention relates to a self-aligned contact method of a semiconductor device, wherein a gate electrode is formed over a semiconductor substrate, an interlayer insulating film is formed over the entire surface, a planarization insulating film is formed over the entire surface, and the planarization insulating film is etched. Exposing the interlayer insulating layer by an etching process using a contact mask, and then isotropically etching the interlayer insulating layer by using an etch selectivity difference with the planarization insulating layer. It is a technology that can improve the characteristics and reliability of the semiconductor device by forming a contact to facilitate the contact process.

Description

Self-aligned Contact Method of Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-aligned contact method of a semiconductor device, and more particularly, to a technique of forming a self-aligned contact hole using a nitride film as an etch barrier.

In general, a refresh time, which is an important characteristic of a memory device, is mainly determined by a leakage current generated by damaging the drain during a storage electrode contact process connecting the storage electrode node and the drain of the transistor.

In the current exposure technology, when forming a contact hole up to 16 M DRAM, a device can be formed without a poor insulation with the conductive layer of the sidewall of the contact hole. However, as the device is highly integrated, the unit cell size is reduced. As a result, the gap between the contact hole and the conductive layer is narrowed.

In order to form a narrowed contact hole as described above, the size of the contact should be reduced. For this purpose, the exposure method or the mask may be changed to some extent. In addition, self-aligned contacts (hereinafter referred to as SAC) have been solved.

On the other hand, the most popular among the SAC process is using a nitride barrier SAC (nitride barrier SAC, hereinafter referred to as NBSAC) process using a nitride film as the etching barrier.

The NBSAC process is roughly classified into an oxide layer etching process and a nitride layer etching process.

In the oxide film etching process, a large amount of C ₃ F ₈ or C ₄ F ₈ gas, which is a polymer induced gas, is used to obtain a high etching selectivity with respect to the nitride film. The C ₃ F ₈ or C ₄ F ₈ gas may induce a large number of polymers to secure an etching selectivity for the nitride film, but there is a problem that the etch stop is not completely removed in the contact hole.

Here, the selectivity and the etch stop with respect to the nitride film are factors that are mutually opposite, which narrows the process window and deteriorates reproducibility.

In order to extend the flow window, a condition in which polymer is generated is used. In this case, the thickness of the nitride film must be increased. However, if the thickness of the nitride film is increased, the contact area is reduced, so that the nitride film should be isotropically etched to compensate for this.

In addition, since the oxide layer under the nitride layer is used as an electrical insulating layer, the nitride layer has to be as little as possible to damage the oxide layer. A high etching selectivity difference with respect to the oxide layer is required, and the portion where the semiconductor substrate is exposed when the oxide layer is etched in the peripheral circuit area is required. There is a need for a condition that minimizes the etching of the semiconductor substrate.

However, ion induced etcher, which is one of the conventional nitride film etching equipment, cannot obtain high etching selectivity for isotropic etching and oxide film.

In addition, the radical etcher, which has recently been in the spotlight, uses gases such as NF ₃ , CF ₄ , SF _6, etc., so it is possible to secure a high etching selectivity for isotropic etching and oxide films, but silicon as a semiconductor substrate It is not possible to secure high etch selectivity.

Because the most influential factor in etching is etchant, but in the case where the main etchant is a fluorine series such as NF ₃ , CF ₄ , SF _6, etc., the radical etching equipment is an oxide film or a nitride film. Since both silicon and silicon can be etched, the bonding force of the thin film determines the etching rate. That is, when the bonding force is in the order of oxide film> nitride film> silicon, since the etching of silicon proceeds fastest, it is impossible to secure a high etching selectivity with respect to silicon during the nitride film etching process.

According to the present invention, in order to solve the problems of the prior art, by adding CH ₃ OH gas to the etching gas, it is possible to secure an isotropic etching shape and high etching characteristics with respect to the oxide film and Si during etching the nitride film. It is an object of the present invention to provide a self-aligned contact method of a semiconductor device which can improve the characteristics and reliability of the semiconductor device and thereby enable high integration of the semiconductor device.

1 to 6 are cross-sectional views showing a self-aligned contact method of a semiconductor device according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11: first conductor 13: mask oxide film

15: first photosensitive film pattern 17: insulating film spacer

19 interlayer insulating film 21 planarization insulating film

23: second photosensitive film pattern 25: contact hole

In order to achieve the above object, a self-aligned contact method of a semiconductor device according to the present invention,

Forming a gate electrode on the semiconductor substrate;

Forming an interlayer insulating film over the entire surface;

Forming a planarization insulating film over the entire surface;

Etching the planarization insulating layer and performing an etching process using a contact mask to expose the interlayer insulating layer;

And isotropically etching the interlayer insulating layer by using an etching selectivity difference from the planarization insulating layer, and adding CH ₃ OH gas to the stock corner gas.

On the other hand, the principle of the self-aligned contact method of the semiconductor device for achieving the above object,

CH ₃ OH gas is added to the main etching gas to improve the isotropic etching shape and high etching characteristics for the oxide film and silicon, which is an oxide substrate during etching of the nitride film.

That is, the CH ₃ OH gas dissociates in the plasma to form H, which combines with N formed when Si ₃ N ₄ is etched by a gas such as NF ₃ or CF ₄ to form a volatile etching product such as NH ₃ . To facilitate etching. In addition, SiO ₂ and Si are etched because CH ₃ OH reacts with NF ₃ or CF ₄ gas to form a polymer on the surface of the thin film. Therefore, when CH ₃ OH gas is used, it is possible to develop a condition for obtaining a high etching selectivity with respect to the oxide film and the nitride film during isotropic etching.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, a first conductor 11 for a gate electrode is formed on a semiconductor substrate (not shown), a mask oxide film 13 is formed on the gate electrode, and then a gate electrode mask (shown on the mask oxide film 13). First photosensitive film pattern 15 is formed by an exposure and development process using the &quot;

In this case, the first conductor 11 may be formed of polycrystalline silicon, tungsten or polyside. (Figure 1)

The first conductor 11 and the mask oxide film 13 are etched using the first photoresist pattern 15 as a mask.

After removing the first photoresist layer pattern 15, an insulating layer spacer 17 is formed on sidewalls of the first conductor 11 and the mask oxide layer 13. At this time, the insulating film spacers 17 are formed by forming an insulating film on the entire surface and anisotropically etching them. (FIG. 2, FIG. 3)

Then, an interlayer insulating film 19 is formed on the entire surface of the nitride film. Then, the planarization insulating film 21 is formed to planarize the entire upper surface portion. In this case, the planarization insulating layer 21 is formed of an insulating material having excellent fluidity, such as BPSG.

A second photoresist layer pattern 23 is formed on the planarization insulating layer 21. In this case, the second photoresist layer pattern 23 is formed by an etching process using a contact mask (not shown). (Figure 4)

Next, the planarization insulating layer 21 is etched using the second photoresist pattern 23 as a mask and the interlayer insulating layer 19 as an etch barrier. At this time, the etching process is carried out using a gas such as C ₃ F ₈ , C ₄ F ₈ , C ₂ HF ₅ causing a lot of polymers. (Figure 5)

In addition, a contact hole 25 is formed by a self-aligned process of etching the interlayer insulating layer by an isotropic etching process using an etching selectivity difference from the planarization insulating layer 21, and the second photoresist layer pattern 23 is removed. do.

At this time, during the isotropic etching process, the interlayer insulating film 19 formed of the nitride film is laterally etched to form an undercut. (Figure 6)

As described above, the self-aligned contact method of the semiconductor device according to the present invention is a self-aligned contact process that secures a contact area by isotropically etching a nitride film used as an etch barrier layer during oxide etching, thereby ensuring a process window and reproducibility. There is an effect that can be secured.

Claims (3)

Forming a gate electrode on the semiconductor substrate; Forming an interlayer insulating film over the entire surface; Forming a planarization insulating film over the entire surface; Etching the planarization insulating layer and performing an etching process using a contact mask to expose the interlayer insulating layer; And isotropically etching the interlayer insulating layer by using an etch selectivity difference from the planarization insulating layer, and adding CH ₃ OH gas to the stock corner gas. The method of claim 1, And said interlayer insulating film is formed of a nitride film. The method of claim 1, And the planarization insulating film is formed of an insulating material having excellent fluidity such as BPSG.