KR100458087B1 - Method for fabricating semiconductor device to etch oxide layer by gas including small quantity of polymer - Google Patents
Method for fabricating semiconductor device to etch oxide layer by gas including small quantity of polymer Download PDFInfo
- Publication number
- KR100458087B1 KR100458087B1 KR1019970029023A KR19970029023A KR100458087B1 KR 100458087 B1 KR100458087 B1 KR 100458087B1 KR 1019970029023 A KR1019970029023 A KR 1019970029023A KR 19970029023 A KR19970029023 A KR 19970029023A KR 100458087 B1 KR100458087 B1 KR 100458087B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- etching
- layer
- gas
- oxide layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229920000642 polymer Polymers 0.000 title claims abstract description 9
- 230000008569 process Effects 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 230000000087 stabilizing effect Effects 0.000 claims description 3
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical compound [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 abstract description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 11
- 229910001936 tantalum oxide Inorganic materials 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000003039 volatile agent Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 자기정렬 콘택홀 형성을 위한 산화막 건식식각시 탄탈늄산화막(Ta2O5)을 식각정지층으로 사용하는 반도체 장치 제조 방법에 관한 것이다.BACKGROUND OF THE
반도체 장치가 점차 고집적화 되어 가면서, 중첩 정확도나 광학 해상력 한계 등으로 인해, 마스크 오정렬 및 미세 홀 형성에 어려움이 있어, 64M DRAM 부터는 통상적인 콘택홀 형성 방법을 사용할 수 없게 되었다. 따라서, 종래에는 여러 가지 콘택홀 형성 방법이 제시되어 왔지만, 그들 중 질화막을 식각정지층으로 사용하는 자기 정렬 콘택(SAC : Self Aligned Contact) 방법이 가장 전망있는 공정으로 인정되어 왔다.As semiconductor devices become increasingly integrated, mask misalignment and fine hole formation are difficult due to overlapping accuracy, optical resolution limitation, etc., and thus, the conventional contact hole forming method cannot be used from 64M DRAM. Therefore, various contact hole formation methods have been proposed in the past, but among them, a self aligned contact (SAC) method using a nitride film as an etch stop layer has been recognized as the most promising process.
그러나, 질화막을 사용하는 SAC 공정은 여러 반도체 소자 제조 회사에서 다년간 연구되어 왔음에도 불구하고, 몇 가지 치명적인 문제로 인하여 실제 소자 제조에는 적용되지 않고 있다. 즉, 질화막을 사용하는 SAC 공정은, 첫째 산화막과 질화막간의 식각 선택비를 유지하기 위하여 지나치게 많은 폴리머 유발가스를 사용하여 식각 공정 재현성 확보가 어렵고, 둘째 프로세스 윈도우(Process Window)가 지나치게 좁아 콘택홀의 크기 변화에 민감하게 변화하고, 셋째 콘택홀의 에스펙트 비(Aspect Ratio)에도 지나치게 민감하게 변화하는 문제를 안고 있다.However, although the SAC process using nitride film has been studied for many years by various semiconductor device manufacturing companies, it is not applied to actual device manufacturing due to some fatal problems. That is, in the SAC process using the nitride film, first, it is difficult to secure the etching process reproducibility by using too much polymer induced gas to maintain the etching selectivity between the oxide film and the nitride film, and the second process window is too narrow so that the contact hole size It is sensitive to change and has a problem of being too sensitive to the aspect ratio of the third contact hole.
따라서, 질화막을 식각정지층으로 사용하는 종래의 SAC 공정은 실제 소자 제조에는 사용되지 못하고 있고, 설령 공정을 개발하더라도 새로운 SAC 전용 장비가 요구되어 장비의 효율성을 떨어뜨리고 소자의 제조 단가를 높이는 원인이 된다.Therefore, the conventional SAC process using the nitride film as an etch stop layer is not used in actual device manufacturing, and even if the process is developed, new SAC-specific equipment is required, which causes the efficiency of the device and the cost of manufacturing the device. do.
본 발명의 목적은 공정 재현성이 우수한 자기정렬콘택 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a self-aligned contact excellent in process reproducibility.
본 발명의 또 다른 목적은 산화막과 식각선택비가 우수한 탄탈늄산화막 (Ta2O5)을 식각정지층으로 사용하는 반도체 장치 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a semiconductor device manufacturing method using an oxide film and a tantalum oxide film (Ta 2 O 5 ) having an excellent etching selectivity as an etch stop layer.
상기 목적을 달성하기 위한, 본 발명의 반도체 장치 제조 방법은, 웨이퍼 상에 후속 공정인 산화막 식각의 식각정지를 위한 탄탈늄산화막을 형성하는 단계; 상기 탄탈늄산화막 상에 상기 산화막을 형성하는 단계; 및 폴리머 유발이 적은 소정가스 분위기에서 상기 탄탈늄산화막을 식각정지층으로 하여 상기 산화막을 식각하는 단계를 포함하여 이루어진다.In order to achieve the above object, the semiconductor device manufacturing method of the present invention comprises the steps of: forming a tantalum oxide film for the etch stop of the oxide film etching is a subsequent process on the wafer; Forming the oxide film on the tantalum oxide film; And etching the oxide film using the tantalum oxide film as an etch stop layer in a predetermined gas atmosphere with less polymer induction.
바람직하게, 상기 탄탈늄산화막은 Ta2O5막으로 하며, 상기 산화막 식각을 플로린-카본 계 가스를 주 에천트로하고, CH3F, H2, C2H2, CH 2F2, C2HF5 가스중 어느 하나 이상의 보조 에천트로하며, 플라즈마 안정화 가스를 더 포함하는 분위기에서 수행한다.Preferably, the tantalum oxide film is a Ta 2 O 5 film, and the oxide film is etched using a florin-carbon gas as a main etchant, and CH 3 F, H 2 , C 2 H 2 , CH 2 F 2 , and C 2 One or more auxiliary etchant of the HF 5 gas is carried out in an atmosphere further comprising a plasma stabilizing gas.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 1 내지 도 4는 본 발명의 일실시예에 따른 비트라인 콘택홀 형성 공정도로서, SAC 공정에서 식각정지층을 탄탈늄산화막으로 사용한 것을 보여준다.1 to 4 are bit line contact hole formation process diagrams according to an embodiment of the present invention, and show that an etch stop layer is used as a tantalum oxide layer in a SAC process.
먼저, 도 1은 실리콘 기판(1) 상에 게이트용 폴리실리콘막(2)과 하드 마스크 (hard mask)를 위한 산화막(3)을 차례로 형성한 다음 게이트 마스크 및 식각 공정을 수행하여 패터닝하고, 다시 스페이서를 위한 산화막을 증착하고 전면 비등방성 식각하여 산화막 스페이서(4)를 형성한다. 이 산화막 스페이서(4)는 LDD 구조의 접합 형성을 위한 이온주입 배리어 및 게이트 폴리실리콘막(2) 측벽과 다른 배선간의 절연막으로 사용된다.First, FIG. 1 illustrates the formation of a
이어서, 도 2는 웨이퍼 전면에 탄탈늄산화막(Ta2O5)(5)을 증착하고, BPSG 산화막(6)을 증착한 후, 열공정으로 플로우(flow)를 실시하고, 콘택 마스크 패턴이 레지스트 패턴(7)을 형성한 상태이다.Subsequently, in Fig. 2, a tantalum oxide film (Ta 2 O 5 ) 5 is deposited on the entire surface of the wafer, and a
이어서, 도 3은 식각정지층인 탄탈늄산화막(5)이 노출될때까지 BPSG 산화막 (6)을 식각한 상태로서, 도면에서와 같이, 콘택 마스크(레지스트 패턴)의 오정렬이 발생하여도 게이트 폴리실리콘 패턴은 손상 받지 않는다.3 is a state in which the
이때, 산화막 식각 조건은 CF4, CHF3, C2F6, C3F 8, C4F8 등의 플로린(F : fluorine)-카본(C : carbon) 계열 가스, 바람직하게는 CF4 + CHF3 의 주 에천트(main etchant)에, CH3F, H2, C2H2, CH2F 2, C2HF5 등과 같은 보조 에천트(sub etchant) 및 He, Ne, Ar과 같은 플라즈마 안정화 가스를 혼합하여 형성한다. BPSG 산화막 식각 시 Ta2O5막은 위에서 언급된 가스로는 거의 식각되지 않는 높은 식각 선택비를 갖고 있으므로, 기존의 산화막 식각 장비로도 용이하게 식각 공정을 수행할 수 있다.At this time, the oxide etching condition is a fluorine-carbon (C: carbon) gas, preferably CF 4 + such as CF 4 , CHF 3 , C 2 F 6 , C 3 F 8 , C 4 F 8 In the main etchant of CHF 3 , sub etchants such as CH 3 F, H 2 , C 2 H 2 , CH 2 F 2 , C 2 HF 5 and the like and He, Ne, Ar It is formed by mixing the plasma stabilization gas. When etching the BPSG oxide, the Ta 2 O 5 film has a high etching selectivity that is hardly etched by the above-mentioned gas, so that the etching process may be easily performed even with the existing oxide etching equipment.
부연하면, 산화막 식각 시 거의 식각이 되지 않는 Ta2O5막을 식각정지층으로 사용할 경우, CF4 + CHF3 와 같은 전형적인 산화막 식각 가스인 낮은 폴리머 유발 가스로도 자기정렬콘택 형성을 위한 식각 형성이 가능하다. 즉, 산화막인 BPSG 또는 SiO2는 CF4 + CHF3와 반응하여 SiF4와 같은 휘발성 물질을 생성함으로써 식각이 진행되나, Ta2O5막은 CF4 + CHF3와 같은 플로린-카본 계 가스와 결합하여 휘발성 물질을 생성할 수 없다. 따라서, 산화막 식각 시, Ta2O5막에 대한 식각 선택비를 30 이상 용이하게 확보할 수 있어, 즉, 식각정지층으로서의 역할을 충실히 수행할 수 있어 공정 재현성이 우수한 콘택홀을 형성할 수 있다.In other words, when a Ta 2 O 5 film which is hardly etched during oxide etching is used as an etch stop layer, even a low polymer-induced gas, which is a typical oxide etching gas such as CF 4 + CHF 3 , can form an etch to form a self-aligned contact. Do. That is, BPSG or SiO 2 , which is an oxide film, is etched by reacting with CF 4 + CHF 3 to produce a volatile substance such as SiF 4 , but the Ta 2 O 5 film is combined with a fluorine-carbon gas such as CF 4 + CHF 3. Cannot produce volatiles. Therefore, when etching the oxide layer, the etching selectivity for the Ta 2 O 5 film can be easily secured to 30 or more, that is, the role as an etch stop layer can be faithfully formed, thereby forming a contact hole having excellent process reproducibility. .
계속해서 도 4는 노출된 Ta2O5막(5)을 Cl2 가스 분위기에서 식각하여 콘택홀 (7)을 형성하고, 레지스트 패턴(7)을 제거한 상태이다.4, the exposed Ta 2 O 5 film 5 is etched in a Cl 2 gas atmosphere to form a
본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention is not limited to the above-described embodiments and the accompanying drawings, and various permutations, modifications, and changes can be made without departing from the spirit of the present invention. It will be obvious to those who have it.
콘택홀 형성 공정에 있어서, 종래의 질화막을 사용하는 SAC 공정이 지나치게 많은 폴리머 형성 가스를 사용하게 되는데, 본 발명은 산화막에 대한 식각 선택비를 높은 Ta2O5막을 식각정지층으로 사용하여, 폴리머 발생이 적은 가스로 산화막 식각을 실시할 수 있도록 하는 것이다. 따라서 현재 64M DRAM의 4 세대 이후부터 반드시 필요하게 되리라 생각되는 SAC 공정을 조기에 확보함으로써 소자 개발을 앞당길 수 있다. 또한, 본 발명과 같이 Ta2O5막을 이용할 경우 산화막 식각 시, 식각 메카니즘이 다른 Ta2O5막에 대한 높은 식각 선택비 확보가 용이하기 때문에 기존의 장비로도 SAC 공정의 구현이 가능하므로, SAC 공정 전용 장비의 구매가 불필요하여 원가 절감에 기여할 수 있다.In the contact hole forming process, a conventional SAC process using a nitride film uses too much polymer forming gas. The present invention uses a Ta 2 O 5 film having a high etching selectivity to an oxide film as an etch stop layer. The oxide film can be etched using a gas that is less likely to be generated. As a result, early development of the SAC process, which is expected to be necessary since the fourth generation of 64M DRAM, can accelerate device development. In addition, when the Ta 2 O 5 film is used as described in the present invention, it is easy to secure a high etching selectivity with respect to Ta 2 O 5 film having different etching mechanisms when the oxide is etched. It can contribute to cost savings because it is unnecessary to purchase equipment exclusively for SAC process.
도 1 내지 도 4는 본 발명의 일실시예에 따라 비트라인 SAC 공정에서 식각정지층을 탄탈늄산화막으로 사용한 것을 보여주는 공정 단면도.1 to 4 are cross-sectional views illustrating an etching stop layer as a tantalum oxide film in a bit line SAC process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 폴리실리콘막1: silicon substrate 2: polysilicon film
3 : 하드 마스크를 위한 산화막 4 : 산화막 스페이서3: oxide film for hard mask 4: oxide film spacer
5 : 탄탈늄산화막(Ta2O5) 6 : BPSG 산화막5: tantalum oxide film (Ta 2 O 5 ) 6: BPSG oxide film
7 : 레지스트 패턴 8 : 콘택홀7: resist pattern 8: contact hole
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029023A KR100458087B1 (en) | 1997-06-30 | 1997-06-30 | Method for fabricating semiconductor device to etch oxide layer by gas including small quantity of polymer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029023A KR100458087B1 (en) | 1997-06-30 | 1997-06-30 | Method for fabricating semiconductor device to etch oxide layer by gas including small quantity of polymer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990004863A KR19990004863A (en) | 1999-01-25 |
| KR100458087B1 true KR100458087B1 (en) | 2005-02-23 |
Family
ID=37376872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970029023A KR100458087B1 (en) | 1997-06-30 | 1997-06-30 | Method for fabricating semiconductor device to etch oxide layer by gas including small quantity of polymer |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100458087B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100338099B1 (en) * | 1999-06-29 | 2002-05-24 | 박종섭 | Method of manufacturing a semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122641A (en) * | 1993-10-22 | 1995-05-12 | Sony Corp | Method for making self-aligned contact hole in semiconductor device |
| JPH07230968A (en) * | 1994-02-17 | 1995-08-29 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| KR950025869A (en) * | 1994-02-07 | 1995-09-18 | 김주용 | How to Form Contact Holes |
| KR100255158B1 (en) * | 1993-11-23 | 2000-05-01 | 김영환 | Forming a contact hole in a semiconductor device |
-
1997
- 1997-06-30 KR KR1019970029023A patent/KR100458087B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122641A (en) * | 1993-10-22 | 1995-05-12 | Sony Corp | Method for making self-aligned contact hole in semiconductor device |
| KR100255158B1 (en) * | 1993-11-23 | 2000-05-01 | 김영환 | Forming a contact hole in a semiconductor device |
| KR950025869A (en) * | 1994-02-07 | 1995-09-18 | 김주용 | How to Form Contact Holes |
| JPH07230968A (en) * | 1994-02-17 | 1995-08-29 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990004863A (en) | 1999-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7105442B2 (en) | Ashable layers for reducing critical dimensions of integrated circuit features | |
| KR100458360B1 (en) | Etching high aspect contact holes in solid state devices | |
| JPH11186225A (en) | Formation of tapered contact hole, formation of tapered polysilicon plug and taepred polysilicon plug | |
| US6432816B2 (en) | Method for fabricating semiconductor device | |
| US20110248385A1 (en) | Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device | |
| KR100244793B1 (en) | Method of forming contact hole in semiconductor device | |
| KR100458087B1 (en) | Method for fabricating semiconductor device to etch oxide layer by gas including small quantity of polymer | |
| KR20030000592A (en) | method for manufacturing of semiconductor device with STI/DTI structure | |
| KR0139072B1 (en) | Method of fabricating semiconductor device having step of forming play in contact hole | |
| KR100430688B1 (en) | Method of forming contact hole of semiconductor device | |
| KR100256809B1 (en) | Method for forming contact hole in semiconductor device | |
| KR100587039B1 (en) | Manufacturing method for contact hole in semiconductor device | |
| JPH07297174A (en) | Manufacture of semiconductor device | |
| KR100430690B1 (en) | Contact Forming Method of Semiconductor Device | |
| KR100634267B1 (en) | Method for forming of device isolation region in a semiconductor device | |
| KR100223869B1 (en) | Manufacturing method of semiconductor device | |
| KR0147771B1 (en) | Method for forming poly side gate of semiconductor device | |
| KR100772699B1 (en) | Method for forming semiconductor device | |
| US6277734B1 (en) | Semiconductor device fabrication method | |
| KR20010036161A (en) | Method for forming a contact hole of a self-aligned contact using a hard mask | |
| KR100223825B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| KR100504551B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR19980025631A (en) | Manufacturing Method of Semiconductor Device | |
| KR0140730B1 (en) | Method of forming contact in semiconductor device | |
| KR100524812B1 (en) | A forming method of bitline using ArF photolithography |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |