KR0177343B1 - Apparatus of semiconductor and method of manufacturing thereof - Google Patents
Apparatus of semiconductor and method of manufacturing thereof Download PDFInfo
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- KR0177343B1 KR0177343B1 KR1019960012580A KR19960012580A KR0177343B1 KR 0177343 B1 KR0177343 B1 KR 0177343B1 KR 1019960012580 A KR1019960012580 A KR 1019960012580A KR 19960012580 A KR19960012580 A KR 19960012580A KR 0177343 B1 KR0177343 B1 KR 0177343B1
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- silicide gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 89
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 38
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000001020 plasma etching Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 24
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 23
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 23
- 230000010354 integration Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
반도체 메모리 셀의 제조 방법에 있어서, 등방성 플라즈마 식각법을 이용하여 메모리 셀의 실리사이드 게이트를 위한 텅스텐 실리사이드 층과 다결정 실리콘층을 리세스 식각하여 실리사이드 게이트의 크기를 실리사이드 게이트를 형성하기 위한 산화층의 마스크의 크기보다 작거나 동일하게 형성함으로써 실리사이드 게이트와 DC 콘택부사이의 층간 절연막의 마진을 충분히 확보할 수 있다. 따라서, 실리사이드 게이트와 비트 라인의 간섭이 방지되어 메모리 셀의 품질이 향상되고, 메모리 셀의 고집적화가 가능하게 된다.A method of fabricating a semiconductor memory cell, comprising etching a tungsten silicide layer and a polycrystalline silicon layer for a silicide gate of a memory cell by isotropic plasma etching to form a silicide gate having a silicide gate size. By forming smaller than or equal to the size, the margin of the interlayer insulating film between the silicide gate and the DC contact portion can be sufficiently secured. Therefore, interference between the silicide gate and the bit line is prevented, thereby improving the quality of the memory cell and enabling high integration of the memory cell.
Description
제1도 (a)내지 (d)는 종래의 반도체 장치의 제조 방법을 나타낸 단면 공정도.1A to 1D are cross-sectional process diagrams illustrating a conventional method for manufacturing a semiconductor device.
제2도는 본 발명에 의한 반도체 장치의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a semiconductor device according to the present invention.
제3도 (a)내지 (c)는 본 발명에 의한 반도체 장치의 제조 방법을 나타낸 단면 공정도.3 (a) to 3 (c) are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 3,9 : 산화층1: Substrate 3,9: Oxide Layer
5 : 다결정 실리콘 층 7 : 텅스텐 실리사이드 층5: polycrystalline silicon layer 7: tungsten silicide layer
11 : 감광막 13 : 층간 절연막11: photosensitive film 13: interlayer insulating film
15 : DC(direct contact) 콘택부 17 : 다결정 실리콘 층15 DC contact portion 17 polycrystalline silicon layer
21 : 기판 23,29 : 텅스텐 실리사이드 층21 substrate 23,29 tungsten silicide layer
25 : 다결정 실리콘 층 27 : 텅스텐 실리사이드 층25 polycrystalline silicon layer 27 tungsten silicide layer
33 : 층간 절연막 35 : DC 콘택부33: interlayer insulating film 35: DC contact portion
37 : 도전층37: conductive layer
본 발명은 반도체 장치에 관한 것으로, 더욱 상세하게는 메모리 셀의 실리사이드 게이트와 DC(direct contact) 콘택부 사이의 층간 절연막 마진을 확보하도록 실리사이드 게이트를 위한 텅스텐 실리사이드 층과 다결정 실리콘 층을 리세스(recess) 식각한 반도체 장치 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to recesses a tungsten silicide layer and a polycrystalline silicon layer for the silicide gate to ensure an interlayer dielectric margin between the silicide gate and the direct contact (DC) contact portion of the memory cell. ) An etched semiconductor device and a method of manufacturing the same.
일반적으로 반도체 메모리 셀의 드레인은 DC(direct contact) 콘택부에서 비트 라인에 전기적으로 접속되고, 게이트는 워드 라인에 전기적으로 접속되어 있다.In general, the drain of the semiconductor memory cell is electrically connected to the bit line at the direct contact (DC) contact portion, and the gate is electrically connected to the word line.
이러한 구조의 반도체 메모리 소자가 고집적화되면, 메모리 셀내의 게이트와 DC(direct contact) 콘택부의 사이의 층간 절연막 마진이 감소하게 되고, 게이트의 신호 전달 속도가 느리게 된다.When the semiconductor memory device having such a structure is highly integrated, the interlayer insulating film margin between the gate in the memory cell and the direct contact (DC) contact portion is reduced, and the signal transmission speed of the gate is slowed.
상기 게이트의 신호 전달 속도를 빠르게 하기 위한 방안의 하나로서 게이트를 다결정 실리콘 층과 텅스텐 실리사이드 층으로 이루어진 복합 구조의 실리사이드 게이트로 구성하는 방안이 제안되었다.As one of the methods for increasing the signal transmission speed of the gate, a method of configuring the gate as a silicide gate having a complex structure composed of a polycrystalline silicon layer and a tungsten silicide layer has been proposed.
제1도 (a) 내지 (d)는 종래의 반도체 장치의 제조 방법을 나타낸 단면 공정도이다.1A to 1D are cross-sectional process diagrams showing a conventional method for manufacturing a semiconductor device.
제1도 (a)를 참조하면, 먼저, 기판(1), 예를 들어 단결정 실리콘 기판의 전면상에 100Å의 얇은 두께로 이루어진 게이트 절연막용 산화층(3)과, 1000Å의 두께로 이루어진 다결정 실리콘 층(5)과, 1500Å의 두께로 이루어진 텅스텐 실리사이드 층(7) 및 비교적 두꺼운 두께의 산화층(9)을 순차적으로 형성한다.Referring to FIG. 1 (a), first, an oxide layer 3 for a gate insulating film 3 on the front surface of a substrate 1, for example, a single crystal silicon substrate, and a polycrystalline silicon layer having a thickness of 1000 ms is formed. (5), and a tungsten silicide layer 7 having a thickness of 1500 kPa and an oxide layer 9 having a relatively thick thickness are sequentially formed.
계속하여, 통상적인 사진 공정을 이용하여 상기 산화층(9)상에 게이트를 형성하기 위한 감광막(11)의 패턴을 각각 형성한다.Subsequently, a pattern of the photoresist film 11 for forming a gate is formed on the oxide layer 9 using a conventional photographic process.
제1도 (b)를 참조하면, 상기 감광막(11)의 패턴을 마스크로 이용하여 산화층(9)을 선택적으로 식각하여 게이트를 형성하기 위한 산화층(9)의 패턴을 형성하고나서, 감광막(11)의 패턴을 제거한다.Referring to FIG. 1B, the pattern of the oxide layer 9 is formed by selectively etching the oxide layer 9 using the pattern of the photosensitive layer 11 as a mask, and then forming the pattern of the photosensitive layer 11. ) To remove the pattern.
제1도 (c)를 참조하면, 상기 산화층(9)의 패턴을 마스크로 이용하여 기판(1)에 소정의 도전형의 이온을 이온 주입하여 기판(1)의 정해진 영역에 메모리셀의 드레인(D)과 소오스(S)를 형성한다.Referring to FIG. 1C, by using the pattern of the oxide layer 9 as a mask, ion of a predetermined conductivity type is implanted into the substrate 1 to drain the memory cell in a predetermined region of the substrate 1. D) and a source (S) are formed.
여기서, 산화층(9)은 산화층(3)에 대한 높은 선택비를 가지며, 소오스(S)와 드레인(D)의 이온 주입시 메모리 셀의 채널 영역의 상측에 위치하는 텅스텐 실리사이드 층(7)의 손상 및 파티클의 발생을 줄여주기 위한 하드 마스크(hard mask)로서 이용된다.Here, the oxide layer 9 has a high selectivity to the oxide layer 3 and damages the tungsten silicide layer 7 located above the channel region of the memory cell during ion implantation of the source S and the drain D. And a hard mask for reducing the generation of particles.
이어서, 상기 산화층(9)의 패턴을 마스크로 이용하여 텅스텐 실리사이드 층(7)과 다결정 실리콘 층(5)을 순차적으로 식각한다.Subsequently, the tungsten silicide layer 7 and the polycrystalline silicon layer 5 are sequentially etched using the pattern of the oxide layer 9 as a mask.
이때, 텅스텐 실리사이드 층(7)과 다결정 실리콘 층(5)의 식각 특성이 포지티브(positive) 특성을 나타낸다. 즉, 식각되고 남은 텅스텐 실리사이드 층(7)과 다결정 실리콘 층(5)의 크기가 상기 산화층(9)의 패턴의 크기와 같거나 크게 된다.At this time, the etching characteristics of the tungsten silicide layer 7 and the polycrystalline silicon layer 5 exhibit positive characteristics. That is, the size of the etched remaining tungsten silicide layer 7 and the polycrystalline silicon layer 5 is equal to or larger than the size of the pattern of the oxide layer 9.
제1도(d)를 참조하면, 상기와 같은 구조가 형성된 기판(1)의 전면상에 산화층으로 이루어진 층간 절연막(13)을 형성한 후 통상적인 사진 공정을 이용하여 드레인(D)의 영역을 개방하기 위한 DC(direct contact) 콘택부(15) 형성한다. 이어서, 상기 층간 절연막(13)의 전면상에 비트 라인을 위한 도핑된 다결정 실리콘 층(17)을 적층하여 드레인(D)에 전기적으로 연결하고나서 다결정 실리콘 층(17)을 비트 라인의 패턴으로 형성한다.Referring to FIG. 1 (d), an interlayer insulating film 13 made of an oxide layer is formed on the entire surface of the substrate 1 having the above structure, and then the region of the drain D is formed by using a conventional photographic process. DC (direct contact) contact portion 15 for opening is formed. Subsequently, a doped polycrystalline silicon layer 17 for the bit line is laminated on the entire surface of the interlayer insulating layer 13 and electrically connected to the drain D, and then the polycrystalline silicon layer 17 is formed in the pattern of the bit line. do.
따라서, 이와 같이 형성된 메모리 셀에서는 실리사이드 게이트를 위한 텅스텐 실리사이드 층(7)과 다결정 실리콘 층(5)으로 이루어진 포지티브 에칭되어 실리사이드 게이트의 하측부와 DC(direct contact) 콘택부 사이의 층간 절연막의 폭이 마진이 실리사이드 게이트의 상측부와 DC(direct contact) 콘택부 사이의 층간 절연막의 폭보다 좁아지게 된다. 그러므로, 실리사이드 게이트의 하측부와 DC(direct contact) 콘택부 사이의 층간 절연막의 마진이 충분히 확보되지 않아 메모리 셀을 더 이상 고집적화할 수 없을 뿐 아니라 실리사이드 게이트와 비트 라인이 서로 간섭하여 메모리 셀의 품질이 악화된다.Therefore, in the memory cell formed as described above, a positive etch consisting of a tungsten silicide layer 7 and a polycrystalline silicon layer 5 for the silicide gate is performed so that the width of the interlayer insulating film between the lower side of the silicide gate and the direct contact (DC) contact portion is The margin becomes narrower than the width of the interlayer insulating film between the upper portion of the silicide gate and the direct contact (DC) contact portion. Therefore, the margin of the interlayer insulating film between the lower side of the silicide gate and the direct contact (DC) contact portion is not sufficiently secured, so that the memory cell can no longer be highly integrated, and the silicide gate and the bit line interfere with each other, so that the quality of the memory cell This gets worse.
따라서, 본 발명의 목적은 메모리 셀의 실리사이드 게이트와 DC 콘택부 사이의 층간 절연막의 마진을 충분히 확보할 수 있도록 한 반도체 장치 및 그 제조 방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which are capable of ensuring a sufficient margin of an interlayer insulating film between a silicide gate of a memory cell and a DC contact portion.
이와 같은 목적을 달성하기 위한 본 발명은 메모리 셀의 실리사이드 게이트를 위한 텅스텐 실리사이드 층과 다결정 실리콘 층을 리세스 식각하여 상기 실리사이드 게이트와 DC 콘택부 사이의 층간 절연막의 마진을 충분히 확보함으로써 메모리 셀의 품질을 향상시킬 수 있을 뿐 아니라 고집적화시킬 수 있는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of etching a tungsten silicide layer and a polycrystalline silicon layer for a silicide gate of a memory cell to sufficiently secure a margin of an interlayer insulating layer between the silicide gate and the DC contact. It can be improved as well as characterized by high integration.
이하, 본 발명에 의한 반도체 장치 및 그 제조 방법을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 의한 반도체 장치의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a semiconductor device according to the present invention.
본 발명의 반도체 장치는 기판(21)에 소오스(S)와 드레인(D)이 각각 형성되어 있고, 소오스(S)와 드레인(D) 사이의 기판(21)의 영역상에 게이트 절연막용 산화층(23)과, 실리사이드 게이트를 위한 다결정 실리콘 층(25) 및 텅스텐 실리사이드 층(27)이 순차적으로 형성되어 있으며, 텅스텐 실리사이드 층(27)상에 실리사이드 게이트를 형성하기 위한 산화층(29)이 형성되어 있는 한편, 층간 절연막(33)이 상기 각부를 덮도록 형성되어 있고, 비트 라인용 도전층(37)이 층간 절연막(33)의 DC 콘택부(35)룰 거쳐 상기 드레인(D)에 전기적으로 연결됨과 아울러 상기 층간 절연막(33)의 표면상에 형성되는 구조로 이루어져 있다.In the semiconductor device of the present invention, the source S and the drain D are formed on the substrate 21, respectively, and the oxide layer for the gate insulating film is formed on the region of the substrate 21 between the source S and the drain D. 23 and a polycrystalline silicon layer 25 and a tungsten silicide layer 27 for the silicide gate are sequentially formed, and an oxide layer 29 for forming the silicide gate is formed on the tungsten silicide layer 27. On the other hand, the interlayer insulating film 33 is formed to cover the respective portions, the bit line conductive layer 37 is electrically connected to the drain (D) via the DC contact portion 35 of the interlayer insulating film 33 and In addition, it has a structure formed on the surface of the interlayer insulating film 33.
여기서, 상기 산화층(29)의 크기가 다결정 실리콘 층(25) 및 텅스텐 실리사이드 층(27)의 크기보다 작거나 같게 형성되어 있다.In this case, the oxide layer 29 has a size smaller than or equal to that of the polycrystalline silicon layer 25 and the tungsten silicide layer 27.
따라서, 상기 DC 콘택부(35)내에 있는 도전층(37)과 실리사이드 게이트의 하측부 사이의 층간 절연막(33)의 폭이 상기 DC 콘택부(35)내에 있는 도전층(37)과 실리사이드 게이트의 상측부 사이의 층간 절연막(33)의 폭보다 넓게 된다. 그러므로, 실리사이드 게이트의 하측부와 DC 콘택부사이의 층간 절연막(33)의 마진이 충분히 확보되어 메모리 셀의 고집적화가 가능하게 되고, 비트 라인용 다결정 실리콘 층(37)과 실리사이드 게이트의 간섭이 방지되어 메모리 셀의 품질이 더욱 향상된다.Thus, the width of the interlayer insulating film 33 between the conductive layer 37 in the DC contact portion 35 and the lower side of the silicide gate is greater than that of the conductive layer 37 and silicide gate in the DC contact portion 35. It becomes wider than the width of the interlayer insulating film 33 between upper portions. Therefore, the margin of the interlayer insulating film 33 between the lower side of the silicide gate and the DC contact portion is sufficiently secured to enable high integration of the memory cell, and the interference between the polycrystalline silicon layer 37 for the bit line and the silicide gate is prevented. The quality of the cell is further improved.
제3도 (a) 내지 (c)는 본 발명에 의한 반도체 장치의 제조 방법을 나타낸 단면 공정도이다.3 (a) to 3 (c) are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.
제3도 (a)를 참조하면, 제1도 (a)와 (b)에 도시된 바와 같은 공정을 동일하게 실시하여 기판(21), 예를 들어 단결정 실리콘 기판에 메모리 셀의 드레인(D)과 소오스(S)이 형성되고, 소오스(S)와 드레인(D) 사이의 기판(21)의 영역상에 게이트 절연막용 산화층(23)과, 실리사이드 게이트를 위한 다결정 실리콘 층(25) 및 텅스텐 실리사이드 층(27)이 형성되며, 텅스텐 실리사이드 층(27)상에 산화층(29)이 형성되도록 한다.Referring to FIG. 3 (a), the drain D of the memory cell is placed on the substrate 21, for example, a single crystal silicon substrate, by carrying out the same process as shown in FIGS. And a source S, and an oxide layer 23 for the gate insulating film, a polycrystalline silicon layer 25 and a tungsten silicide for the silicide gate, on the region of the substrate 21 between the source S and the drain D. Layer 27 is formed, allowing oxide layer 29 to be formed on tungsten silicide layer 27.
여기서, 산화층(29)은 산화층(23)에 대한 높은 선택비를 가지며, 소오스(S)와 드레인(D)의 이온 주입시 게이트용 텅스텐 실리사이드 층(27)의 손상 및 파티클의 발생을 줄여주기 위한 하드 마스크(hard mask)로서 이용된다.Here, the oxide layer 29 has a high selectivity with respect to the oxide layer 23, and to reduce damage and generation of particles of the gate tungsten silicide layer 27 during ion implantation of the source S and the drain D. It is used as a hard mask.
제3도 (b)를 참조하면, 상기 산화층(29)의 패턴을 마스크로 이용하여 텅스텐 실리사이드 층(27)과 다결정 실리콘 층(25)을 플라즈마 에칭한다,Referring to FIG. 3B, the tungsten silicide layer 27 and the polycrystalline silicon layer 25 are plasma etched using the pattern of the oxide layer 29 as a mask.
이때, 텅스텐 실리사이드 층(27)과 다결정 실리콘 층(25)이 등방성 에칭되어 리세스(recess) 에칭 특성을 나타낸다. 즉, 식각되고 남은 텅스텐 실리사이드 층(27)과 다결정 실리콘 층(25)의 크기가 상기 산화층(29)의 패턴의 크기와 같거나 작게 된다.At this time, the tungsten silicide layer 27 and the polycrystalline silicon layer 25 are isotropically etched to exhibit recess etching characteristics. That is, the size of the etched remaining tungsten silicide layer 27 and the polycrystalline silicon layer 25 is equal to or smaller than the size of the pattern of the oxide layer 29.
여기서, 상기 리세스 식각 특성을 위한 조건으로는 SF6, CHF₃,CF₄,NF₃,O₂와 같은 반응 가스들이 사용되고, RF 파워와 압력 및 자장이 소정의 값으로 유지된다.Here, reaction conditions such as SF6, CHF 3, CF₄, NF 3, and O 2 are used as conditions for the recess etch characteristics, and RF power, pressure, and magnetic field are maintained at predetermined values.
제3도 (c)를 참조하면, 상기와 같은 구조가 형성된 기판(21)의 전면상에 산화층으로 이루어진 층간 절연막(33)을 형성한 후 통상적인 사진 공정을 이용하여 드레인(D)의 영역을 개방하기 위한 DC(direct contact) 콘택부(35)를 형성한다.Referring to FIG. 3C, after forming the interlayer insulating film 33 made of an oxide layer on the entire surface of the substrate 21 having the above structure, the region of the drain D is formed by using a conventional photographic process. A direct contact (DC) contact 35 for opening is formed.
이어서, 상기 층간 절연막(33)의 전면상에 비트 라인을 위한 도전층(37), 예를 들어 도핑된 다결정 실리콘 층을 적층하여 드레인(D)에 전기적으로 연결하고나서 도전층(37)을 비트 라인의 패턴으로 형성한다.Subsequently, a conductive layer 37 for a bit line, for example, a doped polycrystalline silicon layer is laminated on the entire surface of the interlayer insulating film 33 and electrically connected to the drain D, and then the conductive layer 37 is bit Form in a pattern of lines.
따라서, 상기 DC 콘택부(35)내에 있는 도전층(37)과 실리사이드 게이트의 하측부 사이의 층간 절연막(33)의 폭이 상기 DC 콘택부(35)내에 있는 도전층(37)과 실리사이드 게이트의 상측부 사이의 층간 절연막(33)의 폭보다 넓게 된다. 그러므로, 상기 DC 콘택부(35)내에 있는 도전층(37)과 실리사이드 게이트의 하측부 사이의 층간 절연막(33)의 마진이 충분히 확보되어 메모리 셀의 고집적화가 가능하게 되고, 비트 라인용 다결정 실리콘 층(37)과 실리사이드 게이트의 간섭이 방지되어 메모리 셀의 품질이 더욱 향상된다.Thus, the width of the interlayer insulating film 33 between the conductive layer 37 in the DC contact portion 35 and the lower side of the silicide gate is greater than that of the conductive layer 37 and silicide gate in the DC contact portion 35. It becomes wider than the width of the interlayer insulating film 33 between upper portions. Therefore, the margin of the interlayer insulating film 33 between the conductive layer 37 in the DC contact portion 35 and the lower side of the silicide gate is sufficiently secured to enable high integration of the memory cell, and thus the polycrystalline silicon layer for the bit line. Interference between the 37 and the silicide gate is prevented, and the quality of the memory cell is further improved.
이상에서 살펴본 바와 같이, 본 발명은 등방성 플라즈마 식각법을 이용하여 메모리 셀의 실리사이드 게이트를 위한 텅스텐 실리사이드 층과 다결정 실리콘층을 리세스 식각하여 실리사이드 게이트의 크기를 실리사이드 게이트를 형성하기 위한 산화층의 마스크의 크기보다 작거나 동일하게 형성함으로써 실리사이드 게이트와 DC 콘택부사이의 층간 절연막의 마진을 충분히 확보할 수 있다. 따라서, 실리사이드 게이트와 비트 라인의 간섭이 방지되어 메모리 셀의 품질이 향상되고 메모리 셀의 고집적화가 가능하게 된다.As described above, the present invention provides a method of masking an oxide layer for forming silicide gates by recess-etching a tungsten silicide layer and a polycrystalline silicon layer for silicide gates of a memory cell using an isotropic plasma etching method. By forming smaller than or equal to the size, the margin of the interlayer insulating film between the silicide gate and the DC contact portion can be sufficiently secured. Therefore, interference between the silicide gate and the bit line is prevented, thereby improving the quality of the memory cell and enabling high integration of the memory cell.
Claims (4)
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