KR100314151B1 - A method for forming a transistor of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a transistor of a semiconductor device,

Forming an oxide film and a polysilicon stack structure on the semiconductor substrate, patterning the stack structure by a photolithography process using a gate electrode mask, and then forming an insulating film spacer on the sidewall of the patterned stack structure and the ion on the semiconductor substrate Implanting to form an impurity junction region, and then forming the layered structure and the planarized internal oxide film on the entire surface, removing the layered structure, and then sequentially depositing alumina as a gate insulating film and a tungsten / tungsten nitride film for the gate electrode on the entire surface. Forming a hard mask on top of the tungsten / tungsten nitride layer between the insulating layer spacers and preventing damage to the metal gate electrode during the subsequent etching process. And characteristics of semiconductor devices It is a technology that enables high integration of semiconductor devices by improving reliability and enabling high speed semiconductor devices.

Description

A method for forming a transistor of semiconductor device

The present invention relates to a method for forming a transistor of a semiconductor device, and more particularly, to a technique for preventing a damage of a gate electrode by an etching process performed after the forming process of the metal gate electrode.

As semiconductor devices become more integrated, thermal processes are minimized and impurities are thinner, resulting in worse current or resistance characteristics.

In order to improve this problem, the overall impurity concentration of a substrate or a transistor is increasing.

When the transistor is operated, a large electric field is generated in the vicinity of the drain, and a hot carrier is formed by the electric field, which causes a long channel length of the transistor and between the source and the drain. The punch through effect causes the threshold voltage to drop, resulting in breakdown even at low voltages.

On the other hand, when a strong electric field is formed in the field region near the oxide film due to the gate voltage, the drain voltage, or the substrate bias applied by the MOS transistor, the hot carriers move a lot of free carriers. You have energy and these free carriers are called hot carriers. In addition, a case in which the hot carrier is injected into the oxide film over the energy barrier between the oxide film and the silicon is called a hot carrier effect.

In order to prevent the deterioration of transistor characteristics due to the above hot carriers, it is now L.D.D. By forming and using a lightly doped drain (LDD) structure, the electric field near the drain is reduced to improve the reliability of the transistor.

However, in the transistor where the source and the drain are determined in consideration of the operation of the circuit, the LDD structure increases the source-side resistance so that the current-voltage characteristic of the transistor is degraded.

Although not shown, the transistor of the LDD structure according to the prior art will be described.

First, a device isolation region defining an active region on a semiconductor substrate is defined, and a gate insulating film and a conductor for a gate electrode are deposited on the entire surface including the active region and patterned to form a gate electrode.

A low concentration source / drain junction region is formed by implanting a low concentration of impurities into the semiconductor substrate using the gate electrode as a mask.

A transistor having an LDD structure is formed by forming an insulating film spacer on the sidewall of the gate electrode and injecting a high concentration of impurities into the semiconductor substrate using the insulating film spacer and the gate electrode as a mask to form a high concentration source / drain junction region.

The prior art deteriorates device characteristics due to the high Rs value of the word line in the fabrication of DRAM devices having a degine rule of 0.13 μm or less.

Therefore, in recent years, in order to lower the Rs value of a word line when manufacturing a DRAM having a design rule of 0.13 μm or less, a lamination structure of silicide or metal-polysilicon was formed, and an insulating film spacer was formed on the sidewall thereof to have an LDD structure.

1 is a cross-sectional view illustrating a method of forming a gate electrode of a semiconductor device according to the related art.

First, polysilicon (not shown) is formed on the semiconductor substrate 11 and patterned by a photolithography process using a first gate electrode mask.

An insulating film spacer 13 is formed on the sidewalls of the polysilicon. In this case, the insulating film spacer 13 is formed of a nitride film, but a nitride film is formed on the entire surface by a predetermined thickness and is formed by anisotropic etching.

Next, an internal oxide film 15 is formed on the entire surface and etched and planarized by a planarization etching process in which the polysilicon is exposed.

The polysilicon is removed by using an etching selectivity difference between the insulating layer spacer 13 and the internal oxide layer 15 and the polysilicon.

A gate insulating film is formed on the entire surface, and an alumina (Al ₂ O ₃ ) 17 is formed on the entire surface.

In addition, a stacked structure of a tungsten / tungsten nitride film 19 serving as a gate electrode metal layer is formed on the alumina 17.

The tungsten / tungsten nitride film 19 and the alumina 17 are patterned by a photolithography process using a second gate electrode mask to form a metal gate electrode. (Figure 1)

In the prior art as described above, the second gate electrode mask is formed to be larger than the first gate electrode mask, and is not applicable to a cell design capable of minimizing the cell size in a subsequent SAC process. There is a problem that is not applicable.

In order to solve the above problems of the prior art, the LDD structure transistor can be applied to a design rule of 0.13 µm or less by forming a mask insulating film on the metal gate electrode to facilitate the subsequent SAC process. It is an object of the present invention to provide a method for forming a transistor of a semiconductor device that can form a and thereby enable a high integration of the semiconductor device.

1 is a cross-sectional view showing a transistor forming method of a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11,21 semiconductor substrate 13,29 insulating film spacer

15,31: internal oxide film 17,33: alumina

19,35 tungsten / tungsten nitride film 23 oxide film

25 polysilicon 27 photosensitive film pattern

37: hard mask, nitride film, silicon rich nitride film

In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,

Forming an oxide film and a polysilicon laminated structure on the frequency substrate,

Patterning the stacked structure by a photolithography process using a gate electrode mask;

Forming an insulating film spacer on sidewalls of the patterned stacked structure;

Forming an impurity junction region by implanting impurities into the semiconductor substrate;

Forming the laminated structure and the planarized internal oxide film on the entire surface thereof;

Removing the laminated structure and continuously forming alumina as a gate insulating film and a tungsten / tungsten nitride film for a gate electrode on the entire surface thereof;

Etching back to the tungsten / tungsten nitride film between the insulating film spacers;

And forming a hard mask on the tungsten / tungsten nitride film between the insulating film spacers.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.

First, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 21.

In addition, a thin oxide film 23 is formed on the semiconductor substrate 21. In this case, the oxide layer 23 is to prevent damage to the semiconductor substrate 21 during the subsequent etching process.

Next, polysilicon 25 is formed on the oxide film 23 at a predetermined thickness.

The photoresist pattern 27 is formed on the polysilicon 25. In this case, the photoresist pattern 27 is formed by an exposure and development process using a gate electrode mask (not shown). (FIG. 2A)

Then, the polysilicon 25 is etched using the photoresist pattern 27 as a mask to form the polysilicon 25 pattern, leaving only the portion where the gate electrode is to be formed.

Then, the photosensitive film pattern 27 is removed. (FIG. 2B)

Next, an insulating film spacer 29 is formed on the sidewalls of the polysilicon 25 pattern.

In this case, the insulating film spacer 29 is formed by forming an insulating film spacer 29 on the entire surface and anisotropically etching it.

Here, the anisotropic etching process is performed by a plasma etching process using a C-H-F-based gas.

Next, an impurity is implanted into the semiconductor substrate 21 and a drive-in process is performed to form a source / drain junction region (not shown).

Then, the internal oxide layer 31 is formed on the entire surface and the internal oxide layer 31 is planarized and etched to expose the polysilicon 25 pattern. In this case, the planarization etching process is performed by a CMP process.

Next, the exposed polysilicon 25 pattern is removed to expose a region where a metal gate electrode is to be formed.

In this case, the polysilicon 25 may be removed by a wet or dry method.

Then, all of the oxide films 23 are removed by removing the oxide film 23 exposed in the region where the metal gate electrode is to be formed. (FIG. 2C)

Then, alumina 33 to be used as a gate insulating film with a predetermined thickness is formed on the entire surface.

Subsequently, a tungsten / tungsten nitride film 35, which is a metal layer for gate electrodes, is formed on the alumina 33 continuously. (FIG. 2D)

Then, the tungsten / tungsten nitride film 35 is etched back using the difference in etching selectivity between the tungsten / tungsten nitride film 35 and the alumina 33, thereby forming a portion of the upper tungsten / tungsten nitride film between the insulating film spacers 29. Etch up to (35).

In this case, the etch back process is performed by a plasma etching process using an F-containing gas.

The F-containing gas may be a gas such as NF ₃ or SF ₆ , and may be added by adding argon or helium gas, which is an inert gas, in order to improve the stability of the plasma etching process.

Next, an upper portion of the tungsten / tungsten nitride film 35 is buried in the nitride film 37 to form a hard mask of the metal gate electrode.

In this case, the nitride film 37 is formed by forming a nitride film 37 on the entire surface and planarizing etching thereof to bury the top of the tungsten / tungsten nitride film 35 stacked structure between the insulating film spacer (29). In addition, the planarization etching process may be performed by using a CMP process, using a difference in etching selectivity from the internal oxide layer 31.

The nitride layer 37 may be formed of a silicon rich nitride layer.

Here, the nitride film 37 serves to facilitate the subsequent process. (FIG. 2F)

As described above, in the method of forming a transistor of the semiconductor device according to the present invention, a gate electrode is formed using a damascene method, an insulating layer spacer is formed on the sidewalls, and a hard mask is formed on the sidewall of the gate electrode during the subsequent etching process. By preventing damage, the present invention can be applied to highly integrated semiconductor devices having a design rule of 0.13 µm or less.

Claims (6)

Forming an oxide film and a polysilicon laminated structure on the frequency substrate, Patterning the stacked structure by a photolithography process using a gate electrode mask; Forming an insulating film spacer on sidewalls of the patterned stacked structure; Forming an impurity junction region by implanting impurities into the semiconductor substrate; Forming the laminated structure and the planarized internal oxide film on the entire surface thereof; Removing the laminated structure and continuously forming alumina as a gate insulating film and a tungsten / tungsten nitride film for a gate electrode on the entire surface thereof; Etching back to the tungsten / tungsten nitride film between the insulating film spacers; And forming a hard mask on the tungsten / tungsten nitride film between the insulating film spacers. The method of claim 1, And forming the insulating film spacers using a plasma etching cape using C-H-F-based gas. The method of claim 1, And etching the tungsten / tungsten nitride film in a plasma etching process using a fluorine (F) -containing gas. The method of claim 3, wherein And the fluorine (F) -containing gas is NF ₃ or SF ₆ gas. The method of claim 1, And said hard mask is formed of a nitride film. The method of claim 5, The hard mask is formed of a silicon rich nitride film, the transistor forming method of a semiconductor device.