CN117672974A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: forming source and drain grooves in channel stacks at two sides of the pseudo gate structures of the first region and the second region; removing part of the thickness sacrificial layer exposed from the side wall of the source drain groove along the length direction of the channel layer, so that a groove is formed between the adjacent channel layer and the residual sacrificial layer or between the protruding part and the adjacent channel layer and the residual sacrificial layer; forming an inner side wall in the grooves of the first area and the second area; forming a first source-drain doping layer in the source-drain groove of the first region, wherein the first source-drain doping layer is contacted with the side wall of the inner side wall; and forming a second source-drain doping layer in the source-drain groove of the second region, wherein the second source-drain doping layer is contacted with the side wall of the inner side wall. The embodiment of the invention simplifies the process flow and improves the process integration degree.

Description

Method for forming semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

To better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.

However, the current process flow for forming the fully-surrounding gate transistor is complex.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which simplifies the process flow.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region for forming a first type MOS transistor and a second region for forming a second type MOS transistor, the first type MOS transistor and the second type MOS transistor having different channel conductivity types; the substrate comprises a substrate and a protruding part protruding out of the substrate, one or more channel laminated layers which are stacked in sequence from bottom to top are formed on the protruding part, and each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a dummy gate structure across the channel stack; forming source and drain grooves in channel stacks at two sides of the pseudo gate structures of the first region and the second region; removing the part of the thickness sacrificial layer exposed from the side wall of the source drain groove along the length direction of the channel layer, so that a groove is formed between the adjacent channel layer and the residual sacrificial layer or between the protruding part and the adjacent channel layer and the residual sacrificial layer; forming an inner side wall in the grooves of the first area and the second area; forming a first source-drain doping layer in the source-drain groove of the first region, wherein the first source-drain doping layer is contacted with the side wall of the inner side wall; and forming a second source-drain doping layer in the source-drain groove of the second region, wherein the second source-drain doping layer is contacted with the side wall of the inner side wall.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the embodiment of the invention, the source-drain grooves are formed in the channel laminated layers at the two sides of the pseudo gate structure of the first area and the second area, then the part of the thickness sacrificial layer exposed out of the side wall of the source-drain groove is removed along the length direction of the channel layer to form the grooves, and then the inner side walls are formed in the grooves of the first area and the second area, so that the process for forming the inner side walls of the first area and the second area is integrated together.

Drawings

Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

fig. 8 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the current process flow for forming the fully-enclosed gate transistor is complex. Now, in combination with a method for forming a semiconductor structure, the reason that the process flow for forming the fully-enclosed gate transistor is complex is analyzed.

Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate is provided including a first region I for forming a first type MOS transistor and a second region II for forming a second type MOS transistor, the first type MOS transistor and the second type MOS transistor being different in channel conductivity type; the base comprises a substrate 1 and a protruding part 2 protruding from the substrate 1, one or more channel stacks 5 which are stacked sequentially from bottom to top are formed on the protruding part 2, and each channel stack 5 comprises a sacrificial layer 3 and a channel layer 4 positioned on the sacrificial layer 3; a dummy gate structure 6 is formed across the channel stack 5.

Referring to fig. 2, first source-drain recesses 7 are formed in the channel stack 5 on both sides of the dummy gate structure 6 in the first region I.

Referring to fig. 3, the sacrificial layer 3 is removed along the length direction of the channel layer 4 by removing the exposed part of the thickness of the sidewall of the first source drain groove 7, so that a first groove (not shown) is formed between the adjacent channel layer 4 and the remaining sacrificial layer 3 or between the protruding part 2 and the adjacent channel layer 4 and the remaining sacrificial layer 3; a first inner sidewall 71 is formed in the first trench.

Referring to fig. 4, after forming the first sidewall wall 71, a first source-drain doped layer 72 is formed in the first source-drain recess 7.

Referring to fig. 5, after forming the first source-drain doped layer 72, second source-drain recesses 8 are formed in the channel stack 5 on both sides of the dummy gate structure 6 of the second region II.

Referring to fig. 6, the sacrificial layer 3 is removed along the length direction of the channel layer 4 by removing the exposed part of the sidewall of the second source drain groove 8, so that a second trench (not shown) is formed between the adjacent channel layer 4 and the remaining sacrificial layer 3 or between the protrusion 2 and the adjacent channel layer 4 and the remaining sacrificial layer 3; a second sidewall wall 81 is formed in the second trench.

Referring to fig. 7, after forming the second sidewall wall 81, a second source-drain doped layer 82 is formed in the second source-drain recess 8.

In the method for forming a semiconductor structure, the steps of forming the first source-drain groove 7, the first trench and the first inner side wall 71, and the steps of forming the second source-drain groove 8, the second trench and the second inner side wall 81 are performed respectively, multiple times of photolithography, etching and deposition processes are required, and the process flow is complex.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region for forming a first type MOS transistor and a second region for forming a second type MOS transistor, the first type MOS transistor and the second type MOS transistor having different channel conductivity types; the substrate comprises a substrate and a protruding part protruding out of the substrate, one or more channel laminated layers which are stacked in sequence from bottom to top are formed on the protruding part, and each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a dummy gate structure across the channel stack; forming source and drain grooves in channel stacks at two sides of the pseudo gate structures of the first region and the second region; removing the part of the thickness sacrificial layer exposed from the side wall of the source drain groove along the length direction of the channel layer, so that a groove is formed between the adjacent channel layer and the residual sacrificial layer or between the protruding part and the adjacent channel layer and the residual sacrificial layer; forming an inner side wall in the grooves of the first area and the second area; forming a first source-drain doping layer in the source-drain groove of the first region, wherein the first source-drain doping layer is contacted with the side wall of the inner side wall; and forming a second source-drain doping layer in the source-drain groove of the second region, wherein the second source-drain doping layer is contacted with the side wall of the inner side wall.

In the method for forming the semiconductor structure provided by the embodiment of the invention, the source-drain grooves are formed in the channel laminated layers at the two sides of the pseudo gate structure of the first area and the second area, then the part of the thickness sacrificial layer exposed out of the side wall of the source-drain groove is removed along the length direction of the channel layer to form the grooves, and then the inner side walls are formed in the grooves of the first area and the second area, so that the process for forming the inner side walls of the first area and the second area is integrated together.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 8 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 8, a substrate is provided including a first region I for forming a first type MOS transistor and a second region II for forming a second type MOS transistor, the first type MOS transistor and the second type MOS transistor being different in channel conductivity type; the base includes a substrate 100 and a protrusion 110 protruding from the substrate 100, and one or more channel stacks 210 stacked sequentially from bottom to top are formed on the protrusion 110, each channel stack 210 including a sacrificial layer 20 and a channel layer 30 on the sacrificial layer 20.

The substrate is used for providing a process platform for the subsequent process. In this embodiment, a fully-enclosed Gate (GAA) transistor is formed as an example. In other embodiments, the formation method may also be used to form a fork gate transistor (fork gate) or a Complementary Field Effect Transistor (CFET).

As an example, the first type MOS transistor is a PMOS transistor and the second type MOS transistor is an NMOS transistor. In other implementations, the first type MOS transistor may also be an NMOS transistor, and the second type MOS transistor may be a PMOS transistor.

In this embodiment, the substrate 100 is a silicon substrate, i.e., the material of the substrate 100 is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

In this embodiment, the bump 110 and the substrate 100 are in an integral structure, and the bump 110 and the substrate 100 are made of the same material and are all made of silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

In this embodiment, the protruding portion 110 is a fin structure extending in the lateral direction.

The channel stack 210 provides a process basis for the subsequent formation of the channel layer 30 in a floating spacer arrangement.

Specifically, the channel layer 30 and a conductive channel for providing a field effect transistor, the sacrificial layer 20 is used for supporting the second channel layer 30, thereby providing a process basis for the subsequent implementation of the spaced-apart suspended arrangement of the channel layer 30, and the sacrificial layer 20 is also used for occupying a space position for the subsequent formation of the gate structure.

In this embodiment, the material of the channel layer 30 of the first region I is the same as that of the channel layer 30 of the second region II, and the material of the sacrificial layer 20 of the first region I is the same as that of the sacrificial layer 20 of the second region II.

As an example, the material of the channel layer 30 is Si and the material of the sacrificial layer 20 is SiGe. In the subsequent process of removing the sacrificial layer 20, the etching selection of SiGe and Si is relatively high, so that the effect of the removal process of the sacrificial layer 20 on the channel layer 30 can be effectively reduced by setting the material of the sacrificial layer 20 to SiGe and setting the material of the channel layer 30 to Si, thereby improving the quality of the channel layer 30 and further being beneficial to improving the device performance.

In other embodiments, the material of the channel layer may also be SiGe, with the material of the sacrificial layer correspondingly being Si.

In other embodiments, the material of the channel layer of the first region may also be different from the material of the channel layer of the second region, and accordingly, the material of the sacrificial layer of the first region may also be different from the material of the sacrificial layer of the second region.

As one example, the number of channel stacks 210 is three. In other embodiments, the channel stack may be other numbers.

In this embodiment, an isolation layer 105 surrounding the convex portion 110 is also formed on the substrate 100.

The isolation layer 105 is used to isolate adjacent protruding portions 110 from each other, and is also used to isolate the substrate 100 from a subsequent gate structure. In this embodiment, the material of the isolation layer 105 is silicon oxide. The isolation layer 105 may also be other insulating materials.

With continued reference to fig. 8, a dummy gate structure 120 is formed across the channel stack 210.

Wherein the dummy gate structure 120 is used to pre-occupy a spatial position for a subsequent gate structure formation.

Specifically, the dummy gate structure 120 is located on the isolation layer 105 and covers a portion of the top and a portion of the sidewalls of the channel stack 210. The extension direction of the dummy gate structure 120 is perpendicular to the extension direction of the channel stack.

The dummy gate structure 120 may have a stacked structure or a single-layer structure. In this embodiment, the dummy gate structure 120 is a stacked structure, and includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) on the dummy gate oxide layer.

Specifically, the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the dummy gate layer may be polysilicon or amorphous silicon.

In this embodiment, in the step of forming the dummy gate structure 120, a dummy gate mask layer (not shown) is further formed on top of the dummy gate structure 120.

The dummy gate mask layer is used as an etching mask for patterning the dummy gate material layer to form the dummy gate mask layer.

As an example, the material of the dummy gate mask layer is silicon nitride.

With continued reference to fig. 8, the method of forming a semiconductor structure further includes: a gate sidewall 130 is formed on the sidewall of the dummy gate structure 120.

In this embodiment, the gate sidewall 130 is used together with the dummy gate structure 120 as an etching mask for subsequently forming the source-drain recess to define the formation position of the source-drain doped layer, and the gate sidewall 130 is also used to protect the sidewalls of the dummy gate structure 120 and the subsequent gate structure.

In this embodiment, the material of the gate sidewall 130 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate sidewall 130 has a single-layer or stacked-layer structure. As an example, the gate sidewall 130 has a single-layer structure, and the material of the gate sidewall 130 is silicon nitride.

Referring to fig. 9, source-drain recesses 140 are formed in the channel stack 210 on both sides of the dummy gate structure 120 in the first region I and the second region II.

In this embodiment, the source-drain recess 140 is used to provide a space for forming the source-drain doped layer. The source-drain groove 140 of the first region I is used for providing a spatial position for the subsequent formation of the first source-drain doped layer, and the source-drain groove 140 of the second region II is used for providing a spatial position for the subsequent formation of the second source-drain doped layer.

And, the sidewalls of the source-drain recess 140 also expose the channel stack 210, so that the sacrificial layer 20 is removed along the length direction of the channel layer.

As an example, the channel stack 210 is etched to form the source-drain recess 140 using the dummy gate mask layer, the dummy gate structure, and the gate sidewall as masks using an anisotropic etching process.

As an example, the anisotropic etching process is an anisotropic dry etching process.

Referring to fig. 10, the sacrificial layer 20 is removed along the length direction of the channel layer 30 by removing the exposed portion of the sidewall of the source drain recess 140, so that a trench 145 is defined between the adjacent channel layer 30 and the remaining sacrificial layer 20 or between the protrusion 110 and the adjacent channel layer 30 and the remaining sacrificial layer 20.

Wherein the trench 145 is used to provide a spatial location for a subsequently formed sidewall (Inner spacer).

In this embodiment, an isotropic etching process is used to remove the part of the sacrificial layer 20 exposed from the sidewalls of the source/drain grooves 140 along the length direction of the channel layer 30.

In this embodiment, the sacrificial layer 20 with partial thickness of the sidewall of the source drain groove 140 is etched along the length direction of the channel layer 30 by using a vapor etching process.

In the above embodiment, the vapor etching process is an isotropic etching process, and can etch the sacrificial layer 20 along the length direction of the channel layer 30, and the vapor etching process is easy to realize a larger etching selectivity, which is beneficial to reducing the difficulty of etching the sacrificial layer 20 and reducing the probability of damaging other film structures (such as the channel layer 30).

In this embodiment, the material of the sacrificial layer 20 is SiGe, the material of the channel layer 30 is Si, and the sacrificial layer 20 on the sidewall of the source drain groove 140 is vapor etched by HCl vapor. The etching rate of the HCl vapor to the SiGe material is much greater than that to the Si material, which effectively reduces the chance of damage to the channel layer 30.

In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, an isotropic dry etching process may be used to etch the sacrificial layer on the sidewall of the recess in the lateral direction. The etchant of the dry etching process may include CF ₄ 、O ₂ 、N ₂ Is a mixture of plasmas of (a) and (b). The difference between the etching rate of the plasma mixture to Si and the etching rate to SiGe is large, and the probability of loss of the channel layer can be effectively reduced.

Referring to fig. 11, an inner sidewall wall 150 is formed in the trench 145 of the first region I and the second region II.

Subsequently, a first source-drain doped layer is formed in the source-drain groove 140 of the first region I, a second source-drain doped layer is formed in the source-drain groove 140 of the second region II, and a gate structure is formed at the positions of the dummy gate structure 120 and the sacrificial layer 20, and the inner sidewall 150 is used for realizing isolation between the first source-drain doped layer and the gate structure and between the second source-drain doped layer and the gate structure, and further increasing the distance between the first source-drain doped layer and the gate structure and between the second source-drain doped layer and the gate structure, which is beneficial for reducing parasitic capacitance between the first source-drain doped layer and the gate structure and between the second source-drain doped layer and the gate structure.

In this embodiment, the material of the inner sidewall 150 is an insulating material, so as to realize isolation between the first source-drain doped layer and the gate structure, and between the second source-drain doped layer and the gate structure.

In this embodiment, the material of the inner sidewall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. As an example, the material of the inner sidewall 150 is silicon nitride.

In this embodiment, the step of forming the inner sidewall includes: and forming inner side walls on the top and the side walls of the pseudo gate structure and the side walls and the bottom of the source drain groove, wherein the inner side walls are filled in the grooves.

In this embodiment, the process of forming the sidewall spacer includes an atomic layer deposition process. The atomic layer deposition process comprises multiple atomic layer deposition cycles, and has good gap filling performance and step coverage, and accordingly the gap filling capability of the inner side wall is improved, so that the filling capability of the inner side wall in the groove is improved.

Referring to fig. 12 to 13, a first source-drain doped layer 170 is formed in the source-drain recess 140 of the first region I, and the first source-drain doped layer 170 contacts with the sidewalls of the inner sidewall 150.

The first source-drain doped layer 170 is used as a source or a drain of the first type MOS transistor, and the first source-drain doped layer 170 is used to provide a carrier source when the first type MOS transistor operates.

In this embodiment, the first source-drain doped layer 170 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers.

Specifically, the first type MOS transistor is a PMOS transistor, the first source-drain doped layer comprises a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe. In other embodiments, when the first type MOS transistor is an NMOS transistor, the first source-drain doped layer includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

In this embodiment, referring to fig. 12, the method for forming a semiconductor structure further includes: after forming the sidewall spacers 150 and before forming the first source and drain doped layer 170, the sidewall spacers 150 on the top and sidewalls of the dummy gate structure 120, the bottom of the source and drain recesses 140, and the channel layer 30 on the sidewalls of the source and drain recesses 140 in the first region I are removed.

In the above embodiment, the top and the side walls of the dummy gate structure 120, the bottom of the source drain recess 140, and the inner side walls 150 on the channel layer 30 on the side walls of the source drain recess 140 are removed so as to expose the raised portion 110 at the bottom of the source drain recess 140 and the channel layer 30 on the side walls of the source drain recess 140 in the first region I, thereby enabling the first source drain doped layer 170 subsequently formed in the source drain recess 140 in the first region I to contact the channel layer 30.

Specifically, the method for forming the semiconductor structure further comprises the following steps: after forming the inner sidewall 150 and before forming the first source/drain doped layer 170, forming a first mask layer covering the second region II, wherein the first mask layer exposes the first region I; the top and side walls of the dummy gate structure 120, the bottom of the source drain recess 140, and the inner side walls 150 on the channel layer 30 on the side walls of the source drain recess 140 in the first region I are removed using the first mask layer as a mask.

The first mask layer is used as an etching mask for removing the top and the side walls of the dummy gate structure 120, the bottom of the source drain groove 140, and the inner sidewall wall 150 on the channel layer 30 on the side wall of the source drain groove 140 in the first region I.

In this embodiment, the first mask layer includes a first planarization layer 171, a first anti-reflection layer 172, and a first photoresist pattern layer 173, which are sequentially formed from bottom to top.

In this embodiment, the first planarization layer 171 is used to provide a planar surface for forming the first anti-reflection layer 172 and the first photoresist pattern layer 173.

As an example, the material of the first planarization layer 171 includes ODL (organic dielectric layer) or SOC (spin-on carbon).

The first anti-reflection layer 172 serves to reduce reflection effects during exposure for forming the first photoresist pattern layer 173. As one example, the material of the first anti-reflective layer 172 includes Si-ARC or BARC.

In this embodiment, the first photoresist pattern layer 173 is used as an etching mask.

In this embodiment, the material of the first photoresist pattern layer 173 is photoresist.

In this embodiment, an anisotropic etching process is used to remove the inner sidewalls 150 on the top of the dummy gate structure 120 and the bottom of the source drain recess 140; the inner sidewall 150 on the channel layer 30 on the sidewalls of the dummy gate structure 120 and the sidewalls of the source drain recess 140 is removed using an isotropic etching process.

The anisotropic etching process has the characteristic of anisotropic etching, so that the inner side wall 150 can be etched in a direction perpendicular to the substrate, thereby facilitating removal of the inner side wall 150 located at the bottom of the source drain groove 140.

As an example, the anisotropic etching process is an anisotropic dry etching process.

As one example, the anisotropic dry etch process includes an atomic layer etch (atomic layer etch, ALE) process. The atomic layer etching process has the characteristics of low etching damage, high selection ratio, accurate depth control, low power process and the like, can accurately etch to one atomic layer, requires the etching process to be uniformly carried out one atomic layer after another and is stopped at proper time or position, thereby obtaining extremely high etching selectivity and etching accuracy.

In particular, the atomic layer etching process may be a capacitively coupled plasma (capacitively coupled plasma, CCP). In other embodiments, an inductively coupled plasma ICP (Inductively coupled plasma) or other etching process is also possible.

The isotropic etching process has the characteristic of isotropic etching, so that the inner side wall 150 can be etched along the direction parallel to the substrate, and the inner side wall 150 on the side wall of the dummy gate structure and the channel layer of the side wall of the source drain groove can be removed.

As one example, the isotropic etching process is a wet etching process.

In this embodiment, the material of the inner sidewall 150 is silicon nitride, and the etching solution of the wet etching process includes phosphoric acid solution.

In this embodiment, after the top and the side walls of the dummy gate structure 120, the bottom of the source drain recess 140, and the inner side walls 150 on the channel layer 30 of the side walls of the source drain recess 140 are removed, the side walls and the bottom of the source drain recess 140 of the second region II are still covered by the inner side walls 150, so that the first source drain doped layer 170 is formed only in the source drain recess 140 of the first region I.

Referring to fig. 14 to 15, a second source-drain doped layer 180 is formed in the source-drain recess 140 of the second region II, and the second source-drain doped layer 180 contacts with the sidewalls of the inner sidewall 150.

The second source-drain doped layer 180 is used as a source or a drain of the second type MOS transistor, and the second source-drain doped layer 180 is used to provide a carrier source when the second type MOS transistor is operated.

In this embodiment, the second source-drain doped layer 180 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers.

Specifically, in this embodiment, the second type MOS transistor is an NMOS transistor, and the second source-drain doped layer 180 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC. In other embodiments, the second type MOS transistor is a PMOS transistor, and the second source drain doped layer 180 includes a stress layer doped with P-type ions, where the material of the stress layer is Si or SiGe.

In this embodiment, the method for forming a semiconductor structure further includes: referring to fig. 14, after forming the inner sidewalls 150, and before forming the second source drain doping layer 180, the inner sidewalls 150 on the top and sidewalls of the dummy gate structure 120, the bottom of the source drain recess 140, and the channel layer 30 of the sidewalls of the source drain recess 140 in the second region II are removed.

The top and side walls of the dummy gate structure 120, the bottom of the source drain recess 140, and the inner sidewalls 150 on the channel layer 30 of the side walls of the source drain recess 140 in the second region II are removed to expose the raised portion 110 at the bottom of the source drain recess 140 and the channel layer 30 of the side walls of the source drain recess 140 in the second region II, so that the second source drain doped layer 180 can be subsequently formed in the source drain recess 140 in the second region II.

In this embodiment, the method for forming a semiconductor structure further includes: after forming the inner sidewall wall 150 and before forming the second source-drain doped layer 180, forming a second mask layer covering the first region I, wherein the second mask layer exposes the second region II; the second mask layer is used as a mask to remove the top and side walls of the dummy gate structure 120, the bottom of the source drain recess 140, and the inner side walls 150 on the channel layer of the side walls of the source drain recess 140 in the second region II.

The second mask layer is used as an etching mask for removing the top and sidewall of the dummy gate structure 120, the bottom of the source drain recess 140, and the sidewall of the source drain recess 140 on the sidewall of the channel layer 30 in the second region II.

In this embodiment, the second mask layer includes a second planarization layer 181, a second anti-reflection layer 182, and a second photoresist pattern layer 183, which are sequentially formed from bottom to top.

Wherein the second planarization layer 181 is used to provide a planarized surface for forming the second anti-reflection layer 182 and the second photoresist pattern layer 183.

As an example, the material of the second flat layer 181 includes ODL (organic dielectric layer) or SOC (spin-on carbon).

In this embodiment, the second anti-reflection layer 182 is used to reduce the reflection effect during the exposure process for forming the second photoresist pattern layer 183. As an example, the material of the second anti-reflective layer 182 includes Si-ARC or BARC.

In this embodiment, the second photoresist pattern layer 183 is used as an etching mask.

In this embodiment, the material of the second photoresist pattern layer 183 is photoresist.

In this embodiment, an anisotropic etching process is used to remove the inner sidewalls 150 on the top of the dummy gate structure 120 and the bottom of the source drain recess 140; the inner sidewall 150 on the channel layer 30 on the sidewalls of the dummy gate structure 120 and the sidewalls of the source drain recess 140 is removed using an isotropic etching process.

The anisotropic etching process has the characteristic of anisotropic etching, so that the inner side wall 150 can be etched in a direction perpendicular to the substrate, thereby facilitating removal of the inner side wall 150 located at the bottom of the source drain groove 140.

As an example, the anisotropic etching process is an anisotropic dry etching process.

As one example, the anisotropic dry etch process includes an atomic layer etch (atomic layer etch, ALE) process. The atomic layer etching process has the characteristics of low etching damage, high selection ratio, accurate depth control, low power process and the like, can accurately etch to one atomic layer, requires the etching process to be uniformly carried out one atomic layer after another and is stopped at proper time or position, thereby obtaining extremely high etching selectivity and etching accuracy.

In particular, the atomic layer etching process may be a capacitively coupled plasma (capacitively coupled plasma, CCP). In other embodiments, an inductively coupled plasma ICP (Inductively coupled plasma) or other etching process is also possible.

The isotropic etching process has the characteristic of isotropic etching, so that the inner side wall 150 can be etched along the direction parallel to the substrate, and the inner side wall 150 on the side wall of the dummy gate structure and the channel layer of the side wall of the source drain groove can be removed.

As one example, the isotropic etching process is a wet etching process.

In this embodiment, the material of the inner sidewall 150 is silicon nitride, and the etching solution of the wet etching process includes phosphoric acid solution.

In this embodiment, before forming the second mask layer, a protective layer (not shown) is further formed to cover the substrate; before the second mask layer is used as a mask to remove the top and the side walls of the dummy gate structure 120, the bottom of the source drain groove 140, and the inner side wall 150 on the channel layer of the side wall of the source drain groove 140 in the second region II, the second mask layer is used as a mask to remove the protection layer in the first region I to expose the second region II.

Accordingly, the remaining protective layer located in the first region II can protect the first region I during the subsequent step of forming the second source/drain doped layer 180, so as to prevent the process of forming the second source/drain doped layer 180 from affecting the first region I.

In the present embodiment, the formation of the second source-drain doped layer 180 after the formation of the first source-drain doped layer 170 is described as an example. In other embodiments, the first source-drain doped layer may be formed in the first region after the second source-drain doped layer is formed in the second region.

It should be noted that, in this embodiment, before forming the source-drain doped layer, the inner sidewalls 150 on the bottom of the source-drain recess 140 and on the sidewall channel layer 30 of the source-drain recess 140 in the corresponding region are removed, respectively. In other embodiments, after forming the sidewall wall and before forming the first source-drain doped layer and the second source-drain doped layer, the sidewall wall on the top and the sidewall of the dummy gate structure, the bottom of the source-drain recess, and the channel layer of the sidewall of the source-drain recess may be removed in the first region and the second region.

Referring to fig. 16, after forming the first source-drain doped layer 170 and the second source-drain doped layer 180, the dummy gate structure 120 is removed, forming a gate opening (not shown) exposing the channel stack 210; removing the sacrificial layer 20 from the channel stack 210 through the gate opening to form a via (not shown), the via being surrounded by the raised portion 110 and the adjacent channel layer 30, or by the adjacent channel layer 30; the gate opening and the via are filled with a gate structure 190, and the gate structure 190 surrounds the channel layer 30.

The gate openings are used to provide spatial locations for forming the gate structures. The gate opening exposes the channel stack 210 to facilitate subsequent removal of the sacrificial layer 20 in the channel stack 210 through the gate opening.

Specifically, after forming the first source-drain doped layer 170 and the second source-drain doped layer 180, and before removing the dummy gate structure 120, further includes: an interlayer dielectric layer 160 covering the first source drain doping layer 170 and the second source drain doping layer 180 is formed at the side of the dummy gate structure 120.

The interlayer dielectric layer 160 serves to isolate adjacent devices. As an example, the material of the interlayer dielectric layer 160 is silicon oxide.

In the step of forming the interlayer dielectric layer 160, the dummy gate mask layer is also removed.

In this embodiment, a gate opening spans channel stack 210 and is located in interlayer dielectric layer 160.

In this embodiment, the through-slots and the gate openings together provide a spatial location for forming the gate structure. The through slot is communicated with the grid opening.

In the above embodiment, the sacrificial layer 20 is removed after the first source-drain doped layer 170 and the second source-drain doped layer 180 are formed, so that after the sacrificial layer 20 is removed, two ends of the channel layer 30 in the first region I are connected to the first source-drain doped layer 170, two ends of the channel layer 30 in the second region II are connected to the second source-drain doped layer 180, and the channel layer 30 is suspended in the gate opening so that the subsequent gate structure can surround the channel layer.

In this embodiment, a vapor etching process is used to remove the sacrificial layer 20. Specifically, the material of the channel layer 30 is Si, and the material of the sacrificial layer 20 is SiGe, so that the sacrificial layer 20 exposed by the gate opening is removed by HCl vapor, and the HCl vapor has a high etching selectivity ratio between SiGe and Si, which is beneficial to improving the removal efficiency of the sacrificial layer 20 and reducing the probability of damage to the channel layer 30.

In this embodiment, the gate structure 190 is used to control the turning on and off of the conductive channel during operation of the device.

In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filled in the through-trench and the gate opening.

In this embodiment, the gate dielectric layer is used to realize electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The gate dielectric layer comprises silicon oxide, nitrogen doped silicon oxide and HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ And Al ₂ O ₃ One or more of the following.

In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ . In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.

In this embodiment, the work function layer is used to adjust the work function of the gate structure 190, thereby adjusting the threshold voltage of the field effect transistor. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

In this embodiment, the gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, for example: w, al, cu, ag, au, pt, ni or Ti, etc.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (13)

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a first region for forming a first type MOS transistor and a second region for forming a second type MOS transistor, the first type MOS transistor and the second type MOS transistor having different channel conductivity types; the substrate comprises a substrate and a protruding part protruding out of the substrate, one or more channel laminated layers stacked in sequence from bottom to top are formed on the protruding part, and each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer;

forming a dummy gate structure across the channel stack;

forming source and drain grooves in channel stacks at two sides of the pseudo gate structures of the first region and the second region;

removing part of the thickness sacrificial layer exposed from the side wall of the source drain groove along the length direction of the channel layer, so that a groove is formed between the adjacent channel layer and the residual sacrificial layer or between the protruding part and the adjacent channel layer and the residual sacrificial layer;

forming an inner side wall in the grooves of the first area and the second area;

forming a first source-drain doping layer in the source-drain groove of the first region, wherein the first source-drain doping layer is contacted with the side wall of the inner side wall;

and forming a second source-drain doping layer in the source-drain groove of the second region, wherein the second source-drain doping layer is contacted with the side wall of the inner side wall.

2. The method of forming a semiconductor structure of claim 1, wherein forming the sidewall spacer comprises: forming inner side walls on the top and the side walls of the pseudo gate structure and the side walls and the bottom of the source drain groove, wherein the inner side walls are filled in the grooves;

the method for forming the semiconductor structure further comprises the following steps: removing the top and the side wall of the pseudo gate structure, the bottom of the source drain groove and the inner side wall on the channel layer of the side wall of the source drain groove in the first area after the inner side wall is formed and before the first source drain doping layer is formed;

the method for forming the semiconductor structure further comprises the following steps: and after the inner side wall is formed and before the second source-drain doped layer is formed, removing the top and the side wall of the pseudo gate structure, the bottom of the source-drain groove and the inner side wall on the channel layer of the side wall of the source-drain groove in the second region.

3. The method of forming a semiconductor structure of claim 2, further comprising: after the inner side wall is formed and before the first source-drain doping layer is formed, a first mask layer covering the second area is formed, and the first mask layer exposes the first area; and taking the first mask layer as a mask, and removing the top and the side wall of the pseudo gate structure, the bottom of the source drain groove and the inner side wall on the channel layer of the side wall of the source drain groove in the first region.

4. The method of forming a semiconductor structure of claim 2, further comprising: after the inner side wall is formed and before a second source-drain doped layer is formed, a second mask layer covering the first area is formed, and the second mask layer exposes the second area; and taking the second mask layer as a mask, and removing the top and the side wall of the pseudo gate structure, the bottom of the source drain groove and the inner side wall on the channel layer of the side wall of the source drain groove in the second region.

5. The method of forming a semiconductor structure of any one of claims 2 to 4, wherein removing inner sidewalls on the top and sidewalls of the dummy gate structure, the bottom of the source drain recess, and the channel layer of the source drain recess sidewalls comprises: removing inner side walls positioned on the top of the pseudo gate structure and the bottom of the source drain groove by adopting an anisotropic etching process; and removing the inner side walls on the side walls of the pseudo gate structure and the channel layer of the side wall of the source drain groove by adopting an isotropic etching process.

6. The method of forming a semiconductor structure of claim 5, wherein the anisotropic etch process is an anisotropic dry etch process.

7. The method of forming a semiconductor structure of claim 6, wherein the dry etching process comprises an atomic layer etching process.

8. The method of forming a semiconductor structure of claim 5, wherein the isotropic etching process comprises a wet etching process.

9. The method of forming a semiconductor structure of claim 8, wherein the etching solution of the wet etching process comprises a phosphoric acid solution.

10. The method of forming a semiconductor structure of claim 2, wherein the process of forming the sidewall spacer comprises an atomic layer deposition process.

11. The method of claim 1, wherein the sacrificial layer is removed along the length of the channel layer by an isotropic etching process.

12. The method of forming a semiconductor structure of claim 1, wherein the first type MOS transistor is a PMOS transistor and the second type MOS transistor is an NMOS transistor; alternatively, the first type MOS transistor is an NMOS transistor and the second type MOS transistor is a PMOS transistor.

13. The method of forming a semiconductor structure according to any one of claims 1 to 4, 10 to 12, further comprising: removing the pseudo gate structure after the first source-drain doped layer and the second source-drain doped layer are formed, and forming a gate opening to expose the channel stack;

removing the sacrificial layer in the channel laminated layer through the gate opening to form a through groove, wherein the through groove is surrounded by the protruding part and the adjacent channel layer or is surrounded by the adjacent channel layer;

and filling a gate structure in the gate opening and the through groove, wherein the gate structure surrounds the channel layer.