CN117410288A

CN117410288A - Semiconductor structure and forming method thereof

Info

Publication number: CN117410288A
Application number: CN202210801270.7A
Authority: CN
Inventors: 武咏琴
Original assignee: North Ic Technology Innovation Center Beijing Co ltd
Current assignee: North Ic Technology Innovation Center Beijing Co ltd
Priority date: 2022-07-08
Filing date: 2022-07-08
Publication date: 2024-01-16

Abstract

A semiconductor structure and a method for forming the same, wherein the method for forming comprises: forming a dummy gate structure crossing the laminated structure in the first region and the second region respectively; forming a first covering layer covering the substrate and the pseudo gate structure in the second region; forming a first source-drain doping layer on the laminated structure of the first region and the substrates at two sides of the pseudo gate structure; forming a second covering layer covering the first source-drain doping layer and the pseudo gate structure in the first region, and removing the first covering layer on the second region; removing the sacrificial layer with the preset first thickness in the channel lamination layer on the second area to form a groove; forming a barrier layer in the trench of the second region; forming an inner side wall at the rest part of the groove; removing a channel layer and a part of the substrate with preset second thickness in the channel stack layer on the second region; forming a second source-drain doped layer; and removing the pseudo gate structures on the first region and the second region to form a gate opening. By adopting the scheme, the electrical performance of the semiconductor structure can be improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

To better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.

However, the performance of the fully-surrounding gate transistor is still to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which can balance the current of a semiconductor device and improve the electrical property of the semiconductor structure.

To solve the above-described problems, embodiments of the present disclosure provide a semiconductor structure, including: a substrate, comprising: a substrate having a first region and a second region; the channel structure layers are respectively positioned above the substrates of the first area and the second area and comprise one or more channel layers which are sequentially arranged at intervals from bottom to top; a gate structure crossing the channel structure layer on the first region and the second region, respectively, wherein: the gate structure ring located in the first region surrounds the channel layers arranged at intervals and fills a space between the substrate and the adjacent channel layers; the gate structure ring in the second region surrounds the channel layers arranged at intervals and fills a space between the substrate and the adjacent channel layers; the first source-drain doped layer is positioned on the channel structure layer of the first region and the substrate at two sides of the grid structure; the second source-drain doping layer is positioned on the substrate at the two sides of the channel structure layer and the grid structure of the second region, wherein the bottom height of the first source-drain doping layer above the substrate is higher than the bottom height of the second source-drain doping layer; the inner side wall is positioned between the second source-drain doping layer and the grid structure, and the outer side face of the inner side wall is vertically flush with the end face of the channel structure layer.

Correspondingly, the embodiment of the specification also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a first area and a second area, a laminated structure is formed on the first area and the second area respectively, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, and each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a dummy gate structure crossing the laminated structure in the first region and the second region respectively; forming a first covering layer covering the substrate and the dummy gate structure in the second region; forming a first source-drain doping layer on the laminated structure of the first region and the substrates at two sides of the pseudo gate structure; forming a second covering layer covering the first source-drain doping layer and the pseudo gate structure in the first region, and removing the first covering layer on the second region; removing the sacrificial layer with the preset first thickness in the channel lamination layer on the second area to form a groove; forming a barrier layer in the groove of the second region; forming an inner side wall at the rest part of the groove, wherein the outer side surface of the formed inner side wall is vertically flush with the end surface of the channel layer; removing a channel layer and a part of substrate with preset second thickness in the channel laminated layer on the second area; forming a second source-drain doping layer on the laminated structure of the second region and the substrates at two sides of the pseudo gate structure; removing the pseudo gate structures on the first region and the second region to form a gate opening, and exposing the laminated structure; removing the sacrificial layer in the channel stack layer on the first region to form a first through groove, and removing the sacrificial layer and the blocking layer in the channel stack layer on the second region to form a second through groove, wherein the first through groove and the second through groove are both surrounded by the channel layer and the substrate or are surrounded by adjacent channel layers; and filling a gate structure in the gate opening, the first through groove and the second through groove, wherein the gate structure surrounds and spans the channel layer.

Compared with the prior art, the technical scheme of the embodiment of the specification has the following advantages:

in the semiconductor structure provided in this embodiment of the present disclosure, the first source-drain doped layer is located on the channel structure layer of the first region and the substrate on two sides of the dummy gate structure, the second source-drain doped layer is located on the channel structure layer of the second region and the substrate on two sides of the dummy gate structure, and the bottom height of the first source-drain doped layer above the substrate is higher than the bottom height of the second source-drain doped layer, that is, the height of the second source-drain doped layer is higher than the height of the first doped layer, which is favorable to increasing the hole mobility of the second region and further increasing the current generated in the second region, so that the current in the second region tends to the current value of the first region, balances the current of the semiconductor device, and improves the electrical performance of the semiconductor structure.

In the method for forming a semiconductor structure provided in this embodiment of the present disclosure, after forming a dummy gate structure crossing the stacked structure in the first region and the second region, a first cover layer covering the substrate and the dummy gate structure is formed in the second region, so that a second cover layer covering the first source/drain doped layer and the dummy gate structure can be formed only in the first region, and the first cover layer on the second region is removed, then a second cover layer covering the substrate and the dummy gate structure is formed in the first region, and the first cover layer on the second region is removed, so that the growth of the second source/drain doped layer can be controlled independently, and before forming the second source/drain doped layer, a blocking layer is formed in a trench of the second region, so that the sacrificial layer can be prevented from being removed completely.

Drawings

Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIG. 8 is a schematic diagram of an embodiment of a semiconductor structure according to an embodiment of the present disclosure;

fig. 9 to 23 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

As known from the background art, the performance of the fully-enclosed gate transistor still needs to be improved. The reason why the performance of the fully-enclosed gate transistor is to be improved is now analyzed in conjunction with a semiconductor structure. Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a base is provided comprising a substrate 10 and a stack structure 11 over the substrate 10, the stack structure 11 comprising one or more channel stacks 12 stacked sequentially from bottom to top, each of the channel stacks 12 comprising a sacrificial layer 121 and a channel layer 122 over the sacrificial layer.

Referring to fig. 2, a dummy gate structure 13 is formed across the stack structure 11.

With continued reference to fig. 2, after forming the dummy gate structure 13, a dummy gate mask layer 131 may also be formed on top of the dummy gate structure 13, and a sidewall 132 may be formed on a sidewall of the dummy gate structure 13. Further, before forming the dummy gate structure 13, an isolation layer 14 may also be formed over the stacked structure 11.

Referring to fig. 3, the sacrificial layer 131 in the stacked structure 11 is removed to form a trench 15.

Referring to fig. 4, an inner sidewall material layer 16 is formed on the sidewalls and the top of the dummy gate structure 14 and the sidewalls of the stacked structure 11, and the inner sidewall material layer 16 is also filled in the trench 15.

Referring to fig. 5, the inner sidewall material layer 16 outside the trench 15, on the sidewall of the stacked structure 11, and on the sidewall and top of the dummy gate structure 14 is removed, and the remaining inner sidewall material layer 16 filled in the inner trench 15 is left as an inner sidewall 17.

Referring to fig. 6, after the inner sidewall 17 is formed, a source/drain doped layer 18 is formed.

Referring to fig. 7, the dummy gate structure 14 is removed to form a gate opening (not shown); removing the sacrificial layer in the channel stack 12 to form a through trench (not shown), wherein the through trench is surrounded by the channel layer 122 and the substrate 100 or is surrounded by adjacent channel layers 122; a gate structure 19 is formed in the gate opening and the via, the gate structure 19 surrounding the channel layer 122.

In the formation of the semiconductor structure, the source-drain doped layers 18 are formed over the substrate 10 at the same time, that is, the heights of the source-drain doped layers 18 in the regions over the substrate 10 are uniform. The inventors have found that when the semiconductor device is operated, the source/drain doped layers 18 in different regions above the substrate 10 generate different currents, which in turn cause mismatch of the currents in the respective portions of the semiconductor device, and accordingly, degrade the performance of the semiconductor device.

In order to solve the above technical problems, in the semiconductor structure provided in the embodiments of the present disclosure, the first source-drain doped layer is located on the channel structure layer of the first region and the substrate on both sides of the dummy gate structure, the second source-drain doped layer is located on the channel structure layer of the second region and the substrate on both sides of the dummy gate structure, and the bottom height of the first source-drain doped layer above the substrate is higher than the bottom height of the second source-drain doped layer, that is, the height of the second source-drain doped layer is higher than the height of the first doped layer, which is favorable for increasing the hole mobility of the second region and further increasing the current generated in the second region, so that the current in the second region tends to the current value of the first region, balances the current of the semiconductor device, and improves the electrical performance of the semiconductor structure.

In order to solve the above-described technical problems, in the method for forming a semiconductor structure provided in the present embodiment, after forming a dummy gate structure crossing the stacked structure in the first region and the second region, respectively, by forming a first capping layer covering the substrate and the dummy gate structure in the second region, it is possible to form a second capping layer covering the first source-drain doped layer and the dummy gate structure only in the first region, and remove the first capping layer on the second region, and then by forming a second capping layer covering the substrate and the dummy gate structure in the first region, and remove the first capping layer on the second region, it is possible to control the growth of the second source-drain doped layer alone, and before forming the second source-drain doped layer, by forming a barrier layer in the trench of the second region, the sacrificial layer can be prevented from being completely removed, and a second source-drain doping layer with the height larger than that of the first source-drain doping layer can be formed on the laminated structure, the dummy gate structure and the substrate on two sides of the dummy gate structure of the second region by removing the channel layer and part of the substrate with the preset second thickness in the channel laminated layer on the second region, so that hole mobility of the second region is increased, current generated by the second region is increased, current of the second region tends to the current value of the first region, and by filling the gate structure in the gate opening, the first through groove and the second through groove, electric connection of the first source-drain doping layer and the second source-drain doping layer can be realized, and then, when the semiconductor device works, the current of the first region and the second region is balanced, and the electrical performance of the semiconductor structure is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 8, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown. In some embodiments of the present description, the semiconductor structure includes: a substrate, comprising: a substrate 100 having a first region I and a second region II; a channel structure layer 300, which is respectively located above the substrate 100 in the first region I and the second region II, and includes one or more channel layers 30 sequentially spaced from bottom to top; a gate structure 150 crossing the channel structure layer 300 on the first region I and the second region II, respectively, wherein: the gate structure 150 located in the first region I surrounds the channel layer 30 disposed at intervals and fills the space between the substrate 100 and the adjacent channel layer 30; the gate structure 150 in the second region II surrounds the channel layer 30 and a space between the substrate 100 and the channel layer 30 disposed adjacent to the space; a first source-drain doped layer 130 located on the substrate 100 at two sides of the channel structure layer 300 and the gate structure 150 in the first region; a second source-drain doped layer 135 located on the substrate 100 at two sides of the channel structure layer 300 and the gate structure 150 in the second region, wherein the bottom height of the first source-drain doped layer 130 above the substrate 100 is higher than the bottom height of the second source-drain doped layer 135; and an inner sidewall 140, located between the second source-drain doped layer 135 and the gate structure 150, where the outer side surface of the inner sidewall 135 is vertically flush with the end surface of the channel structure layer 300.

The substrate is used to provide a process platform for the formation of semiconductor structures. In the present embodiment, a full surrounding Gate (GAA) transistor is formed as an example. In other embodiments, the formation method may also be used to form a fork gate transistor (fork gate) or a Complementary Field Effect Transistor (CFET).

In the present embodiment, the substrate 100 is a silicon substrate, i.e. the material of the substrate 100 is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

In a specific implementation, the substrate 100 may include a first region I and a second region II, and the types of transistors formed on the first region I and the second region II may be different, and accordingly, source-drain doped layers formed on the respective regions may be different, that is, the second source-drain doped layer 135 and the first source-drain doped layer 130 may be different.

As a specific example, the first region I may be used to form an NMOS transistor, and the second region II may be used to form a PMOS transistor, and accordingly, the first source-drain doped layer 130 formed in the first region I is doped with a stress layer of N-type ions, wherein the material of the stress layer is Si or SiC; the second source-drain doped layer 135 formed in the second region II is doped with a stress layer of P-type ions, wherein the material of the stress layer is Si or SiGe. It will be appreciated that the first region I may also be used to form PMOS transistors and the second region II may also be used to form NMOS transistors.

Note that, in some embodiments of the present disclosure, the types of transistors formed on the first region I and the second region II may be the same. For example, the transistors formed in the first region I and the second region II are NMOS transistors or PMOS transistors. The present embodiment does not limit the types of transistors formed in the first region I and the second region II.

The channel structure layer 300 is used to provide a conductive channel of a field effect transistor. As an example, the channel structure layer 300 is a fin structure extending in the lateral direction.

In some embodiments of the present disclosure, as shown in fig. 8, in the channel structure layer 300, the number of the channel layers 30 is 2, and the stacking direction of the channel layers 30 is perpendicular to the surface of the substrate 100. In other embodiments, the channel layer may be other numbers.

The gate structure 150 is used to control the turning on and off of the conduction channel during operation of the device.

In this embodiment, the gate structure 150 is a metal gate structure, and the gate structure 150 includes a gate dielectric layer (not shown in fig. 8), a work function layer (not shown in fig. 8) on the gate dielectric layer, and a gate electrode layer (not shown in fig. 8) on the work function layer and filled in the first via (not shown in fig. 8), the second via (not shown in fig. 8), and the gate opening (not shown in fig. 8).

The gate dielectric layer is used for realizing electrical isolation between the work function layer and the gate electrode layer and the channel. The gate dielectric layer comprises silicon oxide, nitrogen doped silicon oxide and HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ And Al ₂ O ₃ One or more of the following. As an example, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may also be selected from ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ . In other embodiments, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.

The work function layer is used to adjust the work function of the gate structure 150 and thus the threshold voltage of the field effect transistor. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

The gate electrode layer serves as an external electrode for electrically connecting the gate structure 150 to an external circuit. The material of the gate electrode layer is a conductive material, for example: w, al, cu, ag, au, pt, ni or Ti, etc.

In the present embodiment, the gate structure 150 is described as an example of a metal gate structure. In other embodiments, the gate structure may also be other types of gate structures based on actual process requirements, such as: is a polysilicon gate structure or an amorphous silicon gate structure.

In the embodiment of the present disclosure, the gate structures 150 located in the first region I and the second region II each include: a first portion (not shown) located between adjacent channel layers 30 in the channel structure layer 300; a second portion (not shown) spans the channel structure layer 300. Correspondingly, the semiconductor structure further comprises: a first protection sidewall 115 located on sidewalls of the first portion and the second portion of the gate structure 150 of the first region I; and a second protection sidewall 116 located on a second portion of the sidewall of the gate structure 150 in the second region II.

In this embodiment of the present disclosure, the materials of the first protection sidewall 115 and the second protection sidewall 116 may include silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the first protection sidewall 115 and the second protection sidewall 116 have a single-layer or stacked-layer structure. As an example, the first protection sidewall 115 and the second protection sidewall 116 are of a single layer structure, and the materials may be silicon nitride.

In some embodiments of the present disclosure, the sidewall wall 140 may be used to achieve isolation between the second source-drain doped layer 135 and the gate structure 150, and further increase the distance between the second source-drain doped layer 135 and the gate structure 150, which is beneficial to reduce the parasitic capacitance between the second source-drain doped layer 135 and the gate structure 150.

In an embodiment, the material of the inner sidewall 140 is an insulating material to isolate the second source-drain doped layer 135 from the gate structure 150. In the embodiment of the present disclosure, the material of the inner sidewall 140 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low k dielectric material. As an example, the material of the inner sidewall 140 is silicon nitride.

The first and second source-drain doped layers 130 and 135 are used to serve as the source or drain of a field effect transistor, and the first and second source-drain doped layers 130 and 135 are used to provide a carrier source when the field effect transistor is operating.

In the present embodiment, the first source drain doped layer 130 and the second source drain doped layer 135 include stress layers doped with ions, and the stress layers serve to provide stress to the channel region, thereby improving mobility of carriers. Specifically, when forming the NMOS transistor, the first source-drain doped layer 130 and the second source-drain doped layer 135 include a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming the PMOS transistor, the first source drain doping layer 130 and the second source drain doping layer 135 include a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

It is understood that the first and second source-drain doped layers may be doped with completely different ion types to form transistors of different types on the first and second source-drain doped layers. For example, the first source-drain doped layer may be doped with a stress layer of N-type ions to form an NMOS transistor; the second source-drain doped layer can be doped with a stress layer of P-type ions to form the PMOS transistor.

With continued reference to fig. 8, as can be seen from fig. 8, the bottom height of the first source-drain doped layer 130 above the substrate 100 is higher than the bottom height of the second source-drain doped layer 135, that is, the height of the second source-drain doped layer 135 is greater than the first source-drain doped layer 130, so as to facilitate increasing the hole mobility of the second region II, and further increasing the current generated by the second region II, so that the current of the second region II tends to the current value of the first region I, and the current of the semiconductor device can be balanced.

In an embodiment of the present disclosure, the semiconductor structure further includes: an interlayer dielectric layer 145 is located above the first source-drain doped layer 130, the gate structure 150 on the first region I, and the second source-drain doped layer 135, the gate structure 150 on the second region II, and exposes the top of the gate structure 150.

Interlayer dielectric layer 145 is used to isolate adjacent devices. In the embodiment of the present disclosure, the material of the interlayer dielectric layer 145 is silicon oxide. The material of the interlayer dielectric layer 145 may also be other insulating materials.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 9 to 23 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Referring to fig. 9, a base is provided, including a substrate 100, the substrate 100 having a first region I and a second region II, on which a stack structure 200 is formed, respectively, the stack structure 200 including one or more channel stacks 210 stacked in sequence from bottom to top, each of the channel stacks 210 including a sacrificial layer 20 and a channel layer 30 on the sacrificial layer.

The substrate is used for providing a process platform for the subsequent process. In some embodiments of the present description, a full surrounding Gate (GAA) transistor is illustrated as an example. In other embodiments, the formation method may also be used to form a fork gate transistor (fork gate) or a Complementary Field Effect Transistor (CFET).

In a specific implementation, the substrate 100 may include a first region I and a second region II, and the types of transistors formed on the first region I and the second region II may be different, and accordingly, source-drain doped layers formed on the respective regions may be different, that is, a second source-drain doped layer (not shown in fig. 9) and a first source-drain doped layer (not shown in fig. 9) may be different.

As a specific example, the first region I may be used to form an NMOS transistor, and the second region II may be used to form a PMOS transistor, and accordingly, the first source-drain doped layer formed in the first region I is doped with a stress layer of N-type ions, where the material of the stress layer is Si or SiC; the second source-drain doped layer formed in the second region II is doped with a stress layer of P-type ions, wherein the material of the stress layer is Si or SiGe.

It is understood that the first region I may be used to form PMOS transistors and the second region II may be used to form NMOS transistors.

In the stacked structure 200, the stacking direction of the channel stack 210 is perpendicular to the surface of the substrate 100, and the channel stack 210 provides a process basis for forming the channel layer 30 disposed at intervals in the air. Specifically, the channel layer 30 is used to provide a conductive channel of the field effect transistor, the sacrificial layer 20 is used to support the channel layer 30, so as to provide a process foundation for the subsequent implementation of the spaced-apart suspended arrangement of the channel layer 30, and the sacrificial layer 20 is also used to occupy a space position for the subsequent formation of the gate structure.

As an example, the number of channel stacks 210 is 2. In other embodiments, the channel stack may be other numbers.

In the embodiment of the present disclosure, when different types of transistors are formed in different regions, materials used for the sacrificial layer 20 and the channel layer 30 are also different, specifically, when an NMOS transistor is formed, the material of the first channel layer 30 may be Si, and the material of the sacrificial layer 20 may be SiGe. In the subsequent process of removing the sacrificial layer 20, the etching selection of SiGe and Si is relatively high, so that the effect of the removal process of the sacrificial layer 20 on the channel layer 30 can be effectively reduced by setting the material of the sacrificial layer 20 to SiGe and setting the material of the channel layer 30 to Si, thereby improving the quality of the channel layer 30 and further being beneficial to improving the device performance.

In other embodiments, to enhance the performance of the PMOS transistor when forming the PMOS transistor, siGe channel technology may be used, where the material of the channel layer may be SiGe and the material of the sacrificial layer may be Si. In other embodiments, the material of the channel layer may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

Referring to fig. 10, dummy gate structures 110 are formed across the stacked structure 200 in the first region I and the second region II, respectively.

Specifically, the dummy gate structure 110 covers a portion of the top and a portion of the sidewall of the stack structure 200, and the dummy gate structure 110 extends in the longitudinal direction.

The dummy gate structure 110 is used to pre-occupy a spatial location for subsequent gate structure formation.

The dummy gate structure 110 may have a stacked structure or a single layer structure. In this embodiment of the present disclosure, the dummy gate structure 120 is a stacked structure, and includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) on the dummy gate oxide layer. Specifically, the dummy gate structure 110 is a polysilicon gate structure, the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the dummy gate layer may be polysilicon.

The specific steps of forming the dummy gate structure 110 include: forming a dummy gate structure material layer (not shown) on the stacked structure 200 and the substrate 100 of the first region I and the second region II, respectively; forming a patterned gate mask layer 105 on the dummy gate structure material layer; the dummy gate structure material layer is etched using the gate mask layer 105 as a mask, exposing a portion of the top wall of the stacked structure 200, and the remaining dummy gate structure material layer serves as the dummy gate structure 110.

The gate mask layer 105 is used as a mask during the formation of the dummy gate structure 110.

In the embodiment of the present disclosure, the gate mask layer 105 has a stacked structure. For example, the gate mask layer 105 may include a first mask layer 1051, a second mask layer 1052 over the first mask layer 1051, and a third mask layer 1053 over the second mask layer 1052. In other embodiments, the gate mask layer may also have a single-layer structure. The embodiments of the present disclosure do not limit the specific structure of the gate mask layer.

Referring to fig. 11, the method for forming the semiconductor structure further includes: before forming the first capping layer 120 (refer to fig. 12), a first protection sidewall 115 is formed on the sidewall of the dummy gate structure 110 in the first region I, and a second protection sidewall 116 is formed on the sidewall of the dummy gate structure 110 in the second region II.

The first protection sidewall 115 is used together with the dummy gate structure 110 as an etching mask for a subsequent etching process for forming a groove to define a formation position of the first source/drain doped layer, the second protection sidewall 116 is used together with the dummy gate structure 110 as an etching mask for a subsequent etching process for forming a groove to define a formation position of the second source/drain doped layer, and the first protection sidewall 115 and the second protection sidewall 116 are also used for protecting sidewalls of the dummy gate structure 110 and the subsequent gate structure.

In some embodiments of the present disclosure, the materials of the first protection sidewall 115 and the second protection sidewall 116 include silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the first protection sidewall 115 and the second protection sidewall 116 may have a single-layer or stacked-layer structure. As an example, the first protection sidewall 115 and the second protection sidewall 116 are of a single-layer structure, and the materials of the first protection sidewall 115 and the second protection sidewall 116 are silicon nitride.

Referring to fig. 12, a first capping layer 120 is formed at the second region II to cover the substrate 100 and the dummy gate structure 110.

By forming the first cover layer 120 to cover the second region II, only the substrate 100, the dummy gate structure 110, and the stacked structure 200 in the first region I can be processed, and the first source/drain doped layer 130 can be generated (as shown in fig. 13).

Specifically, the first capping layer 120 may be formed using an atomic layer deposition process. The atomic layer deposition process has a high step coverage capability, which is advantageous for depositing a first capping layer material layer on the substrate 100 and on the top and sidewalls of the dummy gate structure 110, and is also advantageous for improving thickness uniformity of the first capping layer material layer.

In some embodiments of the present disclosure, the material of the first cover layer 120 may include: one or more of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxide. As a specific example, the material of the first cover layer 120 may be silicon oxide.

Referring to fig. 13, a first source drain doping layer 130 is formed on the substrate 100 on both sides of the stack structure 200 and the dummy gate structure 110 of the first region I.

The first source-drain doped layer 130 is used as a source or a drain of the field effect transistor, and the first source-drain doped layer 130 is used for providing a carrier source when the field effect transistor works.

In some embodiments of the present disclosure, the first source-drain doped layer 130 includes a stress layer doped with ions, the stress layer being used to provide stress to the channel region, thereby improving the mobility of carriers. Specifically, when forming the NMOS transistor, the first source-drain doped layer 130 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming the PMOS transistor, the first source drain doped layer 130 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

Specifically, an epitaxial process may be used to perform epitaxial growth based on the stacked structure 200 of the first region I and the sidewall of the first protection sidewall 115, to form a stress layer on the substrate 100, and to dope ions during the formation of the stress layer, where the stress layer doped with ions is used as the first source/drain doped layer 130.

In a specific implementation, the morphology and the size of the first source-drain doped layer 130 may be adjusted according to actual requirements based on actual process requirements.

Thereafter, a second source drain doping layer 135 (shown in fig. 19) may be formed over the substrate 100 on both sides of the stack structure 200 and the dummy gate structure 110 of the second region II.

Referring to fig. 14, a second capping layer 125 is formed on the first region I to cover the first source and drain doped layer 130 and the dummy gate structure 110, and the first capping layer 120 on the second region II is removed.

The process of forming the second cover layer 25 and the type of material used may refer to the foregoing description of the first cover layer 120, and will not be repeated herein.

In a specific implementation, a dry etching process may be used to remove the first capping layer 120 on the second region II.

In a specific implementation, the second cover layer 125 may be formed first, and the first cover layer 120 is removed; the first cover layer 120 may be removed first, and the second cover layer 125 may be formed; alternatively, the second cover layer 125 is formed while the first cover layer 120 is removed. In an embodiment of the present disclosure, the second cover layer 125 may be formed first, and the first cover layer 120 is removed, so as to avoid the false etching of the dummy gate structure 110 on the first area I when the first cover layer 120 is removed.

Referring to fig. 15, the sacrificial layer 20 of the predetermined first thickness in the channel stack 200 on the second region II is removed to form a trench 25.

After the first cover layer 120 on the second area II is removed, the sacrificial layer 20 of the stacked structure 200 on the second area II can be exposed, and the sacrificial layer 20 with the preset first thickness is etched by using an anisotropic etching process along the lateral direction (parallel to the extending direction of the sacrificial layer 20) to form the trench 25. The trench 25 is surrounded by an adjacent channel layer 30 and the sacrificial layer 20, wherein the trench 25 is used to provide a space for forming an inner sidewall and a barrier layer later.

In some embodiments of the present disclosure, a vapor etching process may be specifically used to etch the sacrificial layer 20 having the first thickness along the lateral direction. The vapor etching process is an isotropic etching process, and can etch the sacrificial layer 20 along the lateral direction, and the vapor etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the sacrificial layer 20 and reducing the probability of damaging other film structures (such as the channel layer 30).

In the embodiment of the present disclosure, the material of the sacrificial layer 20 is SiGe, the material of the channel layer 30 is Si, and the sacrificial layer 20 on the sidewall of the recess 230 is vapor etched by HCl vapor. The etching rate of the HCl vapor to the SiGe material is much greater than that to the Si material, which effectively reduces the chance of damage to the channel layer 30.

In other embodiments, when the material of the first channel layer is SiGe and the material of the sacrificial layer is Si, a dry etching process may be used to etch the sacrificial layer on the sidewall of the recess along the lateral direction. The etchant of the dry etching process may include CF ₄ 、O ₂ 、N ₂ Is a mixture of plasmas of (a) and (b). The difference between the etching rate of the plasma mixture to Si and the etching rate to SiGe is large, and the channel layer can be effectively reducedProbability of loss.

In a specific implementation, etching is performed along the transverse sacrificial layer, the first thickness of the etching is not too small, and too large, if the width of the first thickness of the etching is too small, the thicknesses of the inner side wall and the barrier layer formed subsequently are easy to be small, and when the etching process is performed subsequently, the inner side wall and the barrier layer can be completely removed, and the sacrificial layer is damaged, so that the performance of the formed semiconductor device is poor; if the width of the etched first thickness is too large, the thicknesses of the inner side wall and the barrier layer which are formed later are easy to be larger, and the difficulty of forming the second source-drain doped layer later is increased. For this reason, in the embodiment of the present specification, the first thickness is 90% to 95% of the thickness of the sacrificial layer.

In a specific implementation, to avoid complete removal of the sacrificial layer 20 in the second region II, referring to fig. 16, a barrier layer is formed within the trench 25 of the second region II. Wherein the barrier layer may protect the sacrificial layer 20.

Specifically, a barrier material layer (not shown in fig. 16) covering the substrate 100, the sidewalls of the stacked structure 200, the trench 25, and the top and sidewalls of the dummy gate structure 110 may be formed on the second region II using an atomic layer deposition process; thereafter, the barrier material layer outside the trench 25 is removed by an isotropic etching process, and the remaining barrier material layer serves as the barrier layer 35.

Wherein an atomic layer deposition process is used to facilitate the deposition of a barrier material layer on the substrate 100, the sidewalls of the stacked structure 200, the trenches 25, and the top and sidewalls of the dummy gate structure 110, and to improve the thickness uniformity of the barrier material layer. In other embodiments, chemical vapor deposition may also be used to form the barrier material layer.

In a specific implementation, the material of the barrier layer 35 and the material of the sacrificial layer 20 may have a larger selective etching ratio, so that the probability of the sacrificial layer 20 being damaged can be effectively reduced when the barrier layer 35 is subsequently removed.

As a specific example, the material of the barrier layer may include: one or more of silicon oxide, silicon nitride, or silicon oxynitride.

In practical application, in order to realize the isolation between the subsequently formed second source-drain doped layer and the gate structure, the distance between the gate structure and the second source-drain doped layer is properly increased, and the parasitic capacitance between the gate structure and the second source-drain doped layer is reduced. Referring to fig. 17, the method for forming a semiconductor structure further includes: an inner sidewall 140 is formed at the remaining portion of the trench 25, and an outer side surface of the formed inner sidewall 140 is vertically flush with an end surface of the channel layer 30. The inner sidewall 140 is used for protecting the sidewall of the channel layer 30, so as to reduce the probability of damaging the channel layer 30.

In some embodiments of the present disclosure, the inner sidewall 140 is made of a material having etching selectivity to the material of the channel layer 30, so that the inner sidewall 140 can protect the channel layer 30 in a subsequent process, and in a subsequent process of removing the inner sidewall 140, the inner sidewall 140 has a higher etching selectivity ratio with other film layers, so as to reduce the difficulty of removing the inner sidewall 140, and reduce the damage to other film layers.

In the embodiment of the present disclosure, the material of the inner sidewall 140 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon oxycarbide, silicon carbonitride, and silicon boron carbonitride.

In some embodiments of the present disclosure, the step of forming the inner side wall 140 includes: forming a conformally covered inner sidewall material layer (not shown) on the bottom and sidewalls of the recess 25; and removing the inner side wall material layer at the top of the channel stack 200 exposed by the grooves 25, and taking the remaining inner side wall material layer as an inner side wall.

In a specific implementation, the inner sidewall material layer may be formed using an atomic layer deposition process. The atomic layer deposition process has a high step coverage capability, which is advantageous for depositing an inner sidewall material layer on the bottom and the sidewall of the recess 25, and also for improving the thickness uniformity of the inner sidewall material layer.

In a specific implementation, an anisotropic etching process is used to remove the sidewall material layer exposed in the recess 25.

As described above, in the prior art, the source and drain doped layers of different regions are generated simultaneously, and the heights of the generated source and drain doped layers are uniform, which results in unbalanced current of the finally formed semiconductor device. For this, referring to fig. 18, the channel layer 30 and a portion of the substrate 100 of the channel stack 200 having the predetermined second thickness are removed from the second region II before the second region II is formed with the second source/drain doped layer.

In a specific implementation, a selective etching process may be used to remove the channel layer 30 and a portion of the substrate 100 with a predetermined second thickness in the channel stack 200 on the second region II. I.e. the part of the substrate 100 in the second region II is lower than the substrate 100 in the first region I.

In a specific implementation, the vapor etching process is one of selective etching processes, and is capable of etching the channel layer 30 and the substrate 100 in the second region II in the lateral direction, and the vapor etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the channel layer 30 and reducing the probability of damaging other film structures.

In some embodiments of the present disclosure, the second thickness of the channel layer of the second region II may be pseudo 5-10nm by using a selective etching process.

Referring to fig. 19, a second source drain doping layer 135 is formed over the stack structure of the second region and the substrate on both sides of the dummy gate structure.

The second source-drain doped layer 135 is used as a source or a drain of the field effect transistor, and the second source-drain doped layer 135 is used to provide a carrier source when the field effect transistor operates.

In some embodiments of the present disclosure, the second source drain doped layer 135 includes a stress layer doped with ions, which is used to provide stress to the channel region, thereby improving the mobility of carriers. Specifically, when forming the NMOS transistor, the second source-drain doped layer 135 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming the PMOS transistor, the second source drain doping layer 135 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

In a specific implementation, a second source-drain doped layer 135 may be formed on the stacked structure 200, the dummy gate structure 110, and the substrate 100 on both sides of the dummy gate structure 110 in the second region II by using an epitaxial process. Specifically, an epitaxial process may be used to perform epitaxial growth based on the stacked structure 200 of the second region II and the sidewall of the second protection sidewall 116, so as to form a stress layer on the substrate 100, and dope ions in the process of forming the stress layer, where the stress layer doped with ions is used as the second source-drain doped layer 135.

In a specific implementation, the morphology and the size of the second source-drain doped layer 135 may be adjusted according to the actual process requirements.

Referring to fig. 19 and 13 in combination, the bottom height of the first source-drain doped layer 130 above the substrate 100 is higher than the bottom height of the second source-drain doped layer 135, that is, the height of the second source-drain doped layer 135 is higher than the first source-drain doped layer 130, so as to facilitate increasing the hole mobility of the second region II, and thus increasing the current generated by the second region II, so that the current of the second region II tends to the current value of the first region I, and the current of the semiconductor device can be balanced.

As previously shown, the substrate 100 of the first region I and the second region II includes a plurality of stacked structures 200 thereon, and only a portion of the stacked structures may be required to form the gate structure during actual operation, and if adjacent devices are in direct contact, a short circuit may be caused. Thus, in the embodiments of the present disclosure, the stacked structure for forming the gate structure may be exposed and the adjacent devices may be isolated.

Referring to fig. 20, the method for forming the semiconductor structure further includes: after forming the second source-drain doped layer 135, an interlayer dielectric layer 145 is formed over the first source-drain doped layer 130, over the dummy gate structure 110, and over the second source-drain doped layer 135, over the dummy gate structure 110 over the first region I, before forming the gate opening.

Wherein the interlayer dielectric layer 145 exposes the top of the dummy gate structure 110 to facilitate subsequent removal of the dummy gate structure 110.

Specifically, the following steps may be adopted to form the interlayer dielectric layer: removing the second cover layer 125 on the first region I to expose the dummy gate structure 110 on the first region I; forming an interlayer dielectric material layer (not shown in fig. 19) covering the substrate 100, the first source drain doping layer 130, the dummy gate structure 110, and the second source drain doping layer 134 over the first region I and the second region II; and etching the interlayer dielectric material layer by taking the top of the dummy gate structure 110 as an etching stop layer, and sequentially removing the interlayer dielectric material layer, the gate mask layer, part of the first protection side wall and part of the second protection side wall until the top of the dummy gate structure 110 is exposed, wherein the rest of the interlayer dielectric material layer is taken as an interlayer dielectric layer 145.

The interlayer dielectric layer 145 is used for isolating adjacent devices, and is also used for supporting the channel layer 30 in the process of removing the dummy gate structure 120 and the sacrificial layer 20 later, so as to realize suspended interval arrangement of the channel layer 30. In the embodiment of the present disclosure, the material of the interlayer dielectric layer 145 is silicon oxide. The material of the interlayer dielectric layer 145 may also be other insulating materials.

Referring to fig. 21, the dummy gate structures 110 on the first region I and the second region II are removed, and a gate opening 170 is formed to expose the stacked structure 200.

The gate opening 170 is used to provide a spatial location for forming the gate structure. The gate opening 170 exposes the stack 200 to facilitate subsequent removal of the sacrificial layer 20 in the channel stack 210 in the first region I and removal of the sacrificial layer 20 and the barrier layer in the channel stack 210 in the first region II through the gate opening 170.

In the present embodiment, the gate opening 170 spans the stacked structure 200.

Referring to fig. 22, the sacrificial layer 20 in the channel stack is removed on the first region I to form a first through groove 160, and the sacrificial layer 20 and the barrier layer 35 in the channel stack are removed on the second region II to form a second through groove 165, wherein the first through groove 160 and the second through groove 165 are surrounded by the channel layer 30 and the substrate 100 or are surrounded by adjacent channel layers 30.

The first through-slot 160 and the gate opening 170 together provide a spatial location for forming a gate structure on the first region I, the second through-slot 165 and the gate opening 170 together provide a spatial location for forming a gate structure on the first region II, and the first through-slot 160 is in communication with the gate opening 170, and the second through-slot 165 is in communication with the gate opening 170.

In some embodiments of the present disclosure, after the sacrificial layer 20 is removed on the first region I and the sacrificial layer 20 and the barrier layer 35 are removed on the second region II, when the number of the channel layers 30 is plural, the plural channel layers 30 are disposed at intervals, so as to form the channel structure layer 300.

In a specific implementation, a anisotropic etching process may be used to remove the sacrificial layer 20 in the channel stack 200 in the first region I, form the first through-slot 160, and remove the sacrificial layer 20 and the barrier layer 35 in the channel stack 200 in the second region II, so as to form the second through-slot 165. Specifically, a vapor etch process may be employed to remove the sacrificial layer 20 and the barrier layer 35. Specifically, the material of the channel layer 30 is Si, and the material of the sacrificial layer 20 is SiGe, so that the sacrificial layer 20 exposed by the gate opening 123 is removed by HCl vapor, and the HCl vapor has a high etching selectivity ratio between SiGe and Si, which is beneficial to improving the removal efficiency of the sacrificial layer 20 and reducing the probability of damage to the channel layer 30.

Referring to fig. 23, a gate structure 150 is filled in the gate opening 170, the first via 160, and the second via 165, and the gate structure 150 surrounds and spans the channel layer 300. The gate structure 150 is used to control the turning on and off of the conduction channel during operation of the device.

In this embodiment, the gate structure 150 is a metal gate structure, and the gate structure 150 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filled in the first through trench 160, the second through trench 165, and the gate opening 170.

The gate dielectric layer is used for realizing electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The gate dielectric layer comprises silicon oxide, nitrogen doped silicon oxide and HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ And Al ₂ O ₃ One or more of the following.

In this embodiment of the present disclosure, the gate dielectric layer includes a high-k gate dielectric layer, and a material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ . In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate, comprising: a substrate having a first region and a second region;

the channel structure layers are respectively positioned above the substrates of the first area and the second area and comprise one or more channel layers which are sequentially arranged at intervals from bottom to top;

a gate structure crossing the channel structure layer on the first region and the second region, respectively, wherein: the gate structure ring located in the first region surrounds the channel layers arranged at intervals and fills the space between the substrate and the adjacent channel layers; the gate structure ring located in the second region surrounds the channel layers arranged at intervals and fills the space between the substrate and the channel layers adjacent to the channel layers arranged at intervals;

The first source-drain doped layer is positioned on the channel structure layer of the first region and the substrate at two sides of the grid structure;

the second source-drain doping layer is positioned on the substrate at the two sides of the channel structure layer and the grid structure of the second region, wherein the bottom height of the first source-drain doping layer above the substrate is higher than the bottom height of the second source-drain doping layer;

the inner side wall is positioned between the second source-drain doping layer and the grid structure, and the outer side face of the inner side wall is vertically flush with the end face of the channel structure layer.

2. The semiconductor structure of claim 1, wherein the second source drain doped layer and the first source drain doped layer are different.

3. The semiconductor structure of claim 1, wherein the gate structures in the first region and the second region each comprise: a first portion located between adjacent ones of the channel structure layers; a second portion crossing the channel structure layer;

the semiconductor structure further includes: the first protection side wall is positioned on the side walls of the first part and the second part of the grid structure in the first region;

And the second protection side wall is positioned on the side wall of the second part of the grid structure in the second region.

4. The semiconductor structure of claim 1, wherein the gate structures in the first region and the second region each comprise a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

5. The semiconductor structure of claim 1, further comprising an interlayer dielectric layer over the first source drain doped layer on the first region, over the gate structure, and over the second source drain doped layer on the second region, over the gate structure, and exposing a top of the gate structure.

6. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a first area and a second area, a laminated structure is formed on the first area and the second area respectively, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, and each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer;

forming a dummy gate structure crossing the laminated structure in the first region and the second region respectively;

Forming a first covering layer covering the substrate and the dummy gate structure in the second region;

forming a first source-drain doping layer on the laminated structure of the first region and the substrates at two sides of the pseudo gate structure;

forming a second covering layer covering the first source-drain doping layer and the pseudo gate structure in the first region, and removing the first covering layer on the second region;

removing the sacrificial layer with the preset first thickness in the channel lamination layer on the second area to form a groove;

forming a barrier layer in the groove of the second region;

forming an inner side wall at the rest part of the groove, wherein the outer side surface of the formed inner side wall is vertically flush with the end surface of the channel layer;

removing a channel layer and a part of substrate with preset second thickness in the channel laminated layer on the second area;

forming a second source-drain doping layer on the laminated structure of the second region and the substrates at two sides of the pseudo gate structure;

removing the pseudo gate structures on the first region and the second region to form a gate opening, and exposing the laminated structure;

removing the sacrificial layer in the channel stack layer on the first region to form a first through groove, and removing the sacrificial layer and the blocking layer in the channel stack layer on the second region to form a second through groove, wherein the first through groove and the second through groove are both surrounded by the channel layer and the substrate or are surrounded by adjacent channel layers;

And filling a gate structure in the gate opening, the first through groove and the second through groove, wherein the gate structure surrounds and spans the channel layer.

7. The method of claim 6, wherein the first source drain doped layer and the second source drain doped layer are different.

8. The method of claim 6, wherein the trench is formed by removing a sacrificial layer of a predetermined first thickness from the channel stack over the second region using an anisotropic etching process.

9. The method of forming a semiconductor structure according to claim 6 or 8, wherein the first thickness is 90% to 95% of the thickness of the sacrificial layer.

10. The method of claim 6, wherein forming a barrier layer in the trench of the second region comprises:

forming a barrier material layer covering the substrate, the side wall of the laminated structure, the groove and the top and side wall of the pseudo gate structure on the second region by adopting an atomic layer deposition process;

and removing the barrier material layer outside the groove by adopting an isotropic etching process, and taking the rest barrier material layer as the barrier layer.

11. The method of forming a semiconductor structure according to claim 6 or 10, wherein the material of the barrier layer comprises: one or more of silicon oxide, silicon nitride, or silicon oxynitride.

12. The method of claim 6, wherein a selective etching process is used to remove a predetermined second thickness of the channel layer and a portion of the substrate in the channel stack over the second region.

13. The method of forming a semiconductor structure according to claim 6 or 12, wherein the second thickness is 5-10nm.

14. The method of claim 6, wherein a second source-drain doped layer is formed on the stacked structure, the dummy gate structure, and the substrate on both sides of the dummy gate structure in the second region by an epitaxial process.

15. The method of claim 6, wherein the sacrificial layer in the channel stack is removed in the first region by a anisotropic etching process to form a first via, and the sacrificial layer and the barrier layer in the channel stack are removed in the second region to form a second via.

16. The method of forming a semiconductor structure of claim 6, further comprising: removing the second covering layer on the first region after the second source-drain doped layer is formed and before the gate opening is formed; and forming an interlayer dielectric layer on the first source/drain doped layer on the first region, the second source/drain doped layer on the dummy gate structure and the dummy gate structure, wherein the interlayer dielectric layer exposes the top of the dummy gate structure.

17. The method of forming a semiconductor structure of claim 6, further comprising: before the first covering layer is formed, a first protection side wall is formed on the side wall of the pseudo gate structure in the first area, and a second protection side wall is formed on the side wall of the pseudo gate structure in the second area.