CN114068706B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114068706B CN114068706B CN202010762886.9A CN202010762886A CN114068706B CN 114068706 B CN114068706 B CN 114068706B CN 202010762886 A CN202010762886 A CN 202010762886A CN 114068706 B CN114068706 B CN 114068706B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
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- 238000005530 etching Methods 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
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- 239000010703 silicon Substances 0.000 claims description 36
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
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- 229910052582 BN Inorganic materials 0.000 claims description 6
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and method of forming the same, the method comprising: providing a substrate, wherein an initial channel laminated layer is formed on the substrate, and the extending direction of the initial channel laminated layer is a first direction; forming a dummy gate structure across the initial channel stack, the dummy gate structure comprising a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack; removing the initial channel stacks at two sides of the pseudo gate structure to form a target channel stack; forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with a channel layer in the target channel stack; after the doped structures are formed on the two sides of the pseudo gate structure, a gate structure is formed in the space occupied by the pseudo gate structure and the sacrificial layer in the target channel stack, and the performance of the device is improved.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed metal gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed metal gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
The full gate nanowire can be obtained by adding only two process modules in the existing replacement gate fin field effect transistor (FinTET) process flow, wherein the two process modules are as follows: firstly, a layer of Silicon is grown on bulk Silicon (bulk Silicon) or SOI wafer, so that the leakage of bulk Silicon materials can be avoided. Second, the sige is selectively removed on a replaceable metal gate loop, and then a HKMG (high-k insulating layer + metal gate) stack is used to surround the silicon channel to form a fully enclosed metal gate transistor.
However, the devices formed by the prior art have poor performance.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which improves the performance of a device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein an initial channel stack layer is formed on the substrate, the extending direction of the initial channel stack layer is a first direction, and the initial channel stack layer comprises a plurality of sacrificial layers and a plurality of channel layers which are alternately stacked;
forming a dummy gate structure across the initial channel stack, the dummy gate structure comprising a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack;
Removing the initial channel stacks at two sides of the pseudo gate structure to form a target channel stack;
forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with a channel layer in the target channel stack;
after forming doped structures on two sides of the dummy gate structure, forming a gate structure in a space occupied by the dummy gate structure and the sacrificial layer in the target channel stack.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises:
a substrate;
a gate structure on the substrate, comprising a top gate structure having a first dimension along the first direction and a bottom gate structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the first direction being perpendicular to an extension direction of the gate structure;
a channel stack intersecting the gate structure, the channel stack including a plurality of channel layers traversing the gate structure, and sidewalls of the channel layers being exposed on both sides of the gate structure;
and the doped structures are positioned at two sides of the gate structure and are connected with the side wall of the channel layer exposed by the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
According to the embodiment of the invention, the pseudo gate structure with large bottom structure size and small top structure size is formed, so that the gate structure formed by the subsequent process has the same size characteristics, more current in the gate structure is distributed at the bottom of the gate structure when the device works, the current density uniformity of the gate structure is improved, the control capability of the gate structure on a channel is further enhanced, the starting resistance of the bottom channel when the channel is started is correspondingly reduced, and the current density uniformity of a drain region in the source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, thereby improving the device performance.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 20 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 21 to 32 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the performance of the device formed at present is not good, and the reason of the poor performance of the device is analyzed by combining a method for forming a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown. As shown in fig. 1, the base comprises a substrate 1 and a fin 2 protruding from the substrate 1; the source-drain doped layer 3 is separated on the fin part 2; an initial channel stack layer 4 suspended between the source-drain doped layers 3 and in contact with the source-drain doped layers 3, the initial channel stack layer 4 including a sacrificial layer 41 and a channel layer 42 on the sacrificial layer 41; a metal gate structure 5 crossing the initial channel stack 4 on the fin 2 and surrounding the initial channel stack 4; and the interlayer dielectric layer 6 covers the source-drain doped layer 3 and the side wall of the metal gate structure 5.
However, when the device is in operation, the current in the metal gate structure 5 gradually decreases along the direction from the top to the bottom of the metal gate structure 5, so that the control capability of the metal gate structure 5 on the channel gradually decreases, and further the current flowing from the drain region in the source-drain doped layer to the source region in the source-drain doped layer through the channel layer gradually decreases. Clearly, the density uniformity of the device current of this structure is not high, resulting in poor device performance.
In view of this, embodiments of the present invention provide a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, wherein an initial channel laminated layer is formed on the substrate, and the extending direction of the initial channel laminated layer is a first direction; forming a dummy gate structure across the initial channel stack, the dummy gate structure comprising a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack; removing the initial channel stacks at two sides of the pseudo gate structure to form a target channel stack; forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with a channel layer in the target channel stack; and after forming doping structures on two sides of the pseudo gate structure, forming a gate structure in a space occupied by the pseudo gate structure and the sacrificial layer.
By forming the pseudo gate structure with large bottom structure size and small top structure size, the gate structure formed by the subsequent process has the same size characteristics, so that more current in the gate structure is distributed at the bottom of the gate structure when the device works, the current density uniformity of the gate structure is improved, the control capability of the gate structure on a channel is further improved, the starting resistance of the bottom channel is correspondingly reduced, and the current density uniformity of a drain region in the source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, thereby improving the device performance.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 20 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2 to 4 in combination, in which fig. 2 is a top view, fig. 3 is a cross-sectional view of fig. 2 in the AA 'direction, and fig. 4 is a cross-sectional view of fig. 2 in the BB' direction, a substrate is provided, and as shown in fig. 2, the substrate 100 is formed with an initial channel stack 120, and an extension direction (X direction in the drawing) of the initial channel stack 120 is a first direction.
The substrate 100 is used to provide a process platform for forming device structures, and the initial channel stack 120 on the substrate 100 is used to provide a process basis for subsequently forming a target channel stack.
In an embodiment of the present invention, the base 100 may include a substrate 101 and a fin 102 protruding from the substrate. The material of the substrate 101 may be silicon. In other embodiments, the material of the substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, the material of the fin portion is a semiconductor material, and the material of the fin portion may be the same as the substrate or different from the material of the substrate.
Also, in other embodiments, the substrate may further include a first semiconductor layer for providing a process basis for subsequently forming the substrate and a second semiconductor layer epitaxially grown on the first semiconductor layer for providing a process basis for subsequently forming the fin
The initial channel stack 120 includes a plurality of sacrificial layers 121 and a plurality of channel layers 122 that are alternately stacked, and in the initial channel stack 120, the number of the sacrificial layers 121 and the channel layers 122 that are alternately stacked may be the same or different, specifically, the initial channel stack may include 3 sacrificial layers and 2 channel layers that are alternately stacked, or the initial channel stack may include 4 sacrificial layers and 3 channel layers that are alternately stacked, which is illustrated in this embodiment as including 4 sacrificial layers 121 and 3 channel layers 122 that are alternately stacked in the initial channel stack 120.
With continued reference to fig. 5, fig. 5 is a cross-sectional view from the perspective of fig. 3, after the step of providing a substrate, an isolation layer 103 may be further formed, where the isolation layer 103 covers the exposed substrate of the fin 102.
The isolation layer 103 is used to electrically isolate the individual fins 102 from each other.
In this embodiment, the isolation layer 103 covers the substrate 101 exposed by the fin 102. The material of the isolation layer 103 includes silicon oxide. In other embodiments, the material of isolation layer 103 may also include one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
It should be noted that, the top surface of the isolation layer 103 is not higher than the top surface of the fin 102, which is beneficial to the subsequent etching of the initial channel stack 120.
In this embodiment of the present invention, after the isolation layer 103 is formed, a dummy gate oxide layer (not shown in the drawing) may be further formed on a portion of the top surface and a portion of the sidewall of the initial channel stack 120, where the material of the dummy gate oxide layer is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
Referring to fig. 6 to 8, wherein fig. 6 is a top view, fig. 7 is a cross-sectional view in the BB 'direction of fig. 6, and fig. 8 is a cross-sectional view in the CC' direction of fig. 6, a dummy gate structure 130 is formed across the initial channel stack 120.
The dummy gate structure 130 occupies a space for a gate structure to be formed in a subsequent process. The extending direction (Y direction in the drawing) of the dummy gate structure 130 may be perpendicular to the extending method of the initial channel stack 120.
The dummy gate structure 130 includes a top structure having a first dimension D1 along the first direction X and a bottom structure having a second dimension D2 along the first direction X, the first dimension D1 being smaller than the second dimension D2, the dummy gate structure 130 covering a portion of the sidewalls and top of the initial channel stack 120; wherein, the dummy gate structure with the top structure size smaller than the bottom structure size (i.e. inverted T shape) is formed for forming the gate structure with the same shape characteristics in the subsequent process, thereby improving the performance of the device.
When the spacer 103 is formed in this embodiment, a dummy gate structure 130 is formed on the spacer 103 across the initial channel stack 120.
In an alternative example, the step of forming the dummy gate structure 130 may include: forming a dummy gate material layer (not shown) covering a side of the substrate having the initial channel stack; forming a patterned first pseudo gate mask layer on the pseudo gate material layer, wherein the first pseudo gate mask layer comprises at least one first mask pattern, and the dimension of the first mask pattern along the first direction is a second dimension; etching the pseudo gate material layer by taking the first pseudo gate mask layer as a mask to form an initial pseudo gate structure; forming a patterned second dummy gate mask layer 131 on the initial dummy gate structure, the second dummy gate mask layer including at least one second mask pattern, the second mask pattern having a first dimension along a first direction; and etching the second pseudo gate mask layer to remove part of the initial pseudo gate structure with the thickness to form a pseudo gate structure with the top size of the first size and the bottom size of the second size, wherein the part with the first size is used as the top structure of the pseudo gate structure, and the part with the second size is used as the bottom structure of the pseudo gate structure.
It should be noted that the thickness of the bottom structure and the top structure is determined according to the preset size of the gate structure. The second dummy gate mask layer 131 may remain in a subsequent step to protect the top of the dummy gate structure 130.
The material of the dummy gate structure 130 may be polysilicon. In other embodiments, the material of the dummy gate structure may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the dummy gate material layer may be formed by an epitaxial growth process.
After forming the dummy gate structure 130 crossing the initial channel stack 120 in the embodiment of the present invention, referring to fig. 9, where fig. 9 is a cross-sectional view of fig. 8, a sidewall 140 may be further formed on two sides of the dummy gate structure, where a thickness of the sidewall on a side of the top structure is greater than a thickness of the sidewall on a side of the bottom structure, and a difference between the thickness of the sidewall on the side of the bottom structure and the thickness of the sidewall on the side of the top structure is equal to 1/2 of a difference between the second dimension D2 and the first dimension D1, that is, (D2-D1)/2, so that a side of the sidewall facing away from the side of the dummy gate structure is a plane.
The sidewall 140 is used for protecting the sidewall of the dummy gate structure 130 and defining the formation region of the source/drain doped region in the subsequent process.
In the embodiment of the present invention, the dummy gate structure 130 is in an inverted T shape, so that the side walls formed on two sides of the dummy gate structure may be thicker at the top and thinner at the bottom, so that the side surface of the side wall facing away from one side of the dummy gate structure is a plane, and preferably, the plane may be perpendicular to the surface of the substrate.
Furthermore, in order to ensure the thickness uniformity of the side wall in the finally formed device, the two materials of the embodiment of the invention form the side wall, so that one material in the side wall can be selectively removed in the subsequent process, and only the other material in the side wall is reserved.
Specifically, the step of forming side walls on two sides of the dummy gate structure includes: forming a first side wall material layer which conformally covers one side of the substrate with the pseudo gate structure; forming a second side wall material layer which conformally covers the first side wall material layer, wherein the thickness of the second side wall material layer is larger than or equal to the difference value between the second dimension and the first dimension; and removing the top of the pseudo gate structure, the first side wall material layer and the second side wall material layer on the surface of the substrate, and the second side wall material layer protruding from the side surface of the pseudo gate structure, and forming side walls on two sides of the pseudo gate structure. The remaining first sidewall material layer is used as the first sidewall 141, and the remaining second sidewall material layer is used as the second sidewall 142.
The material of the first side wall material layer and the second side wall material layer may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the materials of the first side wall material layer and the second side wall material layer are different.
The sidewall material layer may be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or an atomic layer deposition (Atomic Layer Deposition, ALD) process.
It is understood that, based on the characteristics that the bottom structure of the dummy gate structure is large in size and the top structure is small in size, after the first side wall material layer and the second side wall material layer are formed on two sides of the dummy gate structure, a step structure with a protruding bottom is formed on two sides of the dummy gate structure based on the shape of the dummy gate structure, and based on the difference value between the second size and the first size and the thickness of the second side wall material layer, the step structure is only a partial structure of the second side wall material layer, so that the side wall with a protruding side face away from one side of the dummy gate structure is formed by removing the first side wall material layer and the second side wall material layer on the surface of the substrate.
And in the step of removing the top of the pseudo gate structure, the first side wall material layer and the second side wall material layer on the surface of the substrate, and the second side wall material layer protruding from the side surface of the pseudo gate structure, a dry etching process can be adopted to remove the corresponding structure.
Next, referring to fig. 10 to 11, wherein fig. 10 is a top view, fig. 11 is a cross-sectional view along BB 'in fig. 10, and initial channel stacks on both sides of the dummy gate structure 130 are removed to form a target channel stack 120';
in the embodiment of the present invention, the dummy gate structure 130 and the sidewall 140 may be used as masks, and the initial channel stacks on both sides of the dummy gate structure may be removed. In this embodiment, the second dummy gate mask layer 131 is remained on the top of the dummy gate structure, and then the second dummy gate mask layer 131 and the side wall 140 are used as masks to remove the initial channel stacks on both sides of the dummy gate structure.
And removing the initial channel stacks at the two sides of the pseudo gate structure by adopting a dry etching process, a wet etching process or a combination of the dry etching process and the wet etching process, and keeping the initial channel stacks at the intersection positions of the pseudo gate structure and the side walls as target channel stacks. Wherein the target channel stack is comprised of a remaining sacrificial layer 121 'and a remaining channel layer 122'.
And removing the initial channel stacks at the two sides of the pseudo gate structure, and providing a process space for forming the doped structure, and exposing the side walls at the two sides of the target channel stack at the same time so as to facilitate the subsequent etching of the exposed sacrificial layer at the side surfaces of the target channel stack.
In an alternative example, a portion of the fin under the initial channel stack may be further removed at the same time as the initial channel stack is removed, so that a recess is formed in the fin to accommodate a portion of the doping structure.
Referring to fig. 12, the sacrificial layer exposed by the sidewalls of the target channel stack is etched such that the remaining sacrificial layer sides form a receiving space 150 defined by the channel layer adjacent to the sacrificial layer;
the receiving space 150 is used to provide a space for the subsequent formation of the inner side wall.
In this embodiment, a wet etching process or a dry etching process may be used to etch the sacrificial layer exposed on the sidewall of the target channel stack, thereby forming the accommodating space.
Specifically, the side wall of the sacrificial layer in the target channel stack layer with partial thickness can be etched and removed, so that an accommodating space surrounded by the channel layer and the residual sacrificial layer, or surrounded by the channel layer, the residual sacrificial layer and the fin portion, or surrounded by the channel layer, the residual sacrificial layer and the side wall is formed.
Referring to fig. 13, a sidewall 151 is formed in the receiving space 150.
The inner sidewall 151 is used for isolating gate structures and doped structures formed on two sides of the inner sidewall, and providing support for the suspended channel layer in the subsequent process.
The material of the inner sidewall 151 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride or boron carbonitride, and optionally, the material of the inner sidewall may be the same as the material of the first sidewall material layer.
Referring to fig. 14, a doped structure 160 is formed on both sides of the dummy gate structure 130, the doped structure 160 being contiguous with the channel layer 122' in the target channel stack;
the doped structure 160 is used as a source/drain structure of the device, and is used together with a gate structure of the device to control the device.
The doped structure 160 may be silicon, and in other embodiments, the doped structure may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the doped structure 160 is formed by an epitaxial process.
When the device is an NMOS device, the doped ions in the doped structure are N-type ions, wherein the N-type ions can be P ions, as ions or Sb ions; when the device is a PMOS device, the doped ions In the doped structure are P-type ions, which may be B ions, ga ions, or In ions.
In order to ensure uniformity of the device sidewall thickness, the second sidewall layer 142 in the sidewall may be further removed after the doped structure is formed. Specifically, the second sidewall layer 142 may be removed by wet etching, dry etching, or a combination thereof.
Referring to fig. 15 to 20, a gate structure is formed in a space occupied by the dummy gate structure and the sacrificial layer in the target channel stack.
The grid structure is used as a grid of the device to perform corresponding control. In the embodiment of the invention, the grid structure can be formed in the space occupied by the dummy grid structure and the sacrificial layer by removing the dummy grid structure and the sacrificial layer.
Specifically, the step of forming the gate structure in the space occupied by the dummy gate structure and the sacrificial layer may include:
referring to fig. 15, an interlayer dielectric layer 170 is formed flush with the top of the dummy gate structure;
the interlayer dielectric layer 170 is used for realizing electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 170 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 170 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Specifically, the step of forming the interlayer dielectric layer 170 includes: forming an interlayer dielectric material layer (not shown) on the dummy gate structure and the exposed part of the dummy gate structure, wherein the interlayer dielectric material layer covers the top of the dummy gate structure; and carrying out planarization treatment on the interlayer dielectric material layer, and removing the interlayer dielectric material layer higher than the pseudo gate structure, wherein the remaining interlayer dielectric material layer after the planarization treatment is used as the interlayer dielectric layer 160.
In this embodiment, in conjunction with fig. 11 and 12, the second dummy gate mask layer 131 is also removed at the same time during the planarization process.
Referring to fig. 16 to 18, wherein fig. 16 is a top view, fig. 17 is a cross-sectional view along the direction CC ' in fig. 16, fig. 18 is a cross-sectional view along the direction BB ' in fig. 16, the dummy gate structure is removed, and a gate trench 181 is formed, and the gate trench 181 exposes a portion of the target channel stack 120' covered by the dummy gate structure.
The gate trench 181 forms a process space for filling the conductive gate, wherein the dummy gate structure is based on covering a portion of the target channel stack 120', and in this embodiment, the gate trench 181 exposes a portion of the target channel stack 120' covered by the dummy gate structure.
Wherein, the dummy gate structure can be removed by an etching process, such as a wet etching process or a combination of a wet etching process and a dry etching process. Specifically, when etching is performed by a wet etching process, HCl solution may be used.
Referring to fig. 19, wherein fig. 19 is a view of fig. 18, the sacrificial layer in the target channel stack is removed, and a gate channel 182 communicating with the gate trench 181 is formed between the channel layers 122' in the target channel stack.
In the embodiment of the present invention, after the gate trench 181 is formed, the sacrificial layer in the target channel stack layer is removed, so that the channel layer is suspended in the gate trench, and the subsequently formed gate structure surrounds the channel layer. It is understood that the channel layer 122' is supported by the inner sidewalls on both sides of the gate trench.
Specifically, the sacrificial layer in the initial channel stack may be removed using a dry etching process, a wet etching process, or a combination of both.
Referring to fig. 20, a gate structure 190 is formed in the gate trench 181 and the gate channel 182.
The gate structure 190 may include a gate dielectric layer 191 and a conductive gate 192.
In this embodiment of the present invention, specifically, a gate dielectric material layer conformally covering the gate trench and the gate channel may be first deposited in the gate trench and the gate channel, and after the gate dielectric material layer is formed, a conductive gate material layer may be further deposited, and the conductive gate material layer may completely cover the gate trench and the gate channel, then, the gate dielectric material layer and the conductive gate material layer outside the gate trench may be removed, the remaining gate dielectric material layer may be used as the gate dielectric layer 191, and the remaining conductive gate material layer may be used as the conductive gate 192.
In this embodiment, the material of the gate dielectric layer 191 may be a high-k dielectric layer, and the material of the high-k dielectric layer refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 191 is made of HfO 2 . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
The conductive gate 192 is a metal gate structure, and in this embodiment, the material of the metal gate structure is magnesium-tungsten alloy. In other embodiments, the material of the metal gate structure may also be W, al, cu, ag, au, pt, ni or Ti.
In the embodiment of the invention, the pseudo gate structure with large bottom structure size and small top structure size is formed, so that the gate structure formed by the subsequent process has the same size characteristics, more current in the gate structure is distributed at the bottom of the gate structure when the device works, the current density uniformity of the gate structure is improved, the control capability of the gate structure on a channel is further enhanced, the starting resistance of the bottom channel is correspondingly reduced when the channel is started, and the current density uniformity of a drain region in the source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, thereby improving the device performance.
In another embodiment of the present invention, a method for forming a semiconductor structure is provided, where the method forms a sacrificial layer with different etching rates in the same etching process, so that the sacrificial layer formed in the target channel stack layer is matched with the size of the dummy gate structure, and further forms a gate structure with a corresponding size, thereby improving the performance of the device.
Fig. 21 to 32 are schematic structural views corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 21 to 25 in combination, a substrate 200 is provided, the substrate 200 being formed with an initial channel stack having an extension direction of a first direction.
The substrate 200 is used to provide a process platform for forming device structures, and an initial channel stack on the substrate 200 is used to provide a process basis for subsequently forming a target channel stack.
The initial channel stack includes a plurality of sacrificial layers 221 and a plurality of channel layers 222 alternately stacked. Wherein the sacrificial layer 221 includes a first sacrificial layer 221A corresponding to a top structure of the dummy gate structure and a second sacrificial layer 221B corresponding to a bottom structure of the dummy gate structure, and an etching rate of the first sacrificial layer 221A is greater than an etching rate of the second sacrificial layer 221B in a first etching process.
The etching rate of the first sacrificial layer 221A is greater than that of the second sacrificial layer 221B, so that the first sacrificial layer 221A located at the top layer of the initial channel stack may be removed by using a first etching process in a subsequent step to occupy a smaller process space, and the second sacrificial layer 221B located at the bottom layer of the initial channel stack may be removed by using a first etching process in a subsequent step to occupy a larger process space, thereby forming sacrificial layers with different sizes in the same etching process.
The materials of the first sacrificial layer and the second sacrificial layer can be different, or the materials of the first sacrificial layer and the second sacrificial layer are the same, and the component contents of the materials are different, so that the first sacrificial layer and the second sacrificial layer have different etching rates in the same etching process. Alternatively, to reduce the complexity of the process, the materials of the first sacrificial layer and the second sacrificial layer may be the same, and the component contents of the materials may be different.
In this embodiment, the first sacrificial layer and the second sacrificial layer may be made of silicon germanium material, and the germanium content of the first sacrificial layer is greater than that of the second sacrificial layer, so that the etching of the sacrificial layer may be performed by using HCl solution or HCl vapor, so that in the same time, the first sacrificial layer is etched by a larger amount in the HCl solution or HCl vapor, and the second sacrificial layer is etched by a smaller amount, so that sacrificial layers with different sizes are formed in the same etching process.
Specifically, the difference between the percentage value of the germanium content of the first sacrificial layer and the percentage value of the germanium content of the second sacrificial layer may be 5% to 20%.
In this embodiment, the base 200 may include a substrate 201 and a fin 202 protruding from the substrate, and correspondingly, the process of forming the initial channel stack on the base 200 may include:
referring to fig. 21, an initial substrate 20 is provided;
referring to fig. 21 to 25 in combination, the initial substrate 20 is used to provide a process platform for the subsequent formation of a stacked material layer, and further the substrate and the fin protruding from the substrate are formed by removing a portion of the thickness of the initial substrate 20 in a portion of the area.
In this embodiment, the material of the initial substrate 20 is silicon. In other embodiments, the material of the initial substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
In addition, in other embodiments, the initial substrate may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used to provide a process basis for subsequently forming the substrate, and the second semiconductor layer is used to provide a process basis for subsequently forming the fin.
Next, referring to fig. 22, a stacked material layer is formed on the initial substrate 20;
the stacked material layer includes a plurality of sacrificial material layers 211 and a plurality of channel material layers 212 alternately stacked, wherein the sacrificial material layers 211 include at least one first sacrificial material layer 211A located on top of the stacked material layers and at least one second sacrificial material layer 211B located on bottom of the stacked material layers. The stacked material layer is used for forming an initial channel stack by removing the stacked material layer in a part of the area, the first sacrificial material layer 211A provides a process basis for forming the first sacrificial layer, the second sacrificial material layer 211B provides a process basis for forming the second sacrificial layer, and the channel material layer 212 is used for providing a process basis for forming the channel layer.
In the first etching process, the etching rate of the first sacrificial material layer is larger than that of the second sacrificial material layer, so that the first sacrificial layer and the second sacrificial layer which are formed on the basis of the first sacrificial material layer and the second sacrificial material layer subsequently have corresponding etching rates.
The number of layers of the sacrificial material layer 211 and the channel material layer 212 in the stacked material layer is matched with the number of sacrificial layers and channel layers to be formed, and when 4 sacrificial layers and 3 channel layers are alternately stacked in the initial channel stack of this embodiment, the stacked material layer correspondingly includes 4 sacrificial material layers and 3 channel material layers.
In this embodiment, an Epitaxial Growth process (epi-axial Growth) is used to form a stacked material layer on the initial substrate 20. The lattice structure of the semiconductor is not easy to damage by adopting an epitaxial growth process, so that the subsequently formed semiconductor structure is not easy to leak electricity.
In this embodiment, the process of forming the stacked material layer by using the epitaxial growth process may include a stage of forming a sacrificial material layer and a stage of forming a channel material layer, in which the introduced epitaxial gas is different between the stage of forming the sacrificial material layer and the stage of forming the channel material layer; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gas is the same, and the flow rate of the introduced epitaxial gas is different.
The method comprises the steps of controlling different epitaxial gases to be introduced into the device for forming the sacrificial material layers and the channel material layers with different materials, and controlling the flow of the epitaxial gases to be introduced into the device for forming the first sacrificial material layers and the second sacrificial material layers with different components so as to be convenient for removing the first sacrificial layers formed by the first sacrificial material layers and the second sacrificial layers formed by the second sacrificial material layers with different quantities in the subsequent etching steps.
In the present embodiment, the material of the sacrificial material layer 211 is silicon germanium, and the material of the channel material layer 212 is silicon. Specifically, the step of forming the stacked material layer on the substrate using an epitaxial growth process may include: forming a second sacrificial material layer, wherein epitaxial gases introduced in the second sacrificial material layer forming stage are germane and silane; forming a channel material layer, wherein epitaxial gas introduced in the channel material layer forming stage is silane; and forming a first sacrificial material layer, wherein epitaxial gases introduced in the first sacrificial material layer forming stage are germane and silane, and the flow rate of the germane introduced in the first sacrificial material layer forming stage is larger than that of the germane introduced in the second sacrificial material layer forming stage.
Next, referring to fig. 23 to 25, in which fig. 23 is a top view, fig. 24 is a cross-sectional view along the AA 'direction in fig. 23, fig. 25 is a cross-sectional view along the BB' direction in fig. 23, a part of the stacked material layer in the partial region and a part of the thickness of the initial substrate located in the partial region are removed, the initial substrate with the remaining thickness is taken as a substrate 201, the initial substrate protruding from the substrate is taken as a fin 202, and the remaining stacked material layer located on the fin 202 is taken as an initial channel stack.
The stacked material layer in the partial region and the initial substrate of partial thickness in the partial region are removed to achieve patterning of the stacked material layer and the initial substrate, thereby forming a substrate 201 and a fin 202 protruding from the substrate, and an initial channel stack on the fin 202.
In this embodiment, the substrate 201 and the fin 202 protruding from the substrate, and the initial channel stack on the fin 202 may be implemented in one patterning process. Specifically, the process of the substrate 201, the fin 202 protruding from the substrate, and the initial channel stack on the fin 202 includes: forming a patterned first mask layer (not shown in the figure) on the stacked material layer, wherein the first mask layer covers a preset area for forming the fin part and exposes other areas except the area; and etching and removing the stacked material layer in the exposed area of the first mask layer and the initial substrate with partial thickness in the partial area by taking the first mask layer as a mask.
Wherein the first mask layer may be a photoresist layer or a hard mask layer, and in this embodiment, the hard mask layer is preferably selected, and the material of the hard mask layer may be silicon nitride (SiN), silicon oxide (SiO) 2 ) One or more of silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxycarbonitride (SiOCN), and when a plurality of materials are used, the hard mask layer may be a stack of a plurality of material layers. In this embodiment, the material of the hard mask layer may be silicon nitride. And, after forming the initial channel stack, the first mask layer may remain in a subsequent step to continue to protect the top surface of the initial channel stack in the subsequent step.
In the formed initial channel stack, the remaining channel material layer is taken as a channel layer 222, and the remaining sacrificial material layer is taken as a sacrificial layer 221, wherein the first sacrificial material layer remaining in the initial channel stack is taken as a first sacrificial layer 221A, and the second sacrificial material layer remaining in the initial channel stack is taken as a second sacrificial layer 221B.
Further, after the step of removing the stacked material layer in the partial region and the initial substrate with the partial thickness in the partial region, an isolation layer may be further formed, where the isolation layer covers the substrate exposed by the fin portion.
In the embodiment of the present invention, after the isolation layer is formed, the first mask layer may be removed, and further a dummy gate oxide layer (not shown in the figure) may be formed on a portion of the top surface and a portion of the sidewall of the initial channel stack layer, where the material of the dummy gate oxide layer is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
Referring to fig. 26, wherein fig. 26 is a cross-sectional view of the view of fig. 25, a dummy gate structure 230 is formed across the initial channel stack, the dummy gate structure 230 covering a portion of the sidewalls and top of the initial channel stack.
Where an isolation layer is formed in this embodiment, a dummy gate structure 230 is formed on the isolation layer across the initial channel stack.
In the embodiment of the present invention, the cross section of the formed dummy gate structure 230 is illustrated as an inverted T shape. In particular, the dummy gate structure 230 may include a top structure having a first dimension along a first direction and a bottom structure having a second dimension along the first direction, the first dimension being smaller than the second dimension.
It should be noted that the thicknesses of the bottom structure and the top structure are determined according to the size of the preset gate structure, and the thicknesses of the bottom structure and the top structure are matched with the layer structure in the initial channel stack. Specifically, the thickness of the bottom structure is matched with the height of the highest sacrificial layer with the same etching rate as the first sacrificial layer in the initial channel stack, so that a gate structure with the consistent extension shape is formed in the subsequent process.
In forming the dummy gate structure 230, the dummy gate structure 230 may be formed through multiple patterning and etching processes, and in this example, the mask layer 231 located on top of the dummy gate structure may be reserved for use as a mask, so that after the top structure of the dummy gate structure is etched, the top of the dummy gate structure may be further included.
After forming the dummy gate structure crossing the initial channel stack in the embodiment of the present invention, referring to fig. 27, it may further include forming side walls 240 on both sides of the dummy gate structure, where the thickness of the side wall located on the side surface of the top structure is greater than that of the side wall located on the side surface of the bottom structure, and the difference between the thickness of the side wall located on the side surface of the bottom structure and that of the side wall located on the side surface of the top structure is equal to 1/2 of the difference between the second dimension and the first dimension, so that the side surface of the side wall facing away from the side of the dummy gate structure is a plane. The side walls 240 may include a first side wall 141 conformally covering the side walls of the dummy gate structure and a second side wall 242 filled outside the first side wall.
Next, referring to fig. 28, removing the initial channel stacks on both sides of the dummy gate structure to form a target channel stack;
In the embodiment of the invention, the initial channel stacks at two sides of the dummy gate structure can be removed by taking the dummy gate structure and the side walls as masks. Wherein the target channel stack is composed of a remaining sacrificial layer 221' and a remaining channel layer 222', and the remaining sacrificial layer 221' is composed of a remaining first sacrificial layer 221A ' and a remaining second sacrificial layer 221B '.
Next, referring to fig. 29, the sacrificial layer exposed from the sidewalls of the target channel stack is etched using a first etching process, and a receiving space 250 defined by a channel layer adjacent to the sacrificial layer is formed at the side of the remaining sacrificial layer.
The receiving space 250 is used to provide a space for the subsequent formation of the inner side wall.
And on the basis that the etching rate of the first sacrificial layer in the first etching process is greater than that of the second sacrificial layer, the sacrificial layers in the target channel stacks exposed at the two sides of the pseudo gate structure are etched by adopting the first etching process, more first sacrificial layers can be removed at the same time, and less second sacrificial layers are removed, so that the sacrificial layers with different sizes are formed in the first etching process at the same time.
Further, the dimension of the remaining first sacrificial layer in the etched target channel stack layer along the first direction may be greater than or equal to the first dimension, and the dimension of the remaining second sacrificial layer along the first direction may be less than or equal to the second dimension, where the dimension of the remaining first sacrificial layer along the first direction is greater than or equal to the first dimension, so that the gate structure formed in this space further improves the gate control capability of the device, and the dimension of the remaining second sacrificial layer along the first direction is less than or equal to the second dimension, which may enable formation of a void protruding out of the cross section of the dummy gate structure to be avoided, and further may enable a hole to appear at the bottom of the gate structure formed subsequently.
In the first etching process, the sacrificial layer exposed by the side wall of the target channel stack layer can be etched by adopting HCl solution or HCl steam. When the sacrificial layer exposed on the side wall of the target channel lamination is etched by adopting HCl solution, the concentration of the HCl solution can be 5% -20%.
It can be appreciated that after the first etching process is adopted, the accommodating space 250A formed on the side of the remaining first sacrificial layer is larger than the accommodating space 250B formed on the side of the remaining second sacrificial layer.
Referring to fig. 30, an inner sidewall 251 is formed in the receiving space.
The inner sidewall 251 is used for isolating gate structures and doped structures formed on both sides of the inner sidewall, and providing support for the suspended channel layer in the subsequent process.
Based on the embodiment, the accommodating space formed on the side surface of the first sacrificial layer is larger, correspondingly, the thickness of the inner side wall formed in the accommodating space is larger, the accommodating space formed on the side surface of the second sacrificial layer is smaller, and correspondingly, the thickness of the inner side wall formed in the accommodating space is smaller.
Referring to fig. 31, a doping structure 260 is formed at both sides of the dummy gate structure, the doping structure 260 being connected to a channel layer in the target channel stack.
Referring to fig. 32, a gate structure 290 is formed in the space occupied by the dummy gate structure and the sacrificial layer.
The gate structure 290 includes a gate dielectric layer 291 and a conductive gate 292, and an interlayer dielectric layer 270 is also formed during the formation of the gate structure.
The description of each step in this embodiment may refer to the description in the foregoing embodiment, and the present invention is not repeated here.
In the embodiment of the invention, the sacrificial layer formed in the target channel lamination is matched with the size of the pseudo gate structure, so that the size of the gate structure formed at the target channel lamination is matched with the size of the gate structure formed at the pseudo gate structure, and the performance of the device is improved. Meanwhile, the sacrificial layers with different etching rates are formed, so that the sacrificial layers with different sizes are formed in the same etching process, the process is simplified, and the process cost is reduced.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 32, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure comprises:
a substrate 200;
a gate structure 290 on the substrate, including a top gate structure having a first dimension along the first direction and a bottom gate structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the first direction being perpendicular to an extension direction of the gate structure;
A channel stack intersecting the gate structure 290, the channel stack including a plurality of channel layers 222 'traversing the gate structure, and sidewalls of the channel layers 222' being exposed on both sides of the gate structure 290;
the doped structure 260 is located at two sides of the gate structure 290, and the doped structure 260 is connected with the exposed sidewall of the channel layer 222' of the gate structure 290.
Optionally, the semiconductor structure further includes: a first sidewall 241 located on both sides of the gate structure 290 and an inner sidewall 251 located between the doped structure 260 and the gate structure 290.
Optionally, the thickness of the inner sidewall 251 located at the side of the top gate structure is greater than the thickness of the inner sidewall 251 located at the side of the bottom gate structure.
Optionally, the materials of the first side wall 241 and the inner side wall 251 are the same, and the materials of the first side wall 241 and the inner side wall 251 are one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride or boron carbonitride.
The gate structure 290 includes a gate dielectric layer 291 and a conductive gate 292, and the two sides of the gate structure are further provided with an interlayer dielectric layer 270 flush with the gate structure.
According to the embodiment of the invention, the bottom gate structure of the gate structure is large in size, and the top gate structure is small in size, so that more current in the gate structure is distributed at the bottom of the gate structure when the device works, the current density uniformity of the gate structure is improved, the control capability of the gate structure on a channel is further enhanced, the starting resistance of the bottom channel is correspondingly reduced, and the current density uniformity of a drain region in a source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, so that the device performance is improved.
The semiconductor structure according to the embodiment of the present invention may be formed by the forming method of the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein an initial channel stack layer is formed on the substrate, the extending direction of the initial channel stack layer is a first direction, and the initial channel stack layer comprises a plurality of sacrificial layers and a plurality of channel layers which are alternately stacked; forming a dummy gate structure across the initial channel stack, the dummy gate structure comprising a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack;
removing the initial channel stacks at two sides of the pseudo gate structure to form a target channel stack;
forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with a channel layer in the target channel stack;
after forming doped structures on two sides of the dummy gate structure, forming a gate structure in a space occupied by the dummy gate structure and the sacrificial layer in the target channel stack.
2. The method of forming a semiconductor structure of claim 1, wherein after forming a dummy gate structure across the initial channel stack, before removing the initial channel stack on both sides of the dummy gate structure, further comprising:
And forming side walls on two sides of the pseudo gate structure, wherein the thickness of the side wall positioned on the side surface of the top structure is larger than that of the side wall positioned on the side surface of the bottom structure, and the thickness difference between the side wall positioned on the side surface of the bottom structure and the side wall positioned on the side surface of the top structure is equal to 1/2 of the difference between the second dimension and the first dimension.
3. The method for forming a semiconductor structure according to claim 2, wherein forming side walls on both sides of the dummy gate structure comprises:
forming a first side wall material layer which conformally covers one side of the substrate with the pseudo gate structure;
forming a second side wall material layer which conformally covers the first side wall material layer, wherein the thickness of the second side wall material layer is larger than or equal to the difference value between the second dimension and the first dimension;
and removing the top of the pseudo gate structure, the first side wall material layer and the second side wall material layer on the surface of the substrate, and the second side wall material layer protruding from the side surface of the pseudo gate structure, and forming side walls on two sides of the pseudo gate structure.
4. The method of forming a semiconductor structure of claim 3, wherein after forming a doped structure on both sides of the dummy gate structure, the method further comprises, prior to forming a gate structure:
And removing the second side wall material layer in the side wall.
5. The method of forming a semiconductor structure of claim 1, wherein said forming a dummy gate structure across said initial channel stack comprises:
forming a dummy gate material layer covering a side of the substrate having the initial channel stack;
forming a patterned first pseudo gate mask layer on the pseudo gate material layer, wherein the first pseudo gate mask layer comprises at least one first mask pattern, and the dimension of the first mask pattern along the first direction is a second dimension;
etching the pseudo gate material layer by taking the first pseudo gate mask layer as a mask to form an initial pseudo gate structure; forming a patterned second dummy gate mask layer on the initial dummy gate structure, wherein the second dummy gate mask layer comprises at least one second mask pattern, and the dimension of the second mask pattern along the first direction is a first dimension;
and etching the second pseudo gate mask layer to remove part of the initial pseudo gate structure with the thickness to form a pseudo gate structure with the top size of the first size and the bottom size of the second size, wherein the part with the first size is used as the top structure of the pseudo gate structure, and the part with the second size is used as the bottom structure of the pseudo gate structure.
6. The method of forming a semiconductor structure of claim 1, wherein after removing the initial channel stack on both sides of the dummy gate structure, the method further comprises, prior to forming a doped structure on both sides of the dummy gate structure:
etching the exposed sacrificial layer on the side wall of the target channel stack layer to enable the side surface of the remaining sacrificial layer to form an accommodating space defined by the channel layer adjacent to the sacrificial layer;
and forming an inner side wall in the accommodating space.
7. The method of forming a semiconductor structure of claim 6, wherein the sacrificial layer comprises a first sacrificial layer corresponding to a top structure of the dummy gate structure and a second sacrificial layer corresponding to a bottom structure of the dummy gate structure, an etch rate of the first sacrificial layer being greater than an etch rate of the second sacrificial layer in a first etch process.
8. The method of claim 7, wherein the first sacrificial layer and the second sacrificial layer are silicon germanium and the germanium content of the first sacrificial layer is greater than the germanium content of the second sacrificial layer.
9. The method of forming a semiconductor structure of claim 8, wherein a difference between a percentage value of germanium content of the first sacrificial layer and a percentage value of germanium content of the second sacrificial layer is between 5% and 20%.
10. The method of forming a semiconductor structure of claim 7, wherein the base comprises a substrate and a fin protruding from the substrate, the step of forming an initial channel stack on the base comprising;
providing an initial substrate;
forming a stacked material layer on the initial substrate, the stacked material layer comprising a plurality of sacrificial material layers and a plurality of channel material layers that are alternately stacked, wherein the sacrificial material layers comprise at least one first sacrificial material layer on top of the stacked material layer and at least one second sacrificial material layer on bottom of the stacked material layer; in a first etching process, the etching rate of the first sacrificial material layer is greater than that of the second sacrificial material layer;
and removing the stacked material layer in the partial region and the initial substrate with partial thickness in the partial region, taking the initial substrate with residual thickness as a substrate, taking the initial substrate protruding out of the substrate as a fin part, taking the residual stacked material layer as an initial channel lamination, wherein the first sacrificial material layer remained in the initial channel lamination is a first sacrificial layer, and the second sacrificial material layer remained in the initial channel lamination is a second sacrificial layer.
11. The method of forming a semiconductor structure of claim 10, wherein an epitaxial growth process is employed to form a stacked material layer on the initial substrate; wherein, in the stage of forming the sacrificial material layer and the stage of forming the channel material layer, the introduced epitaxial gas is different; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gas is the same, and the flow rate of the introduced epitaxial gas is different.
12. The method of claim 7, wherein the first etching process is used to etch the exposed sacrificial layer on the sidewall of the target channel stack such that the remaining first sacrificial layer has a dimension in the first direction greater than or equal to the first dimension and the remaining second sacrificial layer has a dimension in the first direction less than or equal to the second dimension.
13. The method of claim 7, wherein the first etching process etches the sacrificial layer using HCl solution or HCl vapor.
14. The method of forming a semiconductor structure as claimed in claim 6, wherein the step of removing the initial channel stacks on both sides of the dummy gate structure comprises removing the initial channel stacks on both sides of the dummy gate structure using the dummy gate structure and the sidewalls as masks.
15. The method of forming a semiconductor structure of claim 1, wherein forming a gate structure within a space occupied by the dummy gate structure and a sacrificial layer in the target channel stack comprises:
forming an interlayer dielectric layer which is flush with the top of the pseudo gate structure;
removing the pseudo gate structure to form a gate trench, wherein the gate trench exposes a part of the target channel stack covered by the pseudo gate structure;
removing the sacrificial layer in the target channel stack, and forming a gate channel communicated with the gate groove between channel layers in the target channel stack;
a gate structure is formed in the gate trench and the gate channel.
16. The method of claim 3, wherein the material of the first sidewall material layer and the second sidewall material layer is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the materials of the first sidewall material layer and the second sidewall material layer are different.
17. A semiconductor structure, comprising:
a substrate;
A gate structure on the substrate, comprising a top gate structure having a first dimension along a first direction and a bottom gate structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the first direction being perpendicular to an extension direction of the gate structure;
a channel stack intersecting the gate structure, the channel stack including a plurality of channel layers traversing the gate structure, and sidewalls of the channel layers being exposed on both sides of the gate structure;
the doped structures are positioned at two sides of the grid structure and are connected with the side wall of the channel layer exposed by the grid structure;
and the inner side wall is positioned between the doping structure and the grid electrode structure, and the dimension of the bottom grid electrode structure positioned between the inner side walls along the first direction is smaller than the second dimension.
18. The semiconductor structure of claim 17, further comprising: and the first side walls are positioned at two sides of the grid structure.
19. The semiconductor structure of claim 18, wherein a thickness of the sidewall wall on a side of the top gate structure is greater than a thickness of the sidewall wall on a side of the bottom gate structure.
20. The semiconductor structure of claim 19, wherein the first sidewall and the inner sidewall are the same material, and the material of the first sidewall and the inner sidewall is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
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| JPS62136883A (en) * | 1985-12-06 | 1987-06-19 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Manufacture of self-aligning field effect transistor |
| CN110265301A (en) * | 2018-03-12 | 2019-09-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106009A (en) * | 2018-10-26 | 2020-05-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| US9893171B2 (en) * | 2016-06-03 | 2018-02-13 | International Business Machines Corporation | Fin field effect transistor fabrication and devices having inverted T-shaped gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS62136883A (en) * | 1985-12-06 | 1987-06-19 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Manufacture of self-aligning field effect transistor |
| CN110265301A (en) * | 2018-03-12 | 2019-09-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106009A (en) * | 2018-10-26 | 2020-05-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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