CN114068706A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN114068706A CN114068706A CN202010762886.9A CN202010762886A CN114068706A CN 114068706 A CN114068706 A CN 114068706A CN 202010762886 A CN202010762886 A CN 202010762886A CN 114068706 A CN114068706 A CN 114068706A
- Authority
- CN
- China
- Prior art keywords
- layer
- gate structure
- forming
- sacrificial
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 123
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 238000003475 lamination Methods 0.000 claims abstract description 47
- 239000010410 layer Substances 0.000 claims description 441
- 239000000463 material Substances 0.000 claims description 174
- 238000005530 etching Methods 0.000 claims description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 239000011229 interlayer Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052582 BN Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 238000002955 isolation Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910000078 germane Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- NTCVORQAIAUAJB-UHFFFAOYSA-N [Mg].[W] Chemical compound [Mg].[W] NTCVORQAIAUAJB-UHFFFAOYSA-N 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and method of forming the same, the method comprising: providing a substrate, wherein an initial channel lamination layer is formed on the substrate, and the extending direction of the initial channel lamination layer is a first direction; forming a dummy gate structure across the initial channel stack, the dummy gate structure including a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being less than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack; removing the initial channel lamination layers on the two sides of the pseudo gate structure to form a target channel lamination layer; forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with the channel layer in the target channel lamination; after doping structures are formed on two sides of the pseudo gate structure, a gate structure is formed in a space occupied by the pseudo gate structure and a sacrificial layer in the target channel lamination, and performance of the device is improved.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the fully-surrounded metal gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the fully-surrounded metal gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.
The full-gate nanowire can be obtained by adding only two process modules in the existing replacement gate fin field effect transistor (FinTET) process flow, wherein the two process modules are as follows: one is to grow a layer of Silicon on bulk Silicon (bulk Silicon) or SOI wafer, which avoids leakage of bulk Silicon material. Second, selectively remove the silicon germanium on the replaceable metal gate loop, and then use HKMG (high-k insulating layer + metal gate) to stack the surrounding silicon channel to form the all-around metal gate transistor.
However, the performance of the devices formed by the current process is not good.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which improve the performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein an initial channel lamination layer is formed on the substrate, the extending direction of the initial channel lamination layer is a first direction, and the initial channel lamination layer comprises a plurality of sacrificial layers and a plurality of channel layers which are alternately stacked;
forming a dummy gate structure across the initial channel stack, the dummy gate structure including a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being less than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack;
removing the initial channel lamination layers on the two sides of the pseudo gate structure to form a target channel lamination layer;
forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with the channel layer in the target channel lamination;
and forming a gate structure in a space occupied by the dummy gate structure and the sacrificial layer in the target channel lamination after forming doping structures on two sides of the dummy gate structure.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including:
a substrate;
the gate structure is positioned on the substrate and comprises a top gate structure with a first size along the first direction and a bottom gate structure with a second size along the first direction, the first size is smaller than the second size, and the first direction is vertical to the extending direction of the gate structure;
a channel stack intersecting the gate structure, the channel stack including a plurality of channel layers traversing the gate structure, and sidewalls of the channel layers being exposed on both sides of the gate structure;
and the doped structures are positioned on two sides of the grid structure and connected with the side wall of the channel layer exposed by the grid structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the pseudo-gate structure with the large bottom structure size and the small top structure size is formed, so that the gate structure formed in the subsequent process has the same size characteristic, and thus, when the device works, more current in the gate structure is distributed at the bottom of the gate structure, the current density uniformity of the gate structure is improved, further, the control capability of the gate structure on a channel is enhanced, the opening resistance when the channel at the bottom is opened is correspondingly reduced, the current density uniformity of a drain region in a source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, and the performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 20 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention;
fig. 21 to 32 are schematic structural views corresponding to steps in another embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is not good, and the reason for the poor performance of the devices is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown. As shown in fig. 1, the base includes a substrate 1 and a fin portion 2 protruding from the substrate 1; the source drain doping layer 3 is separated on the fin part 2; the initial channel lamination layer 4 is suspended between the source-drain doping layers 3 and is in contact with the source-drain doping layers 3, and the initial channel lamination layer 4 comprises a sacrificial layer 41 and a channel layer 42 positioned on the sacrificial layer 41; a metal gate structure 5 spanning the initial channel stack 4 on the fin 2 and surrounding the initial channel stack 4; and the interlayer dielectric layer 6 covers the source-drain doping layer 3 and the side wall of the metal gate structure 5.
However, when the device operates, the current in the metal gate structure 5 gradually decreases along the direction from the top of the metal gate structure 5 to the bottom thereof, so that the control capability of the metal gate structure 5 on the channel gradually decreases, and the current flowing from the drain region in the source-drain doped layer to the source region in the source-drain doped layer through the channel layer gradually decreases. Obviously, the device current of such a structure has low uniformity in density, resulting in poor device performance.
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, wherein an initial channel lamination layer is formed on the substrate, and the extending direction of the initial channel lamination layer is a first direction; forming a dummy gate structure across the initial channel stack, the dummy gate structure including a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being less than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack; removing the initial channel lamination layers on the two sides of the pseudo gate structure to form a target channel lamination layer; forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with the channel layer in the target channel lamination; and forming a gate structure in the space occupied by the dummy gate structure and the sacrificial layer after forming doping structures on two sides of the dummy gate structure.
By forming the pseudo-gate structure with the large bottom structure size and the small top structure size, the gate structure formed by the subsequent process has the same size characteristic, so that when the device works, more current in the gate structure is distributed at the bottom of the gate structure, the current density uniformity of the gate structure is improved, the control capability of the gate structure on a channel is enhanced, the opening resistance when the channel at the bottom is opened is correspondingly reduced, the current density uniformity of a drain region in a source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, and the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to fig. 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2 to 4 in combination, wherein fig. 2 is a top view, fig. 3 is a cross-sectional view along AA 'in fig. 2, and fig. 4 is a cross-sectional view along BB' in fig. 2, a substrate is provided, as shown in fig. 2, the substrate 100 is formed with an initial channel stack 120, and an extending direction (X direction in the figure) of the initial channel stack 120 is a first direction.
The substrate 100 is used to provide a process platform for forming a device structure, and the initial channel stack 120 on the substrate 100 is used to provide a process base for subsequently forming a target channel stack.
In the embodiment of the present invention, the substrate 100 may include a substrate 101 and a fin 102 protruding from the substrate. The material of the substrate 101 may be silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, the fin may be made of a semiconductor material, and the fin may be made of the same material as the substrate or different material from the substrate.
In addition, in other embodiments, the substrate may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process foundation for a subsequent substrate formation, and the second semiconductor layer is used to provide a process foundation for a subsequent fin formation
The initial channel stack 120 includes a plurality of sacrificial layers 121 and a plurality of channel layers 122 that are alternately stacked, in the initial channel stack 120, the number of the sacrificial layers 121 and the number of the channel layers 122 that are alternately stacked may be the same or different, specifically, the initial channel stack may include 3 sacrificial layers and 2 channel layers that are alternately stacked, or the initial channel stack may include 4 sacrificial layers and 3 channel layers that are alternately stacked, which is described in this embodiment by taking an example that the initial channel stack 120 includes 4 sacrificial layers 121 and 3 channel layers 122 that are alternately stacked.
With continuing reference to fig. 5, the fig. 5 is a cross-sectional view of the view of fig. 3, after the step of providing a base, an isolation layer 103 may be further formed, and the isolation layer 103 covers the substrate where the fin 102 is exposed.
The isolation layer 103 is used to electrically isolate the fins 102 from each other.
In this embodiment, the isolation layer 103 covers the substrate 101 exposed from the fin portion 102. The material of the isolation layer 103 comprises silicon oxide. In other embodiments, the material of the isolation layer 103 may further include one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
It should be noted that the top surface of the isolation layer 103 is not higher than the top surface of the fin 102, which is beneficial for the subsequent etching of the initial channel stack 120.
In the embodiment of the present invention, after the isolation layer 103 is formed, a dummy gate oxide layer (not shown in the figure) may be further formed on a portion of the top surface and a portion of the sidewall of the initial channel stack 120, and the material of the dummy gate oxide layer is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
Referring to fig. 6 to 8, wherein fig. 6 is a top view, fig. 7 is a cross-sectional view taken along the direction BB 'in fig. 6, and fig. 8 is a cross-sectional view taken along the direction CC' in fig. 6, a dummy gate structure 130 is formed across the initial channel stack 120.
The dummy gate structure 130 occupies a space for forming a gate structure in a subsequent process. Wherein, the extending direction (Y direction in the figure) of the dummy gate structure 130 may be perpendicular to the extending method of the initial channel stack 120.
The dummy gate structure 130 comprises a top structure having a dimension along the first direction X of a first dimension D1 and a bottom structure having a dimension along the first direction X of a second dimension D2, the first dimension D1 being smaller than the second dimension D2, the dummy gate structure 130 covering a portion of the sidewalls and top of the initial channel stack 120; the dummy gate structure with the top structure size smaller than the bottom structure size (namely, the inverted T shape) is formed and used for forming a gate structure with the same shape and characteristics in the subsequent process, so that the performance of the device is improved.
In this embodiment, when the isolation layer 103 is formed, the dummy gate structure 130 crossing the initial channel stack 120 is formed on the isolation layer 103 in this step.
In an alternative example, the step of forming the dummy gate structure 130 may include: forming a dummy gate material layer (not shown) covering one side of the substrate having the initial channel stack; forming a first patterned pseudo gate mask layer on the pseudo gate material layer, wherein the first pseudo gate mask layer comprises at least one first mask pattern, and the size of the first mask pattern along a first direction is a second size; etching the pseudo gate material layer by taking the first pseudo gate mask layer as a mask to form an initial pseudo gate structure; forming a second patterned pseudo gate mask layer 131 on the initial pseudo gate structure, wherein the second pseudo gate mask layer comprises at least one second mask pattern, and the size of the second mask pattern along the first direction is a first size; and etching and removing the initial pseudo gate structure with partial thickness by taking the second pseudo gate mask layer as a mask to form the pseudo gate structure with the top size of a first size and the bottom size of a second size, wherein the part with the first size is taken as the top structure of the pseudo gate structure, and the part with the second size is taken as the bottom structure of the pseudo gate structure.
It should be noted that the thicknesses of the bottom structure and the top structure are determined according to the predetermined size of the gate structure. The second dummy gate mask layer 131 may remain in a subsequent step to protect the top of the dummy gate structure 130.
The material of the dummy gate structure 130 may be polysilicon. In other embodiments, the material of the dummy gate structure may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, an epitaxial growth process may be used to form the dummy gate material layer.
After forming the dummy gate structure 130 crossing the initial channel stack 120 in the embodiment of the present invention, referring to fig. 9, where fig. 9 is a cross-sectional view of the view of fig. 8, the method may further include forming sidewalls 140 on two sides of the dummy gate structure, where a thickness of the sidewall on the side of the top structure is greater than that of the sidewall on the side of the bottom structure, and a thickness difference between the sidewall on the side of the bottom structure and the sidewall on the side of the top structure is equal to 1/2, that is, (D2-D1)/2, of a difference between the second dimension D2 and the first dimension D1, so that a side of the sidewall facing away from the dummy gate structure is a plane.
The sidewall spacers 140 are used to protect the sidewalls of the dummy gate structure 130 and to define the formation region of the source/drain doped region in the subsequent process.
In the embodiment of the present invention, the dummy gate structure 130 is in an inverted T shape, and for convenience of the process flow, the side walls formed at two sides of the dummy gate structure may be in a structure with a thicker top and a thinner bottom, so that the side surface of the side wall away from one side of the dummy gate structure is a plane, and preferably, the plane may be perpendicular to the surface of the substrate.
Furthermore, in order to ensure the thickness uniformity of the side wall in the finally formed device, the side wall is formed by the two materials in the embodiment of the invention, so that one material in the side wall can be selectively removed in the subsequent process, and only the other material in the side wall is reserved.
Specifically, the step of forming the side walls on the two sides of the dummy gate structure includes: forming a first side wall material layer which conformally covers one side of the substrate with the pseudo grid structure; forming a second layer of sidewall material conformally covering the first layer of sidewall material, the second layer of sidewall material having a thickness greater than or equal to the difference between the second dimension and the first dimension; and removing the top of the pseudo grid structure, the first side wall material layer and the second side wall material layer on the surface of the substrate and the second side wall material layer protruding from the side surface of the pseudo grid structure, and forming side walls on two sides of the pseudo grid structure. The remaining first sidewall material layer is used as the first sidewall 141, and the remaining second sidewall material layer is used as the second sidewall 142.
The material of first sidewall material layer and second sidewall material layer can be for one or more in silicon oxide, silicon nitride, carborundum, silicon carbonitride, carbo-nitride-oxide, silicon oxynitride, boron nitride or boron carbonitride, and the material of first sidewall material layer and second sidewall material layer is different, and in this embodiment, first sidewall material layer can be for silicon nitride, and the second sidewall material layer can be for silicon oxide.
The sidewall material Layer may be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process.
It can be understood that, based on the feature that the bottom structure of the dummy gate structure has a large size and the top structure has a small size, after the first sidewall material layer and the second sidewall material layer are formed on both sides of the dummy gate structure, the step structure with a protruding bottom is formed on both sides of the dummy gate structure based on the shape of the dummy gate structure, and based on the fact that the thickness of the second sidewall material layer is greater than or equal to the difference between the second size and the first size, it can be understood that the step structure is only a partial structure of the second sidewall material layer, so that the second sidewall material layer with a protruding side of the dummy gate structure is removed while the first sidewall material layer and the second sidewall material layer on the top of the dummy gate structure and the surface of the substrate are removed, thereby forming a sidewall with a side deviating from one side of the dummy gate structure as a plane.
In the step of removing the top of the dummy gate structure, the first side wall material layer and the second side wall material layer on the surface of the substrate, and the second side wall material layer protruding from the side surface of the dummy gate structure, a dry etching process can be adopted to remove the corresponding structures.
Next, referring to fig. 10 to 11, wherein fig. 10 is a top view, and fig. 11 is a cross-sectional view in the BB 'direction in fig. 10, the initial channel stack on both sides of the dummy gate structure 130 is removed to form a target channel stack 120';
in the embodiment of the present invention, the dummy gate structure 130 and the sidewall spacers 140 may be used as masks to remove the initial channel stacks on both sides of the dummy gate structure. In this embodiment, the second dummy gate mask layer 131 is remained on the top of the dummy gate structure, and the initial channel stacks on both sides of the dummy gate structure are removed by using the second dummy gate mask layer 131 and the sidewalls 140 as masks.
The initial channel lamination layers on the two sides of the pseudo gate structure can be removed by adopting a dry etching process, a wet etching process or a combination of the dry etching process and the wet etching process, and the initial channel lamination layer at the intersection position of the pseudo gate structure and the side wall is reserved as a target channel lamination layer. Wherein the target channel stack is composed of the remaining sacrificial layer 121 'and the remaining channel layer 122'.
And removing the initial channel lamination layers on the two sides of the pseudo-gate structure, providing a process space for forming a doping structure, and simultaneously exposing the side walls on the two sides of the target channel lamination layer so as to facilitate the subsequent etching of the sacrificial layer exposed on the side surface of the target channel lamination layer.
In an alternative example, a part of the fin portion under the initial channel stack may be further removed at the same time as the initial channel stack is removed, so that a groove is formed on the fin portion to accommodate a part of the doped structure.
Referring to fig. 12, etching the sacrificial layer exposed from the sidewalls of the target channel stack to form a receiving space 150 defined by the channel layer adjacent to the sacrificial layer at the side of the remaining sacrificial layer;
the accommodating space 150 is used for providing a space position for the subsequent formation of the inner side wall.
In this embodiment, a wet etching process or a dry etching process may be used to etch the sacrificial layer exposed on the sidewall of the target channel stack, so as to form the accommodating space.
Specifically, the sidewall of the sacrificial layer in the target channel stack with a partial thickness may be removed by etching, so as to form an accommodation space surrounded by the channel layer and the remaining sacrificial layer, or surrounded by the channel layer, the remaining sacrificial layer, and the fin portion, or surrounded by the channel layer, the remaining sacrificial layer, and the sidewall.
Referring to fig. 13, an inner sidewall 151 is formed in the accommodating space 150.
The inner sidewall 151 is used to isolate a gate structure and a doped structure formed on both sides of the inner sidewall in the following process, and to provide a support for a suspended channel layer in the following process.
The inner sidewall 151 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and optionally, the material of the inner sidewall may be the same as that of the first sidewall material layer.
Referring to fig. 14, a doped structure 160 is formed on both sides of the dummy gate structure 130, and the doped structure 160 is connected to the channel layer 122' in the target channel stack;
the doped structure 160 is used as a source/drain structure of the device, and realizes control of the device together with a gate structure of the device.
The doped structure 160 may be silicon, and in other embodiments, the material of the doped structure may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the doped structure 160 is formed by an epitaxial process.
When the device is an NMOS device, the doped ions in the doped structure are N-type ions, and the N-type ions can be P ions, As ions or Sb ions; when the device is a PMOS device, the doped ions In the doped structure are P-type ions, and the P-type ions may be B ions, Ga ions, or In ions.
In order to ensure the uniformity of the thickness of the side wall of the device, after the doped structure is formed, the second side wall layer 142 in the side wall can be further removed. Specifically, the second sidewall layer 142 may be removed by wet etching, dry etching or a combination thereof.
Referring to fig. 15 to 20, a gate structure is formed in a space occupied by the dummy gate structure and the sacrificial layer in the target channel stack.
The grid structure is used as a grid of a device and carries out corresponding control. In the embodiment of the invention, the dummy gate structure and the sacrificial layer can be removed, so that the gate structure is formed in the space occupied by the dummy gate structure and the sacrificial layer.
Specifically, the step of forming a gate structure in the space occupied by the dummy gate structure and the sacrificial layer may include:
referring to fig. 15, an interlayer dielectric layer 170 is formed to be flush with the top of the dummy gate structure;
the interlayer dielectric layer 170 is used for realizing electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 170 is an insulating material. In this embodiment, the interlayer dielectric layer 170 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Specifically, the step of forming the interlayer dielectric layer 170 includes: forming an interlayer dielectric material layer (not shown) on the dummy gate structure and the exposed part of the dummy gate structure, wherein the interlayer dielectric material layer covers the top of the dummy gate structure; and carrying out planarization treatment on the interlayer dielectric material layer, removing the interlayer dielectric material layer higher than the pseudo gate structure, and taking the rest interlayer dielectric material layer after the planarization treatment as the interlayer dielectric layer 160.
In this embodiment, with reference to fig. 11 and 12, during the planarization process, the second dummy gate mask layer 131 is also removed at the same time.
Referring to fig. 16 to 18, wherein fig. 16 is a top view, fig. 17 is a cross-sectional view taken along CC ' in fig. 16, and fig. 18 is a cross-sectional view taken along BB ' in fig. 16, the dummy gate structure is removed, and a gate trench 181 is formed, wherein the gate trench 181 exposes a portion of the target channel stack 120 ' covered by the dummy gate structure.
The gate trench 181 is used to form a process space for filling the conductive gate, wherein the dummy gate structure is used to cover a portion of the target channel stack 120 ', and in this embodiment, the gate trench 181 exposes the portion of the target channel stack 120' covered by the dummy gate structure.
The dummy gate structure may be removed by an etching process, such as a wet etching process or a combination of a wet process and a dry etching process. Specifically, when the wet etching process is used for etching, an HCl solution may be used.
Referring to fig. 19, wherein fig. 19 is a structural view from the perspective of fig. 18, the sacrificial layer in the target channel stack is removed, and a gate via 182 communicating with the gate trench 181 is formed between the channel layers 122' in the target channel stack.
In the embodiment of the present invention, after the gate trench 181 is formed, the sacrificial layer in the target channel stack is removed, so that the channel layer is suspended in the gate trench, and a subsequently formed gate structure surrounds the channel layer. It is understood that the channel layer 122' is supported by the inner sidewalls at both sides of the gate trench.
Specifically, a dry etching process, a wet etching process, or a combination thereof may be used to remove the sacrificial layer in the initial channel stack.
Referring to fig. 20, a gate structure 190 is formed in the gate trench 181 and the gate channel 182.
The gate structure 190 may include a gate dielectric layer 191 and a conductive gate 192.
In this embodiment of the present invention, specifically, a gate dielectric material layer conformally covering the gate trench and the gate channel may be deposited and formed in the gate trench and the gate channel, and after the gate dielectric material layer is formed, a conductive gate material layer may be further deposited and completely covers the gate trench and the gate channel, and then the gate dielectric material layer and the conductive gate material layer outside the gate trench are removed, and the remaining gate dielectric material layer is used as the gate dielectric layer 191, and the remaining conductive gate material layer is used as the conductive gate 192.
In this embodiment, the gate dielectric layer 191 may be a high-k dielectric layer, and the material of the high-k dielectric layer is a dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 191 is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
The conductive gate 192 is a metal gate structure, and in this embodiment, the metal gate structure is made of magnesium-tungsten alloy. In other embodiments, the material of the metal gate structure may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
In the embodiment of the invention, the pseudo-gate structure with large bottom structure size and small top structure size is formed, so that the gate structure formed in the subsequent process has the same size characteristic, and the current in the gate structure is more distributed at the bottom of the gate structure when the device works, so that the current density uniformity of the gate structure is improved, the control capability of the gate structure on a channel is enhanced, the opening resistance when the channel at the bottom is opened is correspondingly reduced, the current density uniformity of a drain region in a source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, and the performance of the device is improved.
In another embodiment of the present invention, a method for forming a semiconductor structure is further provided, in which sacrificial layers with different etching rates are formed in the same etching process, so that the size of the sacrificial layer formed in the target channel stack is matched with that of the dummy gate structure, and a gate structure with a corresponding size is formed, thereby improving the performance of the device.
Fig. 21 to 32 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
With combined reference to fig. 21 to 25, a substrate 200 is provided, the substrate 200 is formed with an initial channel stack, and an extending direction of the initial channel stack is a first direction.
The substrate 200 is used to provide a process platform for forming a device structure, and the initial channel stack on the substrate 200 is used to provide a process base for subsequently forming a target channel stack.
The initial channel stack includes a plurality of sacrificial layers 221 and a plurality of channel layers 222 alternately stacked. The sacrificial layer 221 includes a first sacrificial layer 221A corresponding to a top structure of the dummy gate structure and a second sacrificial layer 221B corresponding to a bottom structure of the dummy gate structure, and in a first etching process, an etching rate of the first sacrificial layer 221A is greater than an etching rate of the second sacrificial layer 221B.
The etching rate of the first sacrificial layer 221A is greater than that of the second sacrificial layer 221B, so that the first sacrificial layer 221A located at the top layer of the initial channel stack can occupy a smaller process space by removing the sidewall with a larger thickness through a first etching process in the subsequent steps, and the second sacrificial layer 221B located at the bottom layer of the initial channel stack can occupy a larger process space by removing the sidewall with a smaller thickness through a first etching process in the subsequent steps, thereby forming sacrificial layers with different sizes in the same etching process.
The materials of the first sacrificial layer and the second sacrificial layer may be different, or the materials of the first sacrificial layer and the second sacrificial layer are the same, and the component contents of the materials are different, so that the first sacrificial layer and the second sacrificial layer have different etching rates in the same etching process. Optionally, in order to reduce the process complexity, the materials of the first sacrificial layer and the second sacrificial layer may be the same, and the component contents of the materials may be different.
In this embodiment, the first sacrificial layer and the second sacrificial layer may be made of silicon germanium materials, and the germanium content of the first sacrificial layer is greater than the germanium content of the second sacrificial layer, so that the HCl solution or HCl vapor may be used to etch the sacrificial layers, so that the first sacrificial layer is etched in the HCl solution or HCl vapor by a larger amount and the second sacrificial layer is etched by a smaller amount in the same time, so as to form sacrificial layers with different sizes in the same etching process.
Specifically, the difference between the percentage value of the germanium content of the first sacrificial layer and the percentage value of the germanium content of the second sacrificial layer may be 5% to 20%.
In this embodiment, the base 200 may include a substrate 201 and a fin 202 protruding from the substrate, and accordingly, the process of forming the initial channel stack on the base 200 may include:
referring to fig. 21, an initial substrate 20 is provided;
with combined reference to fig. 21 to 25, the initial substrate 20 is used to provide a process platform for subsequent formation of stacked material layers, and further, a portion of the thickness of the initial substrate 20 in a portion of the area is removed in a subsequent step to form a substrate and a fin protruding from the substrate.
In this embodiment, the initial substrate 20 is made of silicon. In other embodiments, the material of the initial substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the initial substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In addition, in other embodiments, the initial substrate may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used to provide a process foundation for a subsequent substrate formation, and the second semiconductor layer is used to provide a process foundation for a subsequent fin formation.
Next, referring to fig. 22, stacked material layers are formed on the initial substrate 20;
the stacked material layers include a plurality of sacrificial material layers 211 and a plurality of channel material layers 212 that are alternately stacked, wherein the sacrificial material layers 211 include at least one first sacrificial material layer 211A at the top of the stacked material layers and at least one second sacrificial material layer 211B at the bottom of the stacked material layers. The stacked material layers are used for forming an initial channel stack by subsequently removing the stacked material layers in a partial region, the first sacrificial material layer 211A provides a process basis for subsequently forming a first sacrificial layer, the second sacrificial material layer 211B provides a process basis for subsequently forming a second sacrificial layer, and the channel material layer 212 is used for providing a process basis for subsequently forming a channel layer.
In the first etching process, the etching rate of the first sacrificial material layer is greater than that of the second sacrificial material layer, so that the first sacrificial layer and the second sacrificial layer formed subsequently on the basis of the first sacrificial material layer and the second sacrificial material layer have corresponding etching rates.
The number of layers of the sacrificial material layer 211 and the channel material layer 212 in the stacked material layers is matched with the number of sacrificial layers and channel layers to be formed, and the stacked material layers correspondingly include 4 sacrificial material layers and 3 channel material layers when 4 sacrificial layers and 3 channel layers are alternately stacked in the initial channel stack of the embodiment.
In this embodiment, an Epitaxial Growth process (Epitaxial Growth) is used to form stacked material layers on the initial substrate 20. The epitaxial growth process is adopted, so that the lattice structure of the semiconductor structure is not easy to damage, and the subsequently formed semiconductor structure is not easy to leak electricity.
In this embodiment, the process of forming the stacked material layer by using the epitaxial growth process may include a sacrificial material layer forming stage and a channel material layer forming stage, where the introduced epitaxial gases are different in the sacrificial material layer forming stage and the channel material layer forming stage; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gases are the same, and the flow rates of the introduced epitaxial gases are different.
The method comprises the steps of forming a channel material layer and a sacrificial material layer, wherein different epitaxial gases are introduced under control to form the sacrificial material layer and the channel material layer which are made of different materials, and controlling the flow of the introduced epitaxial gases to form a first sacrificial material layer and a second sacrificial material layer which are different in components, so that the first sacrificial layer and the second sacrificial layer which are formed by the second sacrificial material layer and are formed by different amounts of the first sacrificial material layer can be removed simultaneously in the subsequent etching step.
In the present embodiment, the material of the sacrificial material layer 211 is silicon germanium, and the material of the channel material layer 212 is silicon. Specifically, the step of forming the stacked material layer on the substrate by using an epitaxial growth process may include: forming a second sacrificial material layer, wherein the epitaxial gas introduced in the stage of forming the second sacrificial material layer is germane and silane; forming a channel material layer, wherein the epitaxial gas introduced in the channel material layer forming stage is silane; and forming a first sacrificial material layer, wherein the epitaxial gas introduced in the first sacrificial material layer forming stage is germane and silane, and the flow rate of introducing germane in the first sacrificial material layer forming stage is greater than that of introducing germane in the second sacrificial material layer forming stage.
Next, referring to fig. 23 to 25, where fig. 23 is a top view, fig. 24 is a cross-sectional view along AA 'in fig. 23, and fig. 25 is a cross-sectional view along BB' in fig. 23, the stacked material layer in a partial region and the initial substrate in the partial region are removed, the initial substrate with the remaining thickness is used as a substrate 201, the initial substrate protruding from the substrate is used as a fin 202, and the remaining stacked material layer on the fin 202 is used as an initial channel stack.
And removing the stacked material layer in a partial area and the initial substrate with partial thickness in the partial area to realize the patterning of the stacked material layer and the initial substrate, thereby forming the substrate 201, the fin 202 protruding out of the substrate, and the initial channel lamination layer on the fin 202.
In this embodiment, the substrate 201 and the fin 202 protruding from the substrate, and the initial channel stack on the fin 202 may be implemented in a patterning process. Specifically, the process of stacking the substrate 201, the fin 202 protruding from the substrate, and the initial channel on the fin 202 includes: forming a patterned first mask layer (not shown in the figure) on the stacked material layer, wherein the first mask layer covers a preset region for forming the fin portion and exposes other regions except the region; and taking the first mask layer as a mask, and etching and removing the stacked material layer in the exposed area of the first mask layer and the initial substrate with partial thickness in the partial area.
The first mask layer may be a photoresist layer or a hard mask layer, and is preferably a hard mask layer in this embodiment, and correspondingly, the hard mask layer may be made of silicon nitride (SiN) or silicon oxide (SiO)2) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxycarbonitride (SiOCN), and when multiple materials are used, the hardmask layer may be a stack of multiple material layers. In this embodiment, the hard mask layer may be made of silicon nitride. And, after forming the initial channel stack, the first mask layer may remain to a subsequent step to continue to protect a top surface of the initial channel stack in the subsequent step.
In the formed initial channel stack, the remaining channel material layer is the channel layer 222, and the remaining sacrificial material layer is the sacrificial layer 221, wherein the first sacrificial material layer remaining in the initial channel stack is the first sacrificial layer 221A, and the second sacrificial material layer remaining in the initial channel stack is the second sacrificial layer 221B.
Further, after the step of removing the stacked material layer in a partial region and the initial substrate with a partial thickness in the partial region, an isolation layer may be further formed, and the isolation layer covers the substrate where the fin portion is exposed.
In the embodiment of the present invention, after the isolation layer is formed, the first mask layer may be removed, and a dummy gate oxide layer (not shown in the figure) may be further formed on a portion of the top surface and a portion of the sidewall of the initial channel stack, where the dummy gate oxide layer is made of silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
Referring to fig. 26, wherein fig. 26 is a cross-sectional view of the perspective of fig. 25, a dummy gate structure 230 is formed across the initial channel stack, the dummy gate structure 230 covering portions of the sidewalls and top of the initial channel stack.
When the isolation layer is formed in this embodiment, the dummy gate structure 230 crossing the initial channel stack is formed on the isolation layer in this step.
In the embodiment of the present invention, the cross section of the formed dummy gate structure 230 is an inverted T shape. Specifically, the dummy gate structure 230 may include a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, wherein the first dimension is smaller than the second dimension.
It should be noted that the thicknesses of the bottom structure and the top structure are determined according to the preset size of the gate structure, and the thicknesses of the bottom structure and the top structure are matched with the layer structure in the initial channel stack. Specifically, the thickness of the bottom structure is matched with the height of the highest sacrificial layer in the initial channel lamination layer, wherein the highest sacrificial layer has the same etching rate as the first sacrificial layer, so that a gate structure with the same extension shape is formed in the subsequent process.
In the forming of the dummy gate structure 230, the dummy gate structure 230 may be formed through multiple patterning and etching processes, in this example, the mask layer 231, which is used as a mask and is located on the top of the dummy gate structure, may be remained, so that after the top structure of the dummy gate structure is formed through etching, the top of the dummy gate structure may be further included.
After forming the dummy gate structure crossing the initial channel stack in the embodiment of the present invention, referring to fig. 27, forming spacers 240 on two sides of the dummy gate structure, where a thickness of the spacer located on the side of the top structure is greater than that of the spacer located on the side of the bottom structure, and a thickness difference between the spacer located on the side of the bottom structure and the spacer located on the side of the top structure is equal to 1/2 of a difference between the second size and the first size, so that a side of the spacer facing away from the dummy gate structure is a plane. The sidewall 240 may include a first sidewall 141 conformally covering the sidewall of the dummy gate structure and a second sidewall 242 filling the outside of the first sidewall.
Next, referring to fig. 28, removing the initial channel stacks on both sides of the dummy gate structure to form a target channel stack;
in the embodiment of the invention, the initial channel laminated layers on two sides of the pseudo gate structure can be removed by taking the pseudo gate structure and the side walls as masks. The target channel stack is composed of the remaining sacrificial layer 221 ' and the remaining channel layer 222 ', and the remaining sacrificial layer 221 ' is composed of the remaining first sacrificial layer 221A ' and the remaining second sacrificial layer 221B '.
Next, referring to fig. 29, the sacrificial layer exposed at the sidewall of the target channel stack is etched using a first etching process, and a receiving space 250 defined by a channel layer adjacent to the sacrificial layer is formed at the side of the remaining sacrificial layer.
The receiving space 250 is used for providing a space position for the subsequent formation of the inner side wall.
Based on the fact that the etching rate of the first sacrificial layer in the first etching process is larger than that of the second sacrificial layer, the first etching process is adopted to etch the sacrificial layers in the target channel lamination layer exposed at two sides of the pseudo gate structure, more first sacrificial layers can be removed at the same time, fewer second sacrificial layers are removed, and therefore sacrificial layers with different sizes are formed in the first etching process at the same time.
Furthermore, the size of the remaining first sacrificial layer in the etched target channel stack along the first direction may be greater than or equal to the first size, and the size of the remaining second sacrificial layer along the first direction may be less than or equal to the second size, where the size of the remaining first sacrificial layer along the first direction is greater than or equal to the first size, so that the gate control capability of the device may be further improved for a gate structure subsequently formed in this space, and the size of the remaining second sacrificial layer along the first direction is less than or equal to the second size, so that a void protruding out of the cross section of the dummy gate structure may be prevented from being formed, and further, a void may appear at the bottom of the gate structure subsequently formed.
In the first etching process, an HCl solution or an HCl vapor may be used to etch the sacrificial layer exposed on the sidewall of the target channel stack. When the HCl solution is used for etching the sacrificial layer exposed on the side wall of the target channel lamination, the concentration of the HCl solution can be 5% -20%.
It is understood that after the first etching process is performed, the receiving space 250A formed by the side of the remaining first sacrificial layer is larger than the receiving space 250B formed by the side of the remaining second sacrificial layer.
Referring to fig. 30, an inner sidewall 251 is formed in the accommodating space.
The inner sidewall 251 is used to isolate a gate structure and a doped structure formed on two sides of the inner sidewall later, and to provide a support for a suspended channel layer in the subsequent process.
Based on this embodiment, the accommodating space formed by the side surface of the first sacrificial layer is relatively large, correspondingly, the thickness of the inner side wall formed in the accommodating space is relatively large, the accommodating space formed by the side surface of the second sacrificial layer is relatively small, and correspondingly, the thickness of the inner side wall formed in the accommodating space is relatively small.
Referring to fig. 31, doped structures 260 are formed on both sides of the dummy gate structure, and the doped structures 260 interface with the channel layer in the target channel stack.
Referring to fig. 32, a gate structure 290 is formed in a space occupied by the dummy gate structure and the sacrificial layer.
The gate structure 290 includes a gate dielectric layer 291 and a conductive gate 292, and an interlayer dielectric layer 270 is also formed during the process of forming the gate structure.
For the description of each step in this embodiment, reference may be made to the description in the foregoing embodiments, and the description of the present invention is not repeated herein.
In the embodiment of the invention, the size of the sacrificial layer formed in the target channel lamination is matched with that of the dummy gate structure, so that the size of the gate structure formed at the target channel lamination is matched with that of the gate structure formed at the dummy gate structure, and the performance of the device is improved. Meanwhile, the sacrificial layers with different etching rates are formed, so that the sacrificial layers with different sizes are formed in the same etching process, the process is simplified, and the process cost is reduced.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 32, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes:
a substrate 200;
a gate structure 290 on the substrate, including a top gate structure having a first dimension along the first direction and a bottom gate structure having a second dimension along the first direction, the first dimension being smaller than the second dimension, the first direction being perpendicular to an extending direction of the gate structure;
a channel stack intersecting the gate structure 290, the channel stack including a plurality of channel layers 222 'traversing the gate structure, and sidewalls of the channel layers 222' exposed at both sides of the gate structure 290;
the doped structure 260 is located at both sides of the gate structure 290, and the doped structure 260 is connected to the sidewall of the channel layer 222' exposed by the gate structure 290.
Optionally, the semiconductor structure further includes: a first sidewall 241 located at both sides of the gate structure 290 and an inner sidewall 251 located between the doped structure 260 and the gate structure 290.
Optionally, the thickness of the inner sidewall 251 at the side of the top gate structure is greater than that of the inner sidewall 251 at the side of the bottom gate structure.
Optionally, the first side wall 241 and the inner side wall 251 are made of the same material, and the first side wall 241 and the inner side wall 251 are made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
The gate structure 290 includes a gate dielectric layer 291 and a conductive gate 292, and interlayer dielectric layers 270 flush with the gate structure are disposed on two sides of the gate structure.
In the embodiment of the invention, the bottom grid structure of the grid structure is large in size, and the top grid structure is small in size, so that when the device works, more current in the grid structure is distributed at the bottom of the grid structure, the current density uniformity of the grid structure is improved, the control capability of the grid structure on a channel is enhanced, the starting resistance of the bottom channel is correspondingly reduced when the channel is started, the current density uniformity of a drain region in a source-drain doped layer flowing to a source region in the source-drain doped layer through the channel layer is improved, and the performance of the device is improved.
The semiconductor structure of the embodiment of the invention may be formed by using the forming method of the foregoing embodiment, or may be formed by using other forming methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein an initial channel lamination layer is formed on the substrate, the extending direction of the initial channel lamination layer is a first direction, and the initial channel lamination layer comprises a plurality of sacrificial layers and a plurality of channel layers which are alternately stacked;
forming a dummy gate structure across the initial channel stack, the dummy gate structure including a top structure having a first dimension along the first direction and a bottom structure having a second dimension along the first direction, the first dimension being less than the second dimension, the dummy gate structure covering a portion of the sidewalls and top of the initial channel stack;
removing the initial channel lamination layers on the two sides of the pseudo gate structure to form a target channel lamination layer;
forming doped structures on two sides of the pseudo gate structure, wherein the doped structures are connected with the channel layer in the target channel lamination;
and forming a gate structure in a space occupied by the dummy gate structure and the sacrificial layer in the target channel lamination after forming doping structures on two sides of the dummy gate structure.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the dummy gate structure across the initial channel stack and before removing the initial channel stack on both sides of the dummy gate structure, further comprising:
and forming side walls on two sides of the pseudo gate structure, wherein the thickness of the side wall positioned on the side surface of the top structure is larger than that of the side wall positioned on the side surface of the bottom structure, and the thickness difference between the side wall positioned on the side surface of the bottom structure and the side wall positioned on the side surface of the top structure is equal to 1/2 of the difference between the second size and the first size.
3. The method for forming the semiconductor structure according to claim 2, wherein the forming of the spacers on the two sides of the dummy gate structure comprises:
forming a first side wall material layer which conformally covers one side of the substrate with the pseudo grid structure;
forming a second layer of sidewall material conformally covering the first layer of sidewall material, the second layer of sidewall material having a thickness greater than or equal to the difference between the second dimension and the first dimension;
and removing the top of the pseudo grid structure, the first side wall material layer and the second side wall material layer on the surface of the substrate and the second side wall material layer protruding from the side surface of the pseudo grid structure, and forming side walls on two sides of the pseudo grid structure.
4. The method for forming a semiconductor structure according to claim 3, wherein after the forming of the doped structures on both sides of the dummy gate structure and before the forming of the gate structure, the method further comprises:
and removing the second side wall material layer in the side wall.
5. The method of forming a semiconductor structure of claim 1, wherein said forming a dummy gate structure across said initial channel stack comprises:
forming a dummy gate material layer covering one side of the substrate with the initial channel lamination;
forming a first patterned dummy gate mask layer on the dummy gate material layer, wherein the first dummy gate mask layer comprises at least one first mask pattern, and the size of the first mask pattern along a first direction is a second size;
etching the pseudo gate material layer by taking the first pseudo gate mask layer as a mask to form an initial pseudo gate structure;
forming a second patterned pseudo gate mask layer on the initial pseudo gate structure, wherein the second pseudo gate mask layer comprises at least one second mask pattern, and the size of the second mask pattern along the first direction is a first size;
and etching and removing the initial pseudo gate structure with partial thickness by taking the second pseudo gate mask layer as a mask to form the pseudo gate structure with the top size of a first size and the bottom size of a second size, wherein the part with the first size is taken as the top structure of the pseudo gate structure, and the part with the second size is taken as the bottom structure of the pseudo gate structure.
6. The method for forming a semiconductor structure according to claim 1, wherein after removing the initial channel stack on both sides of the dummy gate structure and before forming the doped structure on both sides of the dummy gate structure, the method further comprises:
etching the sacrificial layer exposed from the side wall of the target channel lamination layer to enable the side face of the remaining sacrificial layer to form a containing space defined by the channel layer adjacent to the sacrificial layer;
and forming an inner side wall in the accommodating space.
7. The method for forming a semiconductor structure according to claim 6, wherein the sacrificial layer comprises a first sacrificial layer corresponding to a top structure of the dummy gate structure and a second sacrificial layer corresponding to a bottom structure of the dummy gate structure, and an etching rate of the first sacrificial layer is higher than an etching rate of the second sacrificial layer in the first etching process.
8. The method of forming a semiconductor structure of claim 7, wherein the first and second sacrificial layers are silicon germanium and the germanium content of the first sacrificial layer is greater than the germanium content of the second sacrificial layer.
9. The method of forming a semiconductor structure of claim 8, wherein a difference between a percentage value of a germanium content of the first sacrificial layer and a percentage value of a germanium content of the second sacrificial layer is 5% to 20%.
10. The method of claim 7, wherein the base comprises a substrate and a fin protruding from the substrate, and wherein forming the initial channel stack on the base comprises;
providing an initial substrate;
forming stacked material layers on the initial substrate, the stacked material layers comprising a plurality of sacrificial material layers and a plurality of channel material layers stacked alternately, wherein the sacrificial material layers comprise at least one first sacrificial material layer on top of the stacked material layers and at least one second sacrificial material layer on bottom of the stacked material layers; in a first etching process, the etching rate of the first sacrificial material layer is greater than that of the second sacrificial material layer;
removing the stacked material layers in a partial region and the initial substrate with partial thickness in the partial region, taking the initial substrate with residual thickness as a substrate, taking the initial substrate protruding out of the substrate as a fin part, and taking the residual stacked material layers as an initial channel lamination, wherein the first sacrificial material layers remaining in the initial channel lamination are first sacrificial layers, and the second sacrificial material layers remaining in the initial channel lamination are second sacrificial layers.
11. The method of forming a semiconductor structure of claim 10, wherein a stack of material layers is formed on the initial substrate using an epitaxial growth process; wherein, in the stage of forming the sacrificial material layer and the stage of forming the channel material layer, the introduced epitaxial gases are different; in the stage of forming the first sacrificial material layer and the stage of forming the second sacrificial material layer, the introduced epitaxial gases are the same, and the flow rates of the introduced epitaxial gases are different.
12. The method for forming a semiconductor structure according to claim 7, wherein the first etching process is used to etch the sacrificial layer exposed on the sidewall of the target channel stack, so that the dimension of the remaining first sacrificial layer along the first direction is greater than or equal to the first dimension, and the dimension of the remaining second sacrificial layer along the first direction is less than or equal to the second dimension.
13. The method of claim 7, wherein in the first etching process, the sacrificial layer is etched using HCl solution or HCl vapor.
14. The method for forming the semiconductor structure according to claim 6, wherein the step of removing the initial channel stacks on both sides of the dummy gate structure specifically includes removing the initial channel stacks on both sides of the dummy gate structure by using the dummy gate structure and the spacers as masks.
15. The method of forming a semiconductor structure of claim 1, wherein forming a gate structure in a space occupied by the dummy gate structure and the sacrificial layer in the target channel stack comprises:
forming an interlayer dielectric layer which is flush with the top of the pseudo gate structure;
removing the dummy gate structure to form a gate groove, wherein the gate groove exposes part of the target channel lamination covered by the dummy gate structure;
removing the sacrificial layer in the target channel lamination, and forming a grid channel communicated with the grid groove between the channel layers in the target channel lamination;
forming a gate structure in the gate trench and the gate channel.
16. The method of claim 3, wherein the material of the first sidewall material layer and the second sidewall material layer is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the material of the first sidewall material layer and the second sidewall material layer is different.
17. A semiconductor structure, comprising:
a substrate;
the gate structure is positioned on the substrate and comprises a top gate structure with a first size along the first direction and a bottom gate structure with a second size along the first direction, the first size is smaller than the second size, and the first direction is vertical to the extending direction of the gate structure;
a channel stack intersecting the gate structure, the channel stack including a plurality of channel layers traversing the gate structure, and sidewalls of the channel layers being exposed on both sides of the gate structure;
and the doped structures are positioned on two sides of the grid structure and connected with the side wall of the channel layer exposed by the grid structure.
18. The semiconductor structure of claim 17, further comprising: the first side walls are positioned on two sides of the grid structure, and the inner side walls are positioned between the doped structure and the grid structure.
19. The semiconductor structure of claim 18, wherein the thickness of the inner sidewall at the side of the top gate structure is greater than the thickness of the inner sidewall at the side of the bottom gate structure.
20. The semiconductor structure of claim 19, wherein the first sidewall and the inner sidewall are made of the same material, and the material of the first sidewall and the inner sidewall is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010762886.9A CN114068706B (en) | 2020-07-31 | 2020-07-31 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010762886.9A CN114068706B (en) | 2020-07-31 | 2020-07-31 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114068706A true CN114068706A (en) | 2022-02-18 |
| CN114068706B CN114068706B (en) | 2023-12-29 |
Family
ID=80227981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010762886.9A Active CN114068706B (en) | 2020-07-31 | 2020-07-31 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114068706B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136883A (en) * | 1985-12-06 | 1987-06-19 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Manufacture of self-aligning field effect transistor |
| US20140134836A1 (en) * | 2012-11-09 | 2014-05-15 | GlobalFoundries, Inc. | Dielectric cap layer for replacement gate with self-aligned contact |
| US20170352744A1 (en) * | 2016-06-03 | 2017-12-07 | International Business Machines Corporation | Fin field effect transistor fabrication and devices having inverted t-shaped gate |
| CN110265301A (en) * | 2018-03-12 | 2019-09-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106009A (en) * | 2018-10-26 | 2020-05-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2020
- 2020-07-31 CN CN202010762886.9A patent/CN114068706B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136883A (en) * | 1985-12-06 | 1987-06-19 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Manufacture of self-aligning field effect transistor |
| US20140134836A1 (en) * | 2012-11-09 | 2014-05-15 | GlobalFoundries, Inc. | Dielectric cap layer for replacement gate with self-aligned contact |
| US20170352744A1 (en) * | 2016-06-03 | 2017-12-07 | International Business Machines Corporation | Fin field effect transistor fabrication and devices having inverted t-shaped gate |
| CN110265301A (en) * | 2018-03-12 | 2019-09-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106009A (en) * | 2018-10-26 | 2020-05-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114068706B (en) | 2023-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9570557B2 (en) | Tilt implantation for STI formation in FinFET structures | |
| US10529863B2 (en) | Flat STI surface for gate oxide uniformity in Fin FET devices | |
| US9865709B2 (en) | Selectively deposited spacer film for metal gate sidewall protection | |
| CN112309860A (en) | Semiconductor structure and forming method thereof | |
| US20150295070A1 (en) | Finfet and method for manufacturing the same | |
| CN110581173A (en) | Semiconductor structure and forming method thereof | |
| CN111613581B (en) | Semiconductor structure and forming method thereof | |
| CN114334827A (en) | Semiconductor structure and forming method thereof | |
| CN108010846B (en) | Method for improving short channel effect and semiconductor structure | |
| CN110854194A (en) | Semiconductor structure and forming method thereof | |
| CN113130311B (en) | Semiconductor structure and forming method thereof | |
| CN113539969B (en) | Semiconductor structure and forming method thereof | |
| CN114068706B (en) | Semiconductor structure and forming method thereof | |
| CN117652014A (en) | Semiconductor structure and forming method thereof | |
| CN115775769A (en) | Semiconductor structure and forming method thereof | |
| CN115249705A (en) | Semiconductor structure and forming method thereof | |
| CN111463275B (en) | Semiconductor structure and forming method thereof | |
| CN113838803A (en) | Semiconductor structure and forming method thereof | |
| CN113809011A (en) | Semiconductor structure and forming method thereof | |
| CN112309862A (en) | Semiconductor structure and forming method thereof | |
| CN111627814A (en) | Semiconductor structure and forming method thereof | |
| CN113808947B (en) | Semiconductor structure and forming method thereof | |
| CN110690286B (en) | Semiconductor structure and forming method thereof | |
| US20230387261A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN112103249B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |