CN112103249B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112103249B
CN112103249B CN201910528461.9A CN201910528461A CN112103249B CN 112103249 B CN112103249 B CN 112103249B CN 201910528461 A CN201910528461 A CN 201910528461A CN 112103249 B CN112103249 B CN 112103249B
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layer
forming
metal contact
contact hole
semiconductor layer
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CN112103249A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor structure and method of forming the same, the method comprising: providing a substrate, wherein a grid structure is formed on the substrate; forming a first epitaxial layer on the substrate at two sides of the grid structure; forming an interlayer dielectric layer covering the surface of the substrate on one side of the substrate on which the first epitaxial layer is formed; forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer; forming a second epitaxial layer in the metal contact hole, wherein the second epitaxial layer covers the bottom surface of the metal contact hole, and the surface of the second epitaxial layer is lower than the surface of the interlayer dielectric layer; and forming a metal electrode in the metal contact hole. The method increases the size of the source-drain doped layer and improves the performance of the device.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
However, the electrical performance of the semiconductor devices formed by the prior art is still to be improved.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure and a forming method thereof, which can improve the electrical performance of a semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a grid structure is formed on the substrate; forming a first epitaxial layer on the substrate at two sides of the grid structure; forming an interlayer dielectric layer covering the surface of the substrate on one side of the substrate on which the first epitaxial layer is formed; forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer; forming a second epitaxial layer in the metal contact hole, wherein the second epitaxial layer covers the bottom surface of the metal contact hole, and the surface of the second epitaxial layer is lower than the surface of the interlayer dielectric layer; and forming a metal electrode in the metal contact hole.
Preferably, in the step of providing a base, the base includes a substrate and a plurality of discrete fins protruding from the substrate; the grid structure spans across the fin parts and covers partial tops and partial side walls of the fin parts; the step of forming a first epitaxial layer on the substrate at two sides of the gate structure comprises the following steps: and forming a first epitaxial layer on fin parts at two sides of the grid electrode structure.
Preferably, in the step of forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer, the first epitaxial layers on the fin portions on the same side of the gate structure are exposed in one metal contact hole.
Preferably, the step of forming the first epitaxial layer on the substrate at two sides of the gate structure specifically includes: forming doped semiconductor layers on the substrates at two sides of the grid structure; the step of forming the second epitaxial layer in the metal contact hole specifically comprises the following steps: and forming an intrinsic semiconductor layer in the metal contact hole.
Preferably, in the step of providing a substrate, the substrate includes an NMOS device region and a PMOS device region, where the gate structures are formed in the NMOS device region and the PMOS device region, respectively; the step of forming a doped semiconductor layer on the substrate at two sides of the gate structure comprises the following steps: forming an N-type doped semiconductor layer in the NMOS device region, wherein the N-type doped semiconductor layer is positioned on a substrate at two sides of a grid structure in the NMOS device region; forming a P-type doped semiconductor layer in the PMOS device region, wherein the P-type doped semiconductor layer is positioned on the substrate at two sides of the grid structure in the PMOS device region; the step of forming the intrinsic semiconductor layer in the metal contact hole comprises the following steps: and simultaneously forming an intrinsic semiconductor layer in the metal contact holes of the NMOS device region and the PMOS device region.
Preferably, the step of forming the first epitaxial layer on the substrate at two sides of the gate structure specifically includes: forming an intrinsic semiconductor layer on the substrate at two sides of the gate structure; the step of forming the second epitaxial layer in the metal contact hole specifically comprises the following steps: and forming a doped semiconductor layer in the metal contact hole.
Preferably, in the step of providing a substrate, the substrate includes an NMOS device region and a PMOS device region, wherein gate structures are formed in both the NMOS device region and the PMOS device region; the step of forming the intrinsic semiconductor layer on the substrate at two sides of the gate structure comprises the following steps: simultaneously forming an intrinsic semiconductor layer on the substrate at two sides of the grid structure of the NMOS device region and the PMOS device region; the step of forming a doped semiconductor layer in the metal contact hole comprises the following steps: forming a patterned N-type mask layer, wherein the N-type mask layer exposes the NMOS device region and covers the PMOS device region; forming an N-type doped semiconductor layer in the metal contact hole of the NMOS device region by taking the N-type mask layer as a mask; forming a patterned P-type mask layer, wherein the P-type mask layer exposes the PMOS device region and covers the NMOS device region; and forming a P-type doped semiconductor layer in the metal contact hole of the PMOS device region by taking the P-type mask layer as a mask.
Preferably, after the step of forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer, before the step of forming a doped semiconductor layer in the metal contact hole, the method further includes: and removing the intrinsic semiconductor layer in the metal contact hole to form an epitaxial structure hole communicated with the metal contact hole.
Preferably, in the step of forming the N-type doped semiconductor layer in the metal contact hole of the NMOS device region, the method further includes: forming an N-type doped semiconductor layer in the epitaxial structure hole of the NMOS device region; the step of forming the P-type doped semiconductor layer in the metal contact hole of the PMOS device region further comprises the following steps: and forming a P-type doped semiconductor layer in the epitaxial structure hole of the PMOS device region.
Preferably, the material of the intrinsic semiconductor layer is silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide; the N-type doped semiconductor layer and the P-type doped semiconductor layer are homogenous with the intrinsic semiconductor layer.
Preferably, a second epitaxial layer is formed in the metal contact hole by adopting an epitaxial growth process.
Correspondingly, the invention also provides a semiconductor structure, which comprises: a substrate, on which a gate structure is formed; the interlayer dielectric layer is covered on the surface of the substrate and is positioned on one side of the substrate, on which the grid structure is formed; the epitaxial structure holes are positioned in the interlayer dielectric layer, the epitaxial structure holes are positioned at two sides of the grid structure, and the bottom surface of the epitaxial structure holes extends to the substrate; the metal contact hole is communicated with the epitaxial structure hole and extends to the surface of the interlayer dielectric layer; the source-drain doped layer is positioned in the epitaxial structure hole and the metal contact hole, and the surface of the source-drain doped layer is higher than the bottom surface of the metal contact hole and lower than the surface of the interlayer dielectric layer; and the metal electrode is positioned in the metal contact hole.
Preferably, the substrate comprises a substrate and a plurality of discrete fins protruding out of the substrate, and the gate structure spans across the fins and covers part of top and part of side walls of the fins; the epitaxial structure hole extends to fin portions on two sides of the grid electrode.
Preferably, the epitaxial structure holes on the fin portions on the same side of the gate structure are communicated into one metal contact hole.
Preferably, the source-drain doped layer includes: a first epitaxial layer on the substrate and a second epitaxial layer on the first epitaxial layer;
the first epitaxial layer is positioned in the epitaxial structure hole, and the second epitaxial layer is positioned in the metal contact hole; and the second epitaxial layer covers the bottom surface of the metal contact hole, and the surface of the second epitaxial layer is lower than the surface of the interlayer dielectric layer.
Preferably, the first epitaxial layer is a doped semiconductor layer; the second epitaxial layer is an intrinsic semiconductor layer.
Preferably, the first epitaxial layer is an intrinsic semiconductor layer; the second epitaxial layer is a doped semiconductor layer.
Preferably, the substrate comprises an NMOS device region and a PMOS device region, wherein the grid structure is formed in the NMOS device region and the PMOS device region; the doped semiconductor layer positioned in the NMOS device region is an N-type doped semiconductor layer; the doped semiconductor layer in the PMOS device region is a P-type doped semiconductor layer.
Preferably, the material of the intrinsic semiconductor layer is silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide; the N-type doped semiconductor layer and the P-type doped semiconductor layer are homogenous with the intrinsic semiconductor layer.
Preferably, the source-drain doped layer is a doped semiconductor layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the method for forming the semiconductor structure, after the first epitaxial layer is formed, the second epitaxial layer is formed in the formed metal contact hole, so that the size of the epitaxial layer is increased, and the performance of the device is improved. Because the second epitaxial layer is formed in the metal contact hole, the short circuit of the source-drain doped layers of adjacent devices is avoided, meanwhile, the second epitaxial layer covering the bottom surface of the metal contact hole fills pits or holes which are possibly generated when the metal contact hole is formed, and extra capacitance and short circuit risks caused by metal materials in the pits or holes are avoided.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Fig. 14 to 17 are schematic views illustrating a structure corresponding to partial steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Fig. 18 to 19 are schematic views of a structure corresponding to partial steps in a method for forming a semiconductor structure according to another embodiment of the present invention.
Fig. 20 is a schematic structural view of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, the electrical performance of semiconductor devices has yet to be improved. The reason why the electrical properties are still to be improved is now analyzed in connection with a method of forming a semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1 to 2, wherein fig. 2 is a cross-sectional view along the PP1 direction in fig. 1, a substrate 1 includes a PMOS device region I and an NMOS device region II, a gate electrode 4 is formed on the substrate 1, source and drain doped layers 5 (also referred to as source and drain epitaxial layers, source Drain epitaxy layer) are formed on both sides of the gate electrode 4, wherein the source and drain doped layers formed in the PMOS device region I are P-type doped semiconductor layers, and the source and drain doped layers formed in the NMOS device region II are N-type doped semiconductor layers. Referring to fig. 3, fig. 3 is a cross-sectional structure diagram based on fig. 2, after an interlayer dielectric layer 6 covering a substrate is formed on one side where an active drain doping layer 5 is formed, a metal contact hole for exposing the active drain doping layer 5 is formed on the interlayer dielectric layer 6, and referring to fig. 4, fig. 4 is a cross-sectional structure diagram based on fig. 3, a metal electrode layer is deposited in the metal contact hole, and a metal electrode 7 electrically connected to the active drain doping layer is formed.
In the prior art, the size requirement on the source-drain doped layer is high.
Generally, the source-drain doped layer with larger size can reduce the risk of virtual connection between the metal electrode and the source-drain doped layer, and simultaneously reduce the contact resistance between the source-drain doped layer and the metal electrode, thereby improving the performance of the device. For a PMOS type device, the source-drain doped layer with larger size can also provide higher compressive stress, so that the hole mobility of the PMOS tube is improved, and the device performance is further improved. However, as the feature size of the device is gradually reduced, the larger size of the source-drain doped layer tends to create a short risk for the source-drain doped layer of the adjacent device.
When the size of the source-drain doped layer is smaller, overetching of the bottom surface of the metal contact hole is easy to cause, so that the metal contact hole is further etched downwards in the interlayer dielectric layer adjacent to the source-drain doped layer besides exposing the source-drain doped layer, and pits or holes are formed in the bottom surface of the metal contact hole. These pit or hole portions are also filled with metal material during subsequent deposition of the metal electrode layer, which may introduce additional metal electrode-gate electrode (CT-MG) capacitance during device operation, while increasing the risk of shorting of the metal electrode-gate electrode (CT-MG).
Based on the above, the embodiment of the invention provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a substrate, wherein a grid structure is formed on the substrate; forming a first epitaxial layer on the substrate at two sides of the grid structure; forming an interlayer dielectric layer covering the surface of the substrate on the side of the substrate on which the first epitaxial layer is formed; forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer; forming a second epitaxial layer in the metal contact hole, wherein the surface of the second epitaxial layer is lower than the surface of the interlayer dielectric layer and covers the bottom surface of the metal contact hole; and forming a metal electrode in the metal contact hole.
According to the method for forming the semiconductor structure, after the first epitaxial layer is formed, the second epitaxial layer is formed in the formed metal contact hole, so that the size of the epitaxial layer is increased, and the performance of the device is improved. Because the second epitaxial layer is formed in the metal contact hole, the short circuit of the source-drain doped layers of adjacent devices is avoided, meanwhile, the second epitaxial layer covering the bottom surface of the metal contact hole fills pits or holes which are possibly generated when the metal contact hole is formed, and extra capacitance and short circuit risks caused by metal materials in the pits or holes are avoided.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5 and 6 in combination, fig. 5 is a perspective view, and fig. 6 is a cross-sectional view taken along line AA1 of fig. 5, a substrate is provided, and a gate structure is formed on the substrate.
The substrate provides a process platform for the subsequent formation of semiconductor devices.
In this embodiment, the base is used to form a finfet, so in the step of providing a base, the base includes a substrate 100 and a plurality of discrete fins protruding from the substrate. In other embodiments, the substrate is used to form a planar transistor, and correspondingly, the substrate is a planar substrate.
The substrate 100 provides a process platform for the subsequent formation of semiconductor devices, and the fins serve to provide channels for the formed fin field effect transistors.
In this embodiment, taking the formed fin field effect transistor as a CMOS device as an example, the substrate 100 includes a PMOS device region I and an NMOS device region II, where the substrate 100 of the PMOS device region I and the NMOS device region II each have a plurality of discrete fins thereon. Specifically, the fin portion located on the PMOS device region I substrate 100 is a first fin portion 110, and the fin portion located on the NMOS device region II substrate 100 is a second fin portion 120.
In other embodiments, where the formed finfet includes only NMOS devices, the substrate includes only NMOS device regions; when the formed fin field effect transistor only comprises a PMOS device, the substrate only comprises a PMOS device region.
In this embodiment, the PMOS device region I and the NMOS device region II are adjacent regions. In other embodiments, the PMOS device region and the NMOS device region may also be isolated.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 100 may also have an interface layer formed on the surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
The fin is of the same material as the substrate 100. Therefore, in this embodiment, the material of the fin portion is silicon, that is, the material of the first fin portion 110 and the second fin portion 120 is silicon.
Referring to fig. 6 in combination, it should be noted that the substrate is further formed with an isolation structure 130, the isolation structure 130 covers a portion of the sidewall of the fin, and the top of the isolation structure 130 is lower than the top of the fin.
The isolation structure 130 is used as an isolation structure of the semiconductor device, and is used for isolating adjacent devices. In this embodiment, the material of the isolation structure 130 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
The gate structure 140 spans across the plurality of fins and covers portions of the top and portions of the sidewalls of the plurality of fins. The gate structure 140 may be a dummy gate structure for providing a process space for the metal gate structure, or may be a metal gate structure for controlling the opening and closing of the channel when the semiconductor structure is operated. The grid structures are formed on the substrates in the NMOS device region II and the PMOS device region I.
In this embodiment, the gate structure 140 is a metal gate structure.
In this embodiment, the gate structure 140 is a gate dielectric layer including a portion of the top and a portion of the sidewall of the fin and a gate layer on the gate dielectric layer. The gate layer is a stacked structure, and in other embodiments, the gate structure may be a single-layer structure.
The gate dielectric layer is made of a high-k dielectric layer, and the high-k dielectric layer is made of a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO 2 . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
The gate layer serves as an electrode for making electrical connection with an external circuit. In this embodiment, the material of the gate layer is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, al, cu, ag, au, pt, ni or Ti. Alternatively, the gate structure may also be a polysilicon gate structure.
The substrate further includes a hard mask layer 141 on the top surface of the gate structure 140, where the hard mask layer is used to define the pattern of the gate structure during the formation of the gate structure and to protect the top of the gate structure during subsequent processing. In this embodiment, the hard mask layer 141 is made of silicon nitride.
The substrate further includes a side wall 142 (as shown in fig. 5), where the side wall 142 is used to protect the side wall of the gate structure 140 in the process of removing the interlayer dielectric layer on the first epitaxial layer by subsequent etching, and the side wall 142 is further used to define the position of the first epitaxial layer.
Referring to fig. 7 to 9, fig. 7 is a perspective view (only four fins are illustrated), fig. 8 is a cross-sectional view along the AA1 line in fig. 7, and fig. 9 is a cross-sectional view along the BB1 line in fig. 7, wherein a first epitaxial layer is formed on the substrate on both sides of the gate structure.
Specifically, in this embodiment, the first epitaxial layer 150 is formed on the fin portions at two sides of the gate structure 140.
The first epitaxial layer 150 is used to form a source-drain doped layer together with a second epitaxial layer formed later, and is used as a source/drain region of a device, and when the semiconductor structure works, stress is provided for a channel below the gate structure, so that the mobility of carriers is improved.
It should be noted that, in the embodiment of the present invention, since the second epitaxial layer is further formed on the first epitaxial layer, the size of the first epitaxial layer does not need to be too large, so that the problem of short circuit of the adjacent devices possibly caused by the first epitaxial layer with a larger size is avoided.
Meanwhile, even though the first epitaxial layer in the embodiment of the invention has smaller size, when the metal contact hole is formed by etching, even if pits or holes are formed in the bottom surface of the metal contact hole by further etching downwards in the interlayer dielectric layer adjacent to the first epitaxial layer, the pits or holes can be filled by subsequently forming the second epitaxial layer covering the bottom surface of the metal contact hole in the metal contact hole, so that the problem of reduced device performance caused by filling the pits or holes with the metal material subsequently formed in the metal contact hole is avoided.
In this embodiment, the first epitaxial layer 150 is a doped semiconductor layer. The material of the doped semiconductor layer can be silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide.
Used to form the PMOS (Positive Channel Metal Oxide Semiconductor) transistor is a P-doped semiconductor layer, i.e., a semiconductor material doped with P-type ions. The doped semiconductor layer of this embodiment is silicon, and by doping P-type ions in the silicon, the P-type ions replace the silicon atoms in the lattice, and the more P-type ions are doped, the higher the concentration of the polyton and the stronger the conductivity. Specifically, the P-type ions include B, ga or In.
Used to form the NMOS (Negative channel Metal Oxide Semiconductor) transistor is an N-doped semiconductor layer, i.e., an N-ion doped semiconductor material. The doped semiconductor layer of this embodiment is silicon, and by doping N-type ions in the silicon, the N-type ions replace the positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of the polyton and the stronger the conductivity. Specifically, the N-type ions include P, as or Sb.
Since the doped epitaxial layers of different devices are different in type, in the step of forming the doped epitaxial layers, it is necessary to form an N-type doped semiconductor layer and a P-type doped semiconductor layer, respectively.
Specifically, the step of forming a doped semiconductor layer on the substrate at two sides of the gate structure includes: forming an N-type doped semiconductor layer in the NMOS device region, wherein the N-type doped semiconductor layer is positioned on a substrate at two sides of a grid structure in the NMOS device region; and forming a P-type doped semiconductor layer in the PMOS device region, wherein the P-type doped semiconductor layer is positioned on the substrate at two sides of the grid structure in the PMOS device region.
Referring to fig. 9, before the step of forming the first epitaxial layer on the fin portions on both sides of the gate structure, the present embodiment further forms a recess in the fin portions on both sides of the gate structure. The groove is formed to provide a process foundation for forming the first epitaxial layer, so that when the first epitaxial layer is formed, the first epitaxial layer which is partially embedded into the groove is formed on the fin parts on two sides of the gate structure.
The step of forming grooves in fin portions on two sides of the gate structure comprises the following steps: and forming N-region grooves on fin parts on two sides of the gate structure of the NMOS device region II, and forming P-region grooves on fin parts on two sides of the gate structure of the PMOS device region I.
The step of forming a doped epitaxial layer in the recess includes: forming an N-type doped semiconductor layer partially embedded in the N-region groove; and forming a P-type doped semiconductor layer which is partially embedded into the P-region groove in the P-region groove.
In this embodiment, a doped semiconductor layer is formed by a selective epitaxy process, and in the process of forming the doped semiconductor layer, P-type ions are self-doped in situ to form the P-type doped semiconductor layer, and N-type ions are self-doped in situ to form the N-type doped semiconductor layer.
It should be noted that, in order to avoid the process damage to the surface of the doped semiconductor layer caused by the subsequent process, after the doped semiconductor is formed, the method further includes: and (3) carrying out oxidation treatment on the surface of the doped semiconductor layer, and forming an oxidation protection layer (not shown) on the surface of the doped semiconductor layer, wherein the oxidation treatment can be dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation.
It should be noted that, after forming the first epitaxial layer 150, the method further includes: an etch stop layer (Contact Etch Stop Layer, CESL) is formed on the substrate on the side where the first epitaxial layer is formed (not shown in the drawings). The etching stop layer is used for defining the etching stop position of the etching process in the process of forming the metal contact hole by etching the interlayer dielectric layer.
The material of the etching stop layer adopts a material with low K dielectric constant. The material of the etching stop layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the material of the etching stop layer is silicon nitride.
Referring to fig. 10, fig. 10 is a cross-sectional view of fig. 8, and an interlayer dielectric layer 160 is formed on the substrate on the side where the first epitaxial layer 150 is formed.
The interlayer dielectric layer 160 is used to achieve electrical isolation between adjacent semiconductor structures, and thus, the material of the interlayer dielectric layer 160 is an insulating material.
Specifically, the material of the interlayer dielectric layer 160 is silicon oxide. The silicon oxide is a dielectric material with common process and lower cost, has higher process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer, and has simple removal process. In other embodiments, the material of the interlayer dielectric layer may be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
The interlayer dielectric layer 160 may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the interlayer dielectric layer 160 is formed by a chemical vapor deposition process.
In other embodiments of the present invention, if the gate structure is a dummy gate structure, the method further includes a step of removing the dummy gate structure and a step of forming a metal gate structure at the location of the dummy gate structure after the step.
Referring to fig. 11, fig. 11 is a cross-sectional view of the structure of fig. 10, and a metal contact hole 170 exposing the first epitaxial layer 150 is formed on the interlayer dielectric layer 160.
The metal contact hole is used for providing a process foundation for the subsequent formation of the second epitaxial layer and the metal electrode. The second epitaxial layer is formed in the metal contact hole, so that the first epitaxial layer and the second epitaxial layer form a source-drain doped layer, the source-drain doped layer with larger size is formed, and the electrical performance of the device is improved.
In this embodiment, the step of forming the metal contact hole 170 exposing the first epitaxial layer 150 includes: forming a patterned dielectric mask layer on the interlayer dielectric layer 160; and etching the interlayer dielectric layer 160 by taking the dielectric mask layer as a mask to form the metal contact hole 170.
Wherein the metal contact hole 170 may be formed using a wet etching or a dry etching process.
In this embodiment, an etching stop layer (not shown) is formed on the first epitaxial layer 150, so after forming the metal contact hole 170, further etching the metal contact hole 170 and removing the etching stop layer at the bottom of the metal contact hole 170 is included.
In this step, considering the accuracy of the dielectric mask layer and the influence of the etching process, the bottom of the metal contact hole does not necessarily completely fit with the bottom of the first epitaxial layer, and thus, there is a high probability that a pit or hole will occur in the interlayer dielectric layer adjacent to the first epitaxial layer at the bottom of the metal contact hole. In the embodiment of the invention, the second epitaxial layer formed later covers the bottom surface of the metal contact hole, so that the pit or hole at the bottom of the metal contact hole is prevented from being filled with the metal material formed later in the metal contact hole, and the additional metal electrode-gate electrode (CT-MG) capacitance and the short circuit risk of the metal electrode-gate electrode (CT-MG) caused by the metal material in the pit or hole are avoided.
Since the second epitaxial layer is further formed later, the first epitaxial layer 150 on the plurality of fins on the same side of the gate structure is exposed in one metal contact hole 170 during the formation of the metal contact hole 170 in this step. Specifically, taking a CMOS device including two fin portions as an example, two fin portions located at one side of a gate structure are located in the same metal contact hole 170, so that the process difficulty can be reduced, and the production efficiency can be improved. Meanwhile, the size of the metal contact hole 170 is increased, the size of a second epitaxial layer formed subsequently is further increased, and the performance of the device is further improved.
It should be noted that, during the process of forming the metal contact hole 170, the first epitaxial layers on the fin portions on the same side of the gate structure are exposed in one metal contact hole 170, so that a portion of the interlayer dielectric layer between the first epitaxial layers 150 is removed, which further causes uneven etching interface of the interlayer dielectric layer 160 (shown by a dashed box in fig. 11) between the first epitaxial layers, and the subsequently formed second epitaxial layer covers the bottom surface of the metal contact hole, so that the metal material formed in the metal contact hole is prevented from filling the pit or hole at the bottom of the metal contact hole, and the additional metal electrode-gate electrode (CT-MG) capacitance and the risk of short circuit of the metal electrode-gate electrode (CT-MG) caused by the metal material in the pit or hole are avoided.
Referring to fig. 12, fig. 12 is a cross-sectional view of fig. 11, a second epitaxial layer 180 is formed in the metal contact hole, the second epitaxial layer 180 covers the bottom surface of the metal contact hole 170, and the surface is lower than the surface of the interlayer dielectric layer 160.
The second epitaxial layer is used for forming a source-drain doped layer with the first epitaxial layer and is used as a source/drain region of the device, and stress is provided for a channel below the grid structure when the semiconductor structure works, so that the mobility of carriers is improved.
Since the second epitaxial layer 180 is further formed in the metal contact hole 170, the size of the source-drain doped layer is increased, thereby improving the performance of the device. And, the second epitaxial layer 180 covers the bottom surface of the metal contact hole 170, covers the etching defect of the bottom surface of the metal contact hole 170, and further improves the performance of the device.
The surface of the second epitaxial layer 180 is lower than the surface of the interlayer dielectric layer 160, so as to provide a process basis for forming a metal electrode later, and the metal electrode is formed in the metal contact hole 170.
In this embodiment, the second epitaxial layer 180 is an intrinsic semiconductor layer, and the intrinsic semiconductor layer is homogeneous with the doped semiconductor layer. That is, the intrinsic semiconductor layer and the doped semiconductor layer are made of the same material. Specifically, the material of the intrinsic semiconductor layer may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the intrinsic semiconductor layer is silicon.
In this step, the step of forming the intrinsic semiconductor layer in the metal contact hole includes: and simultaneously forming an intrinsic semiconductor layer in the metal contact holes of the NMOS device region II and the PMOS device region I.
Because the second epitaxial layer 180 is an intrinsic semiconductor layer, the same process can be used to form the intrinsic semiconductor layer in the NMOS device region II and the PMOS device region II at the same time, thereby saving the process flow and reducing the process cost.
Specifically, the second epitaxial layer 180 is formed in the metal contact hole using an epitaxial growth process.
Referring to fig. 13, fig. 13 is a cross-sectional view based on fig. 12, a metal electrode 190 is formed in the metal contact hole.
The metal electrode 190 is used to make electrical connection within the semiconductor structure.
The step of forming the metal electrode 190 includes: conductive material (not shown) is filled in the remaining space of the metal contact hole, the conductive material higher than the metal contact hole is removed, and the conductive material located in the metal contact hole serves as a metal electrode 190.
Specifically, a CMP (chemical mechanical polishing) process may be used to remove the conductive material above the metal contact hole.
In this embodiment, the conductive material is W. In other embodiments, the material of the conductive material may also be Al, cu, ag, au, or the like.
According to the method for forming the semiconductor structure, after the first epitaxial layer is formed, the second epitaxial layer is formed in the formed metal contact hole, so that the size of the epitaxial layer is increased, and the performance of the device is improved. Because the second epitaxial layer is formed in the metal contact hole, the short circuit of the source-drain doped layers of adjacent devices is avoided, meanwhile, the second epitaxial layer covering the bottom surface of the metal contact hole fills pits or holes which are possibly generated when the metal contact hole is formed, and extra capacitance and short circuit risks caused by metal materials in the pits or holes are avoided.
In another embodiment of the present invention, a method for forming a semiconductor structure is further provided, and referring to fig. 14 to 18, schematic structural diagrams corresponding to partial steps of the method for forming a semiconductor structure in this embodiment are provided.
Referring to fig. 14, unlike the previous embodiment, in the step of forming the first epitaxial layer on the substrate at both sides of the gate structure, the first epitaxial layer is formed as the intrinsic semiconductor layer 210.
The intrinsic semiconductor layer is used for forming a source-drain doped layer together with a second epitaxial layer formed later, and is used as a source/drain region of a device, and when the semiconductor structure works, stress is provided for a channel below the gate structure, so that the mobility of carriers is improved.
In other embodiments of the present invention, the intrinsic semiconductor may also be used as a pseudo-epitaxial layer, after the metal contact hole is formed subsequently, the intrinsic semiconductor layer in the metal contact hole is removed, an epitaxial structure hole communicating with the metal contact hole is formed, and when a second epitaxial layer is formed in the metal contact hole subsequently, the second epitaxial layer is used to fill the epitaxial structure hole, and further part of the second epitaxial layer is used to fill the metal contact hole to form the source-drain doped layer.
The material of the intrinsic semiconductor layer may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the intrinsic semiconductor layer is silicon.
Because the intrinsic semiconductor materials formed in the N-type device region II and the P-type device region I are the same, in this embodiment, the intrinsic semiconductor layer 210 may be formed on the substrate on both sides of the gate structures of the NMOS device region II and the PMOS device region I at the same time, so as to save the process flow and reduce the process cost.
Referring to fig. 15, an interlayer dielectric layer 160 is formed on the substrate on the side where the first epitaxial layer is formed, to cover the surface of the substrate.
The step of forming the interlayer dielectric layer 160 may refer to the description in the previous embodiment, and this embodiment will not be repeated.
Referring to fig. 16, a metal contact hole 170 exposing the first epitaxial layer is formed on the interlayer dielectric layer.
The step of forming the metal contact hole 170 may refer to the description in the previous embodiment, and the description of this embodiment is omitted.
Referring to fig. 17, in this embodiment, the step of forming the second epitaxial layer in the metal contact hole specifically includes: a doped semiconductor layer 220 is formed within the metal contact hole.
Wherein the step of forming the doped semiconductor layer 220 in the metal contact hole 170 includes: forming a patterned N-type mask layer (not shown in the figure), wherein the N-type mask layer exposes the NMOS device region II and covers the PMOS device region I; forming an N-type doped semiconductor layer in the metal contact hole of the NMOS device region II by taking the N-type mask layer as a mask; forming a patterned P-type mask layer, wherein the P-type mask layer exposes the PMOS device region I and covers the NMOS device region II; and forming a P-type doped semiconductor layer in the metal contact hole of the PMOS device region I by taking the P-type mask layer as a mask.
The N-type mask layer and the P-type mask layer can be photoresist masks or hard masks. The forming sequence of the N-type doped semiconductor layer and the P-type doped semiconductor layer can be adjusted according to actual requirements. After forming one type of doped semiconductor layer, the mask layer is removed and another type of doped semiconductor layer is formed.
To further improve the electrical performance of the device, the doped semiconductor layer 220 is homogenous with the intrinsic semiconductor layer 210.
In this embodiment, a selective epitaxy process may be used to form a doped semiconductor layer, and in the process of forming the doped semiconductor layer, P-type ions are self-doped in situ to form the P-type doped semiconductor layer, and N-type ions are self-doped in situ to form the N-type doped semiconductor layer.
Referring to fig. 18 to 19, schematic structural views corresponding to partial steps of a method for forming a semiconductor structure according to another embodiment of the present invention are shown.
Unlike the previous embodiment, referring to fig. 18, after the step of forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer, the intrinsic semiconductor layer in the metal contact hole is removed before the step of forming a doped semiconductor layer in the metal contact hole, forming an epitaxial structure hole 310 communicating with the metal contact hole.
The epitaxial structure holes 310 are used to provide a process basis for the subsequent formation of a second epitaxial layer and metal electrodes. By removing the intrinsic semiconductor layer, the degradation of the electrical performance of the device due to too few carriers of the intrinsic semiconductor layer is avoided.
After the intrinsic semiconductor layer 210 in the metal contact hole 170 is removed to form the epitaxial structure hole 310, a doped semiconductor layer is formed in the subsequent epitaxial structure hole 310 and the metal contact hole 170 to serve as a source-drain doped layer of the device, so that the electrical performance of the device is improved.
In this embodiment, the intrinsic semiconductor layer in the metal contact hole may be removed by a wet etching or dry etching process.
Referring to fig. 19, a doped semiconductor layer 320 is formed within the metal contact hole.
Wherein the step of forming the doped semiconductor layer 320 in the metal contact hole 170 includes: forming a patterned N-type mask layer (not shown in the figure), wherein the N-type mask layer exposes the NMOS device region II and covers the PMOS device region I; forming an N-type doped semiconductor layer in the metal contact hole of the NMOS device region II by taking the N-type mask layer as a mask; forming a patterned P-type mask layer, wherein the P-type mask layer exposes the PMOS device region I and covers the NMOS device region II; and forming a P-type doped semiconductor layer in the metal contact hole of the PMOS device region I by taking the P-type mask layer as a mask.
In this embodiment, in the step of forming the N-type doped semiconductor layer in the metal contact hole of the NMOS device region II, the method further includes: forming an N-type doped semiconductor layer 320 in the epitaxial structure hole of the NMOS device region II; the step of forming the P-type doped semiconductor layer in the metal contact hole of the PMOS device region I further comprises the following steps: a P-type doped semiconductor layer 330 is formed within the epitaxial structure hole of the PMOS device region I.
In this embodiment, the source-drain doped layer is formed only by the doped epitaxial layer, so that the electrical performance of the device is further improved.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure comprises a substrate, wherein a grid structure is formed on the substrate; an interlayer dielectric layer 160 covering the surface of the substrate, wherein the interlayer dielectric layer 160 is positioned at one side of the substrate where the gate structure is formed; an epitaxial structure hole (150 in the figure) located in the interlayer dielectric layer 160, the epitaxial structure hole being located at two sides of the gate structure, and the bottom surface extending to the substrate; a metal contact hole (a portion composed of 180 and 190) in communication with the epitaxial structure hole, the metal contact hole extending to a surface of the interlayer dielectric layer 160; the source-drain doped layers (150 and 180) are positioned in the epitaxial structure holes and the metal contact holes, and the surfaces of the source-drain doped layers are higher than the bottom surfaces of the metal contact holes and lower than the surfaces of the interlayer dielectric layers; and a metal electrode 190 located in the metal contact hole.
In this embodiment, the substrate has a fin field effect transistor thereon, and thus the substrate includes a substrate 100 and a plurality of discrete fins protruding from the substrate. Correspondingly, the grid structure spans across the fin parts and covers partial tops and partial side walls of the fin parts; the epitaxial structure hole extends to fin portions on two sides of the grid electrode. In other embodiments, the substrate is used to form a planar transistor, and correspondingly, the substrate is a planar substrate.
In this embodiment, taking the fin field effect transistor as a CMOS device as an example, the substrate 100 includes a PMOS device region I and an NMOS device region II, where the substrate 100 of the PMOS device region I and the NMOS device region II each have a discrete fin portion. Specifically, the fin portion located on the PMOS device region I substrate 100 is a first fin portion 110, and the fin portion located on the NMOS device region II substrate 100 is a second fin portion 120.
In other embodiments, where the finfet includes only NMOS devices, the substrate includes only NMOS device regions; when the fin field effect transistor only comprises a PMOS device, the substrate only comprises a PMOS device region.
Correspondingly, the gate structure in the PMOS device region I spans the first fin 110 and covers a portion of the top surface and the sidewall surface of the first fin 110; the gate structure in the NMOS device region II spans the second fin 120 and covers a portion of the top surface and the sidewall surface of the second fin 120.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 100 may also have an interface layer formed on the surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
The substrate further comprises an isolation structure 130, the isolation structure 130 covers part of the side wall of the fin portion, and the top of the isolation structure 130 is lower than the top of the fin portion.
The gate structure is a gate dielectric layer including a portion of the top and a portion of the sidewall of the fin and a gate layer overlying the gate dielectric layer. The gate layer is a stacked structure, and in other embodiments, the gate structure may be a single-layer structure.
The interlayer dielectric layer 160 is used to achieve electrical isolation between adjacent semiconductor structures, and thus, the material of the interlayer dielectric layer 160 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide.
The epitaxial structure holes are positioned on two sides of the grid structure, the bottom surfaces of the epitaxial structure holes extend to the fin parts, and the epitaxial structure holes are used for arranging source-drain doped layers together with the metal contact holes to serve as source/drain regions of the device.
And grooves are formed in fin parts at two sides of the gate structure, and the epitaxial structure holes extend into the grooves.
The metal contact hole is communicated with the epitaxial structure hole and is used for arranging part of source-drain doped layers and metal electrodes.
In this embodiment, in the same device, the epitaxial structure holes on the fin portions on the same side of the gate structure are connected to one metal contact hole. Therefore, the metal contact hole in the embodiment has larger size, so that the process difficulty can be reduced, and the production efficiency can be improved. Meanwhile, the size of the metal contact hole is increased, the size of a second epitaxial layer formed subsequently is further increased, and the performance of the device is further improved.
The source-drain doped layer is not only formed in the epitaxial structure hole, but also further formed in the metal contact hole, so that the size of the source-drain doped layer is increased, and the performance of the device is improved.
The source-drain doped layer comprises: a first epitaxial layer 150 on the substrate and a second epitaxial layer 180 on the first epitaxial layer 150; the first epitaxial layer 150 is located in the epitaxial structure hole, and the second epitaxial layer 180 is located in the metal contact hole; the second epitaxial layer 180 covers the bottom surface of the metal contact hole, and the surface is lower than the surface of the interlayer dielectric layer 160.
In this embodiment, grooves are formed in the fin portions on both sides of the gate structure, and the first epitaxial layer 150 is partially embedded in the grooves.
In this embodiment, the first epitaxial layer 150 is a doped semiconductor layer; the second epitaxial layer 180 is an intrinsic semiconductor layer.
The substrate comprises an NMOS device region II and a PMOS device region I, and the gate structures are formed on the substrates of the NMOS device region II and the PMOS device region I; the doped semiconductor layer positioned in the NMOS device region is an N-type doped semiconductor layer; the doped semiconductor layer in the PMOS device region is a P-type doped semiconductor layer.
The intrinsic semiconductor layer is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide; the N-type doped semiconductor layer and the P-type doped semiconductor layer are homogenous with the intrinsic semiconductor layer.
In this embodiment, the intrinsic semiconductor layer is silicon, and the N-type doped semiconductor layer and the P-type doped semiconductor layer are silicon materials doped with corresponding ions. Specifically, the P-type ions include B, ga or In, and the N-type ions include P, as or Sb.
Referring to fig. 17, in another embodiment of the present invention, the first epitaxial layer is an intrinsic semiconductor layer 210; the second epitaxial layer is a doped semiconductor layer 220.
The substrate comprises an NMOS device region II and a PMOS device region I, wherein the doped semiconductor layer positioned in the NMOS device region II is an N-type doped semiconductor layer; the doped semiconductor layer in the PMOS device region I is a P-type doped semiconductor layer. The intrinsic semiconductor layer 210 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the N-type doped semiconductor layer and the P-type doped semiconductor layer are homogenous with the intrinsic semiconductor layer.
In this embodiment, the intrinsic semiconductor layer 210 is silicon, and the N-type doped semiconductor layer and the P-type doped semiconductor layer are silicon materials doped with corresponding ions. Specifically, the P-type ions include B, ga or In, and the N-type ions include P, as or Sb.
The grid structures are formed on the substrates of the NMOS device region II and the PMOS device region I; the doped semiconductor layer 210 in the NMOS device region is an N-type doped semiconductor layer; the doped semiconductor layer 210 in the PMOS device region is a P-type doped semiconductor layer.
Referring to fig. 20, in a further embodiment of the present invention, the source-drain doped layer is a doped semiconductor layer.
The substrate comprises an NMOS device region II and a PMOS device region I, and the gate structures are formed on the substrates of the NMOS device region II and the PMOS device region I; the doped semiconductor layer positioned in the NMOS device region is an N-type doped semiconductor layer; the doped semiconductor layer in the PMOS device region is a P-type doped semiconductor layer.
The N-type doped semiconductor layer and the P-type doped semiconductor layer are silicon materials doped with corresponding ions. Specifically, the P-type ions include B, ga or In, and the N-type ions include P, as or Sb.
In this embodiment, the source-drain doped layer is formed only by the doped epitaxial layer, so that the electrical performance of the device is further improved.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and no further description is given here.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is formed on the substrate;
forming a first epitaxial layer on the substrate at two sides of the grid structure;
forming an interlayer dielectric layer covering the surface of the substrate on one side of the substrate on which the first epitaxial layer is formed;
forming a metal contact hole exposing the first epitaxial layer on the interlayer dielectric layer;
forming a second epitaxial layer in the metal contact hole, wherein the second epitaxial layer covers the bottom surface of the metal contact hole, and the surface of the second epitaxial layer is lower than the surface of the interlayer dielectric layer;
forming a metal electrode in the metal contact hole;
the step of forming the first epitaxial layer on the substrate at two sides of the gate structure specifically comprises the following steps: forming doped semiconductor layers on the substrates at two sides of the grid structure; the step of forming the second epitaxial layer in the metal contact hole specifically comprises the following steps: forming an intrinsic semiconductor layer in the metal contact hole;
or, the step of forming the first epitaxial layer on the substrate at two sides of the gate structure specifically includes: forming an intrinsic semiconductor layer on the substrate at two sides of the gate structure; the step of forming the second epitaxial layer in the metal contact hole specifically comprises the following steps: and forming a doped semiconductor layer in the metal contact hole.
2. The method of claim 1, wherein in the step of providing a base, the base comprises a substrate and a plurality of discrete fins protruding from the substrate; the grid structure spans across the fin parts and covers partial tops and partial side walls of the fin parts;
the step of forming a first epitaxial layer on the substrate at two sides of the gate structure comprises the following steps: and forming a first epitaxial layer on fin parts at two sides of the grid electrode structure.
3. The method of claim 2, wherein in the step of forming a metal contact hole in the interlayer dielectric layer exposing the first epitaxial layer, the first epitaxial layer on the plurality of fins on the same side of the gate structure is exposed in one metal contact hole.
4. The method of claim 1, wherein in the step of providing a substrate, the substrate includes an NMOS device region and a PMOS device region, the NMOS device region and the PMOS device region each having the gate structure formed therein;
the step of forming a doped semiconductor layer on the substrate at two sides of the gate structure comprises the following steps: forming an N-type doped semiconductor layer in the NMOS device region, wherein the N-type doped semiconductor layer is positioned on a substrate at two sides of a grid structure in the NMOS device region; forming a P-type doped semiconductor layer in the PMOS device region, wherein the P-type doped semiconductor layer is positioned on the substrate at two sides of the grid structure in the PMOS device region;
The step of forming the intrinsic semiconductor layer in the metal contact hole comprises the following steps: and simultaneously forming an intrinsic semiconductor layer in the metal contact holes of the NMOS device region and the PMOS device region.
5. The method of claim 1, wherein in the step of providing a substrate, the substrate comprises an NMOS device region and a PMOS device region, wherein the NMOS device region and the PMOS device region each have a gate structure formed therein;
the step of forming the intrinsic semiconductor layer on the substrate at two sides of the gate structure comprises the following steps: simultaneously forming an intrinsic semiconductor layer on the substrate at two sides of the grid structure of the NMOS device region and the PMOS device region;
the step of forming a doped semiconductor layer in the metal contact hole comprises the following steps: forming a patterned N-type mask layer, wherein the N-type mask layer exposes the NMOS device region and covers the PMOS device region; forming an N-type doped semiconductor layer in the metal contact hole of the NMOS device region by taking the N-type mask layer as a mask; forming a patterned P-type mask layer, wherein the P-type mask layer exposes the PMOS device region and covers the NMOS device region; and forming a P-type doped semiconductor layer in the metal contact hole of the PMOS device region by taking the P-type mask layer as a mask.
6. The method of claim 5, wherein after the step of forming a metal contact hole in the interlayer dielectric layer exposing the first epitaxial layer, the method further comprises, prior to the step of forming a doped semiconductor layer in the metal contact hole:
and removing the intrinsic semiconductor layer in the metal contact hole to form an epitaxial structure hole communicated with the metal contact hole.
7. The method of claim 6, wherein forming an N-doped semiconductor layer within the metal contact hole of the NMOS device region further comprises: forming an N-type doped semiconductor layer in the epitaxial structure hole of the NMOS device region;
the step of forming the P-type doped semiconductor layer in the metal contact hole of the PMOS device region further comprises the following steps: and forming a P-type doped semiconductor layer in the epitaxial structure hole of the PMOS device region.
8. The method of claim 4 or 5, wherein the material of the intrinsic semiconductor layer is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the N-type doped semiconductor layer and the P-type doped semiconductor layer are homogenous with the intrinsic semiconductor layer.
9. The method of claim 1, wherein a second epitaxial layer is formed within the metal contact hole using an epitaxial growth process.
10. A semiconductor structure, comprising:
a substrate, on which a gate structure is formed;
the interlayer dielectric layer is covered on the surface of the substrate and is positioned on one side of the substrate, on which the grid structure is formed;
the epitaxial structure holes are positioned in the interlayer dielectric layer, the epitaxial structure holes are positioned at two sides of the grid structure, and the bottom surface of the epitaxial structure holes extends to the substrate;
the metal contact hole is communicated with the epitaxial structure hole, extends to the surface of the interlayer dielectric layer, and is used for arranging a source-drain doping layer together to serve as a source/drain region of the device;
the source-drain doped layer is positioned in the epitaxial structure hole and the metal contact hole, and the surface of the source-drain doped layer is higher than the bottom surface of the metal contact hole and lower than the surface of the interlayer dielectric layer; the source-drain doped layer comprises: a first epitaxial layer on the substrate and a second epitaxial layer on the first epitaxial layer; the first epitaxial layer is positioned in the epitaxial structure hole, and the second epitaxial layer is positioned in the metal contact hole; the second epitaxial layer covers the bottom surface of the metal contact hole, and the surface of the second epitaxial layer is lower than the surface of the interlayer dielectric layer;
The first epitaxial layer is a doped semiconductor layer; the second epitaxial layer is an intrinsic semiconductor layer; alternatively, the first epitaxial layer is an intrinsic semiconductor layer; the second epitaxial layer is a doped semiconductor layer;
and the metal electrode is positioned in the metal contact hole.
11. The semiconductor structure of claim 10, wherein the base includes a substrate and a discrete plurality of fins protruding from the substrate thereon, the gate structure spanning the plurality of fins and covering portions of top and sidewalls of the plurality of fins; the epitaxial structure hole extends to fin portions on two sides of the grid electrode.
12. The semiconductor structure of claim 11, wherein epitaxial structure holes on the plurality of fins on a same side of the gate structure communicate into one metal contact hole.
13. The semiconductor structure of claim 10, wherein the substrate comprises an NMOS device region and a PMOS device region, the NMOS device region and the PMOS device region each having the gate structure formed therein; the doped semiconductor layer positioned in the NMOS device region is an N-type doped semiconductor layer; the doped semiconductor layer in the PMOS device region is a P-type doped semiconductor layer.
14. The semiconductor structure of claim 13, wherein the intrinsic semiconductor layer material is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the N-type doped semiconductor layer and the P-type doped semiconductor layer are homogenous with the intrinsic semiconductor layer.
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