CN103633027A - Method for forming double epitaxial layers of source-drain area - Google Patents
Method for forming double epitaxial layers of source-drain area Download PDFInfo
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- CN103633027A CN103633027A CN201210303567.7A CN201210303567A CN103633027A CN 103633027 A CN103633027 A CN 103633027A CN 201210303567 A CN201210303567 A CN 201210303567A CN 103633027 A CN103633027 A CN 103633027A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Abstract
The invention relates to a method for forming double epitaxial layers of a source-drain area. The method comprises: providing a semiconductor substrate which at least includes a first gate and a second gate; forming an epitaxial barrier layer on the semiconductor substrate; removing the first gate and the epitaxial barrier layer on a source-drain area at the two sides through etching to expose the semiconductor substrate, and growing a first semiconductor material layer in an epitaxial manner in the source-drain area at the two sides of the first gate to form a first uplift source-drain; and removing the residual epitaxial barrier layer through etching, growing a second semiconductor material layer in an epitaxial manner in the source-drain area at the two sides of the second gate, and forming a second uplift source-drain, wherein the first uplift source-drain is in the shape of a closed angle so as to inhibit the epitaxial growth of the second semiconductor material layer on the first uplift source-drain. By using the method provided by the invention, the epitaxial barrier layer is formed only once, and the process steps are simplified.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of method that forms the two epitaxial loayers of source-drain area.
Background technology
Often need to be at two kinds of different semi-conducting materials of zones of different epitaxial growth of Semiconductor substrate when preparing semiconductor device, for example usually need to leak two kinds of different semi-conducting materials of epitaxial growth in the source of NMOS and PMOS, and often need to form twice extension barrier layer while leaking at present the different semi-conducting material of two kinds of epitaxial growths in the source of NMOS and PMOS, concrete method is: semi-conductive substrate is provided, source-drain area and the grid on described substrate with NMOS and PMOS, in order to form a kind of semi-conducting material on NMOS, need to leak deposition in the source of NMOS and PMOS and form extension barrier layer, then the extension barrier layer on the leakage of described NMOS source and grid is removed in etching, at nmos area zone epitaxial growth semi-conducting material I, then remove extension barrier layer on PMOS to described substrate, then on the leakage of the source of NMOS and PMOS and grid, deposit the second extension barrier layer, the second extension barrier layer described in etching on PMOS, the second extension barrier layer on reservation NMOS is as protective layer, epitaxial growth of semiconductor material II above described PMOS, after epitaxial growth, the second extension barrier layer on described NMOS is removed in etching again.Therefore in this preparation process, need to leak and deposit extension barrier layer twice in the source of described NMOS and PMOS, the extension barrier layer of twice formation all needs to open by etching, and after its barrier effect completes, need to remove, serve unnecessary step to whole technique band.
The processing step of current two kinds of different semi-conducting materials of zones of different epitaxial growth in Semiconductor substrate is very loaded down with trivial details, increases a lot of unnecessary steps, and efficiency is low, therefore need to improve current method.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of method that forms the two epitaxial loayers of source-drain area, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, at least comprises first grid and second grid;
In described Semiconductor substrate, form extension barrier layer;
The extension barrier layer on described first grid and both sides source-drain area is removed in etching, exposes described Semiconductor substrate, and at source-drain area epitaxial growth first semiconductor material layer of described first grid both sides, forms the first lifting source and leak;
Remaining described extension barrier layer is removed in etching, and source-drain area epitaxial growth the second semiconductor material layer in described second grid both sides forms the second lifting source and leaks,
Wherein, described the first lifting source leaks and is angular shape, the epitaxial growth of leaking at described the first lifting source to suppress described the second semi-conducting material.
As preferably, the cross section that described the first lifting source leaks is triangle.
As preferably, the crystal face that described the first lifting source leaks is (111) face.
As preferably, described the first semiconductor material layer is SiGe material layer.
As preferably, described the second semiconductor material layer is Si material layer or SiC material layer.
As preferably, described extension barrier layer is silicon dioxide or silicon nitride layer.
As preferably, cross the extension barrier layer on the source-drain area that etching removes described first grid and both sides, and the source-drain area in described first grid both sides forms " ∑ " shape depression.
As preferably, cross etching and remove residue described extension barrier layer, and form depression at described second grid and both sides source-drain area.
As preferably, the part that described first grid and both sides source-drain area are PMOS, correspondingly, the part that described second grid and both sides source-drain area are NMOS.
The invention provides a kind of method that two epitaxial loayers are leaked in source that forms, first in Semiconductor substrate, form extension barrier layer, chemical wet etching is opened PMOS region, extension the first semi-conducting material forms wedge angle, SiGe for example, now only be left (111) face, then remove extension barrier layer, NMOS and PMOS source are leaked to extension the second semi-conducting material simultaneously, for example Si or SiC, now (111) face extension speed is very slow, almost can ignore, only in NMOS source, leak growth Si or SiC, the contact area that has increased contact hole is leaked in the source that simultaneously forms wedge angle, thereby reduce contact resistance.Method of the present invention only need to form extension barrier layer one time, simplifies processing step.Utilize the first semi-conducting material and the second semi-conducting material in the difference of the epitaxial growth speed of different crystal faces, can optionally in territory, nmos area, grow.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1d is the generalized section of the two epitaxial loayer processes of preparation in the present invention;
Fig. 2 is the process chart that the present invention prepares two epitaxial loayers.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed description be proposed in following description, to illustrate that the present invention forms the method for the two epitaxial loayers of source-drain area.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Below, the method for only preparing described pair of epitaxial loayer by one deck extension barrier layer the present invention being proposed with reference to Fig. 1 a-d and Fig. 2 is carried out detailed explanation.
First, as shown in Figure 1a, semi-conductive substrate 201 is provided, and described Semiconductor substrate 201 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In addition, in Semiconductor substrate 201, can be defined active area.On this active area, can also include other active device, for convenient, shown in do not indicate in figure.
Then on described substrate, form shallow trench isolation from 204, described shallow trench isolation can be selected method conventional in prior art from 204 formation method, for example first, forms successively the first oxide skin(coating) and the first nitride layer in Semiconductor substrate 201.Then, carry out dry etch process, successively the first nitride layer, the first oxide skin(coating) and Semiconductor substrate 201 are carried out to etching to form groove 204.Particularly, can on the first nitride layer, form the figuratum photoresist layer of tool, take this photoresist layer carries out dry etching to the first nitride layer as mask, with by design transfer to the first nitride layer, and take photoresist layer and the first nitride layer and the first oxide skin(coating) and Semiconductor substrate 201 are carried out to etching as mask, to form groove.Therefore certainly can also adopt other method to form groove, due to this technique, think known in the artly, no longer be described further.
Then, in groove, fill shallow trench isolated material, to form the first sub-fleet plough groove isolation structure 302.Particularly, can on the first nitride layer He in groove, form shallow trench isolated material, described shallow trench isolated material can be silica, silicon oxynitride and/or other existing advanced low-k materials; Carry out chemical mechanical milling tech and stop on the first nitride layer, to form, thering is fleet plough groove isolation structure.
Described shallow trench isolation can be divided into described Semiconductor substrate territory, nmos area and PMOS region from 204 in the present invention.
Then, in described PMOS region, form PMOS grid 302 and source-drain area, in territory, described nmos area, form NMOS grid 202 and source-drain area.Particularly, deposition oxide insulating barrier, gate material layers successively in described Semiconductor substrate, then described oxide insulating layer, gate material layers are carried out to etching and obtain grid structure, described process also comprises the formation of gate spacer wall, described formation method can be selected ability common method, does not repeat them here.Wherein, described oxide insulating layer is preferably silicon dioxide, its formation method can form insulating barrier for Semiconductor substrate described in deposition of silica material layer or high-temperature oxydation, described gate material layers can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; Conductive metal oxide layer can comprise yttrium oxide (IrO
2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer.
As preferably, after forming described grid structure, can also further be included in the step that grid both sides form source-drain area, particularly, can form by the method for Implantation or diffusion described source-drain area, as further preferably, after carrying out Implantation or diffusion, can further include the step of a thermal annealing.Described annealing steps is generally that described substrate is placed under the protection of high vacuum or high-purity gas; being heated to certain temperature heat-treats; at high-purity gas of the present invention, be preferably nitrogen or inert gas; the temperature of described thermal anneal step is 800-1200 ℃, and the described thermal anneal step time is 1-300s.As further preferred, can select rapid thermal annealing in the present invention, can select a kind of in following several mode: pulse laser short annealing, the short annealing of the Pulse Electric philosophical works, ion beam short annealing, continuous wave laser short annealing and incoherent wideband light source (as halogen lamp, arc lamp, graphite heating) short annealing etc., but be not limited to examples cited.
In described Semiconductor substrate, form extension barrier layer 203, described extension barrier layer can be silicon dioxide layer or silicon nitride layer, and the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method can be passed through in described extension barrier layer 203.As example, described silicon nitride layer can be by ammonia and dichlorosilane at the temperature of 750 ℃ of left and right, adopt low-pressure chemical vapor deposition to form.
As shown in Figure 1 b, the extension barrier layer in PMOS region described in etching, particularly, the extension barrier layer that described in etching, leak in PMOS grid 302 and source, both sides, to expose described Semiconductor substrate, described engraving method can be selected the conventional dry method of ability or wet etching, wherein in order to remove more thoroughly described extension barrier layer, be preferably formed in the present invention etching, in source-drain area formation " ∑ " shape depression of described PMOS.
Then at source-drain area epitaxial growth the first semi-conducting material of described PMOS, to form the first lifting source, leak 205, as shown in Fig. 1 c, particularly, the preferred SiGe of described the first semi-conducting material in an embodiment of the present invention; Described extension can be selected a kind of in reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy, molecular beam epitaxy in the present invention.Wherein, the shape that described the first lifting source leaks is tip-angled shape, now, remaining crystal face is (111) face, the cross section that described lifting source leaks is triangle, the special shape leaking just because of described the first lifting source, can utilize the difference of material epitaxial growth speed on different crystal faces, thereby realizes optionally growth.In addition,, because the source leakage forming has special angular shape, leak in the source of described wedge angle has increased the contact area of contact hole, thereby reduces contact resistance.
With reference to Fig. 1 d, remove the extension barrier layer on described NMOS, comprise the epitaxial loayer in the source leakage of removing NMOS grid and both sides, expose described Semiconductor substrate, in the present invention, in order thoroughly to remove described extension barrier layer, can form etching, in addition, all right selective etch, leaks and forms depression with the source at described NMOS in the present invention.
Follow epitaxial growth the second semiconductor material layer 206 above described NMOS source-drain area and described the first lifting source leakage 205, the selection of described the second semiconductor material layer not arbitrarily, preferably from described the first semiconductor material layer discrepant material of epitaxial growth speed on different crystal faces, if for example the first semiconductor material layer is selected SiGe in the present invention, described the second semiconductor material layer is preferably Si or SiC material layer, utilize SiGe and Si and SiC in the difference of the epitaxial growth speed of different crystal faces, can be optionally at territory, nmos area growth Si or SiC, from Fig. 1 d, can find out at Si or the SiC layer of the first lifting source leakage growth very thin, can ignore completely.
The formation method of described the second semiconductor material layer 206 can be selected a kind of in reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy, molecular beam epitaxy.The epitaxially grown silicon of take is below described further as example: by hydrogen (H
2) gas carries silicon tetrachloride (SiCl
4) or trichlorosilane (SiHCl
3), silane (SiH
4) or dichloro hydrogen silicon (SiH
2cl
2) etc. enter the reative cell that is equipped with silicon substrate, at reative cell, carry out high-temperature chemical reaction, make the reduction of siliceous reacting gas or thermal decomposition, the silicon atom producing epitaxial growth on substrate silicon surface.In this step, can select 98.5% highly diluted ratio, the temperature of reaction is 1500-1800 ℃, and to control air pressure be about 1pa, can be that on the substrate of 200 ℃, epitaxial growth obtains 200nm or above silicon thin film in temperature, in this step, can also regulate temperature, time to control silicon thin film.
After epitaxial growth the second semi-conducting material, at leakage position, described NMOS source, form the second lifting source and leak 206, as shown in Figure 1 d.
With reference to Fig. 2, wherein show the method flow diagram that the present invention prepares the two epitaxial loayers of source-drain area, for schematically illustrating the flow process of whole manufacturing process.
The extension barrier layer on described first grid and both sides source-drain area is removed in step 203 etching, exposes described Semiconductor substrate, and epitaxial growth the first semiconductor material layer, forms the first lifting source and leaks, and wherein said the first lifting source leaks and is angular shape;
Residue described extension barrier layer is removed in step 204 etching, source-drain area epitaxial growth the second semiconductor material layer in second grid both sides, and the source-drain area in described second grid both sides forms the second lifting source and leaks.
The invention provides a kind of method that two epitaxial loayers are leaked in source that forms, first in Semiconductor substrate, form extension barrier layer, chemical wet etching is opened PMOS region, extension the first semi-conducting material forms wedge angle, SiGe for example, now only be left (111) face, then remove extension barrier layer, NMOS and PMOS source are leaked to extension the second semi-conducting material simultaneously, for example Si or SiC, now (111) face extension speed is very slow, almost can ignore, only in NMOS source, leak growth Si or SiC, the contact area that has increased contact hole is leaked in the source that simultaneously forms wedge angle, thereby reduce contact resistance.。Method of the present invention only need to form extension barrier layer one time, simplifies processing step.Utilize the first semi-conducting material and the second semi-conducting material in the difference of the epitaxial growth speed of different crystal faces, can optionally in territory, nmos area, grow.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a method that forms the two epitaxial loayers of source-drain area, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, at least comprises first grid and second grid;
In described Semiconductor substrate, form extension barrier layer;
The extension barrier layer on described first grid and both sides source-drain area is removed in etching, exposes described Semiconductor substrate, and at source-drain area epitaxial growth first semiconductor material layer of described first grid both sides, forms the first lifting source and leak;
Remaining described extension barrier layer is removed in etching, and source-drain area epitaxial growth the second semiconductor material layer in described second grid both sides forms the second lifting source and leaks,
Wherein, described the first lifting source leaks and is angular shape, the epitaxial growth of leaking at described the first lifting source to suppress described the second semi-conducting material.
2. method according to claim 1, is characterized in that, the cross section that described the first lifting source leaks is triangle.
3. method according to claim 1, is characterized in that, the crystal face that described the first lifting source leaks is (111) face.
4. method according to claim 1, is characterized in that, described the first semiconductor material layer is SiGe material layer.
5. method according to claim 1, is characterized in that, described the second semiconductor material layer is Si material layer or SiC material layer.
6. method according to claim 1, is characterized in that, described extension barrier layer is silicon dioxide or silicon nitride layer.
7. method according to claim 1, is characterized in that, cross the extension barrier layer on the source-drain area that etching removes described first grid and both sides, and the source-drain area in described first grid both sides forms " ∑ " shape depression.
8. method according to claim 1, is characterized in that, crosses etching and removes residue described extension barrier layer, and form depression at described second grid and both sides source-drain area.
9. method according to claim 1, is characterized in that, the part that described first grid and both sides source-drain area are PMOS, correspondingly, the part that described second grid and both sides source-drain area are NMOS.
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| CN105489555A (en) * | 2014-09-19 | 2016-04-13 | 中国科学院微电子研究所 | Manufacturing method of semiconductor device |
| CN112103249A (en) * | 2019-06-18 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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