CN103000499A - Germanium-silicon-boron epitaxial layer growth method - Google Patents
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Abstract
The invention discloses a germanium-silicon-boron epitaxial layer growth method. The method includes: firstly, enabling SiGe base layers to be subjected to selective epitaxial growth prior to selective epitaxial growth of SiGeB epitaxial layers or selective epitaxial growth of SiGe seed layers when the SiGe seed layers exist; then, subjecting the grown SiGe base layers to dry etching so that the SiGe base layers at the bottom of trenches are removed by dry etching but the SiGe base layers on the side walls of the trenches are left; and finally, on the structure, subjecting the SiGeB epitaxial layers to selective epitaxial growth according to existing process. Therefore, the performance of the grown epitaxial layers is improved.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of germanium silicon boron outer layer growth method.
Background technology
At present, semi-conductor industry is growth of device on wafer (wafer) device side of silicon substrate mainly, for example, mos field effect transistor (Metal-Oxide Semiconductor Field Effect Transistor, MOSFET) device architecture includes the source region, source electrode, drain and gate, wherein, described active area is arranged in the semiconductor silicon substrate, described grid is positioned at the active area top, carry out Implantation in the active area of described grid both sides and form source electrode and drain electrode, the grid below has conducting channel, between described grid and the conducting channel gate dielectric layer is arranged.Dissimilar according to Implantation, cavity type mos field effect transistor (PMOS) and electron type mos field effect transistor (NMOS).
For many years, the approach that provides along Moore's Law, people adopt always and MOSFET is carried out the equal proportion micro increase device speed, yet along with the dwindling of MOSFET size, conventional equal proportion micro method has run into the series of problems take short-channel effect as core.For example, how the scaled down of supply voltage increases the problem of drive current (Idsat) density when reducing dynamic power consumption, therefore how to improve carrier mobility and becomes the key that keeps the MOSFET performance.
Because the average mobility in hole is lower three times than electronics in the strainless silicon substrate, so improve the focus that the interior hole mobility of PMOS conducting channel becomes concern.
In recent years, strain engineering technology (strain engineering) is considered to one of key technology that Moore's Law is extended.So-called strain gauge technique, namely by introducing local simple tension or compressive type of stress to the conducting channel of MOSFET, promote the interior carrier mobility of conducting channel of MOSFET, thereby in the attenuation of gate-dielectric layer thickness or situation about remaining unchanged, drive current is increased substantially, finally improve the device performance of MOSFET.For the conducting channel in the silicon substrate, the possible constructions that can produce local unidirectional strain has SiGeB and Si
yC
1-yB must design respectively for PMOS and NMOS the structure of local unidirectional strain.Wherein, the mobility of PMOS being introduced compressive type of stress increase hole is called the strain of local Uniaxial Compression type, and the mobility of NMOS introducing tensile type of stress raising electronics is called local simple tension strain.
The strain engineering technology that is applied at present mainly contains: silicon nitride (SiN) cover layer of deposition stretching or compressive type of stress; Increase in dielectric (PMD) structure before (STI) and the metallization at shallow trench isolation and to stretch or the oxide skin(coating) of compressive type of stress, and source, the drain region of germanium silicon boron (SiGeB) epitaxial loayer filling etching or rising.
Source, drain region (Recessed SiGe S/D) that the SiGeB epitaxial loayer is filled etching are a kind of strain engineering technology that is widely used, the method elder generation partial etching is removed source, the drain electrode of grid both sides in the PMOS device architecture, pass through again method growth SiGeB epitaxial loayer above the source after the etching, drain electrode of selective epitaxial growth, the compressive type of stress that is imported by the SiGeB epitaxial loayer is conducted to the conducting channel of MOSFET, finally improves the mobility in hole among the PMOS.
Source, drain region selective epitaxial growth SiGeB epitaxial loayer at PMOS have following advantage: first, as indicated above, thereby the lattice constant of SiGeB is different from Si makes the conducting channel in the silicon substrate produce strain, is used for improving the mobility of holoe carrier; The second, SiGeB has the energy gap less than Si, and the potential barrier between semiconductor and silicide (Silicide) reduces like this; The 3rd, germanium has increased doping B element (dopant) thereby dissolving in Si reduced resistance and the diffusion resistance of source, drain region.These three factors have just promoted the drive current of MOSFET, have increased device speed.
Source, drain region selective epitaxial growth SiGeB epitaxial loayer technique at PMOS in the prior art comprise following 3 steps, and the technological process of epitaxial growth SiGeB epitaxial loayer in the prior aries is described in conjunction with Fig. 2～4:
In this step, the preliminary treatment of wafer is comprised oxide layer and the impurity of removing surface of silicon, whether need must consider back of the body envelope (backseal) to reduce the auto-doping phenomenon in the follow-up selective epitaxial growth process for heavily doped silicon substrate.Generally all need to pass into the step of hydrogen (H2) and baking (bake), its purpose is oxide layer and other impurity of original position (in-situ) removal surface of silicon, is that clean surface of silicon is prepared in follow-up epitaxial deposition.
After the source on step 101, silicon substrate 200 surfaces, the drain region etched recesses 201, in groove 201 superficial growth SiGe Seed Layer 204, form cross-sectional view as shown in Figure 2;
In this step, as shown in Figure 2, be the STI207 isolation between the active area, the source electrode in the active area and drain electrode are arranged in the silicon substrate 200 of gate oxide 202 both sides of grid 203 and grid 203 belows, and etching forms groove 201 in the silicon substrate 200 of source, drain region; Groove 201 epontic SiGe Seed Layer 204, Ge content wherein is lower than the Ge content in the SiGeB epitaxial loayer that forms in the subsequent step 102, the lattice constant of the SiGe Seed Layer 204 that Ge content is less is more near the lattice constant of silicon in the silicon substrate 200, as the resilient coating in the larger SiGeB epitaxial loayer process of selective epitaxial growth Ge content, be conducive to obtain high-quality SiGeB epitaxial loayer, the method of growth SiGe Seed Layer 204 is identical with subsequent step 102, all adopt selective epitaxial growth process, concrete steps are prior art, repeat no more.It should be noted that this step is not to carry out selective epitaxial growth SiGeB epitaxial loayer steps necessary before, also can omit this step.
Epitaxial growth equipment is generally reaction chamber, after wafer put into reaction chamber, in reaction chamber, pass into reacting gas 305 and heating, make the crystal structure of reacting gas growth needs in the groove 201 of silicon substrate 200, in the present embodiment, SiGe layer filling groove 201, its upper surface and silicon substrate 200 flush are lower than the height of gate oxide 202.Source, drain region growth SiGeB epitaxial loayer 306 at PMOS are used selective epitaxial process usually.So-called selective epitaxial process refers to that SiGeB epitaxial loayer 306 only is deposited on silicon substrate 200 surfaces of exposing in the groove 201, perhaps epitaxially grown SiGe Seed Layer 204 surfaces in the step 101), and the isolated area around active area, for example STI207 and grid 203 surfaces do not have forming core or growth.Owing to can be made into simultaneously hundred thousands of devices on the wafer, for each MOSFET can be independent of other device work, (PN junction isolation, carrying out local oxide isolation or STI) is out discrete with active area by the isolated area that is arranged in equally silicon substrate 200, makes between the MOSFET not interfere with each other.For selective epitaxial growth SiGeB epitaxial loayer 306, reacting gas 305 comprises deposition gases and etching gas two parts, by regulating the silane (SiH as deposition gases
4) and germane (GeH
4) mist and flow proportional as the hydrogen chloride gas (HCl) of etching gas, realization is to the accurate control of the unidirectional strain in part, so that final etch rate on isolated area is greater than deposition rate, the deposition rate of SiGeB epitaxial loayer 306 in groove 201 maximizes as far as possible, thereby realized the selectivity of low-pressure chemical vapor deposition process.Within 100 seconds the wafer in the reaction chamber is heated to more than 1100 ℃, utilizes advanced temperature detection device the technological temperature error can be controlled in the several years, the flow of reacting gas then can pass through precisely control of mass flowmenter (MFC).
When selective epitaxial growth SiGeB epitaxial loayer 306, adopt original position B to mix and form the SiGeB epitaxial loayer.
In this step, cap rock 408 materials of growth are SiGe or Si on the SiGeB epitaxial loayer 306, finally form the height of cap rock 408 greater than the height of gate oxide 202.The effect of cap rock 408 is that the effect of metal silicide is reduction source, drain resistance for the follow-up metal silicide that forms above source, drain region provides high-quality silicon crystalline structure.
But, source for PMOS, the SiGeB epitaxial loayer 306 of drain region top selective epitaxial growth or when SiGe Seed Layer 204 exists during selective epitaxial growth SiGe Seed Layer 204, because the sidewall of groove 201 and the silicon wafer of bottom are to difference, the crystal orientation of sidewall is Si (110), the silicon wafer of bottom is to being Si (100), so the SiGeB epitaxial loayer 306 of sidewall or the speed of growth of SiGe Seed Layer 204 are less than the bottom, so that the sidewall of SiGeB epitaxial loayer 306 is different with bottom formation speed, cause the SiGeB epitaxial loayer 306 that finally obtains inhomogeneous, so that the B in the SiGeB epitaxial loayer arrives channel region by sidewall diffusion easily, can cause that leakage current increases, thus so that PMOS performance reduction.
Summary of the invention
In view of this, the invention provides a kind of germanium and silicon epitaxial layer growth method, the method can improve the germanium and silicon epitaxial layer performance of growing.
Technical scheme of the present invention is achieved in that
A kind of germanium silicon boron outer layer growth method, the method comprises:
The wafer that provides is carried out the preliminary treatment of selective epitaxial growth;
After the source of the surface of silicon of described wafer, drain region etched recesses, at groove surfaces growth germanium silicon SiGe basal layer;
Employing is dry-etched in groove surfaces growth SiGe basal layer, so that the SiGe basal layer of groove 201 bottoms is etched away, the SiGe basal layer of recess sidewall stays;
Selective growth germanium silicon boron epitaxial loayer in groove, the groove of filling silicon substrate;
At the germanium silicon boron epitaxial loayer cap rock of growing.
The content of germanium is 5%～30% in the described germanium silicon SiGe basal layer.
The thickness that the SiGe basal layer of described recess sidewall stays is that 5 dusts are to 50 dusts.
The content of the germanium of described germanium and silicon epitaxial layer is 5%～35%.
Described germanium silicon boron epitaxial loayer adopts original position B to mix and forms the SiGeB epitaxial loayer, and the concentration of B is that 1E19 is to every cubic centimetre in 1E23 atom.
Describedly in groove, before the selective growth germanium and silicon epitaxial layer, also comprise:
Growth SiGe Seed Layer in groove;
The interior selective growth germanium and silicon epitaxial layer of described groove is that the SiGe Seed Layer in groove is epontic.
Can find out from such scheme, method provided by the invention is at the SiGeB of selective epitaxial growth epitaxial loayer or when the SiGe Seed Layer exists before the selective epitaxial growth SiGe Seed Layer, the selective epitaxial growth SiGe of elder generation basal layer, then after the SiGe basal layer of growing being adopted dry etching, etch away the SiGe basal layer of channel bottom, stay the SiGe basal layer of trenched side-wall, and then on this structure, carry out the growth course of the SiGeB epitaxial loayer of selective epitaxial growth according to existing technique.Like this, even the speed of growth of trenched side-wall is less than the bottom in follow-up selective epitaxial growth SiGeB epitaxial loayer process, because sidewall has stayed the SiGe basal layer, B spreads to channel region by sidewall in the SiGeB epitaxial loayer so can stop, can not cause that leakage current increases, thereby improve the performance of PMOS.
Description of drawings
Fig. 1 is the technological process of prior art epitaxial growth SiGeB epitaxial loayer;
Fig. 2～Fig. 4 is the cross-sectional view of prior art epitaxial growth SiGeB epitaxial loayer;
Fig. 5 is germanium and silicon epitaxial layer growth method flow diagram provided by the invention;
Fig. 6～Figure 10 is germanium and silicon epitaxial layer growth method section flow chart provided by the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
Can find out that from background technology the SiGeB epitaxial loayer of growth in situ can improve the performance of PMOS, yet will cause that leakage current increases if the B in the SiGeB epitaxial loayer is diffused into channel region, thus so that PMOS performance reduction.
In order to address this problem, method provided by the invention is at the SiGeB of selective epitaxial growth epitaxial loayer or when the SiGe Seed Layer exists before the selective epitaxial growth SiGe Seed Layer, the selective epitaxial growth SiGe of elder generation basal layer, then after the SiGe basal layer of growing being adopted dry etching, etch away the SiGe basal layer of channel bottom, stay the SiGe basal layer of trenched side-wall, and then on this structure, carry out again the growth course of the SiGeB epitaxial loayer of selective epitaxial growth according to existing technique.Like this, even the speed of growth of trenched side-wall is less than the bottom in follow-up selective epitaxial growth SiGeB epitaxial loayer process, because sidewall has stayed the SiGe basal layer and has played the effect on a barrier layer, so can not cause that B diffuses to channel region in the SiGeB epitaxial loayer yet, like this, improve the germanium and silicon epitaxial layer performance of growing, thereby improved the performance of PMOS.
Fig. 5 is germanium and silicon epitaxial layer growth method flow diagram provided by the invention, and in conjunction with Fig. 6～germanium and silicon epitaxial layer growth method section flow chart provided by the invention shown in Figure 10, the present invention is described in detail:
In this step, the preliminary treatment of wafer is comprised oxide layer and the impurity of removing surface of silicon, then must consideration whether need backseal to reduce the auto-doping phenomenon in the follow-up selective epitaxial growth process for heavily doped silicon substrate.The general step that all needs to pass into H2 and bake, its purpose are that original position in-situ removes oxide layer and other impurity of surface of silicon, for clean surface of silicon is prepared in follow-up epitaxial deposition.
After the source on step 501, silicon substrate 200 surfaces, the drain region etched recesses 201, at groove 201 superficial growth SiGe basal layers 601, as shown in Figure 6;
In this step, be the STI207 isolation between the active area, the source electrode in the active area and drain electrode are arranged in the silicon substrate 200 of gate oxide 202 both sides of grid 203 and grid 203 belows, and etching forms groove 201 in the silicon substrate 200 of source, drain region; Groove 201 epontic SiGe basal layers 601 adopt selective epitaxial growth process, and concrete steps are prior art, repeat no more;
In this step, the content of germanium is 5%～30% in the described SiGe basal layer 601.
Step 502, adopt and to be dry-etched in groove 201 superficial growth SiGe basal layers 601, so that the SiGe basal layer 601 of groove 201 bottoms is etched away, and the SiGe basal layer 601 of groove 201 sidewalls stays, as shown in Figure 7;
In this step, through behind the dry etching, be that 5 dusts are to 50 dusts at SiGe basal layer 601 thickness of groove 201 sidewalls.
In this step, as shown in Figure 8, groove 201 epontic SiGe Seed Layer 204, Ge content wherein is lower than the Ge content in the SiGeB epitaxial loayer that forms in the subsequent step 102, the lattice constant of the SiGe Seed Layer 204 that Ge content is less is more near the lattice constant of silicon in the silicon substrate 200, as the resilient coating in the larger SiGeB epitaxial loayer process of selective epitaxial growth Ge content, be conducive to obtain high-quality SiGeB epitaxial loayer and adopt selective epitaxial growth process.
It should be noted that this step is not to carry out selective epitaxial growth SiGeB epitaxial loayer steps necessary before, also can omit this step.
Epitaxial growth equipment is generally reaction chamber, after wafer put into reaction chamber, in reaction chamber, pass into reacting gas 305 and heating, make the crystal structure of reacting gas growth needs in the groove 201 of silicon substrate 200, in the present embodiment, SiGe layer filling groove 201, its upper surface and silicon substrate 200 flush are lower than the height of gate oxide 202.Source, drain region growth SiGeB epitaxial loayer 306 at PMOS are used selective epitaxial process usually.
So-called selective epitaxial process refers to that SiGeB epitaxial loayer 306 only is deposited on silicon substrate 200 surfaces of exposing in the groove 201, perhaps epitaxially grown SiGe Seed Layer 204 surfaces in the step 101, and the isolated area around active area, for example STI207 and grid 203 surfaces do not have forming core or growth.Owing to can be made into simultaneously hundred thousands of devices on the wafer, for each MOSFET can be independent of other device work, (PN junction isolation, carrying out local oxide isolation or STI) is out discrete with active area by the isolated area that is arranged in equally silicon substrate 200, makes between the MOSFET not interfere with each other.For selective epitaxial growth SiGeB epitaxial loayer 306, reacting gas 305 comprises deposition gases and etching gas two parts, by regulating the silane (SiH as deposition gases
4) and germane (GeH
4) mist and flow proportional as the hydrogen chloride gas (HCl) of etching gas, realization is to the accurate control of the unidirectional strain in part, so that final etch rate on isolated area is greater than deposition rate, the deposition rate of SiGe layer 306 in groove 201 maximizes as far as possible, thereby realized the selectivity of low-pressure chemical vapor deposition process.Within 100 seconds the wafer in the reaction chamber is heated to more than 1100 ℃, utilizes advanced temperature detection device the technological temperature error can be controlled in the several years, the flow of reacting gas then can pass through precisely control of mass flowmenter (MFC).
In this step, the content of germanium is 5%～35% in the described SiGe basal layer 601.
In selective epitaxial growth SiGeB epitaxial loayer 306 processes, adopt the mode B Implanted (B) of Implantation, form germanium silicon boron (SiGeB) epitaxial loayer, the dosage of described boron Implantation is that 1E14 is to every cubic centimetre in 5E15 atom;
In this step, the SiGeB epitaxial loayer also can be the SiGeB epitaxial loayer, adopts original position B to mix and forms the SiGeB epitaxial loayer, and the concentration of B is that 1E19 is to every cubic centimetre in 1E23 atom.
In this step, cap rock 408 materials of growth are SiGe or Si on the SiGeB epitaxial loayer 306, finally form the height of cap rock 408 greater than the height of gate oxide 202.The effect of cap rock 408 is that the effect of metal silicide is reduction source, drain resistance for the follow-up metal silicide that forms above source, drain region provides high-quality silicon crystalline structure.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (6)
1. germanium silicon boron outer layer growth method, the method comprises:
The wafer that provides is carried out the preliminary treatment of selective epitaxial growth;
After the source of the surface of silicon of described wafer, drain region etched recesses, at groove surfaces growth germanium silicon SiGe basal layer;
Employing is dry-etched in groove surfaces growth SiGe basal layer, so that the SiGe basal layer of groove 201 bottoms is etched away, the SiGe basal layer of recess sidewall stays;
Selective growth germanium silicon boron epitaxial loayer in groove, the groove of filling silicon substrate;
At the germanium silicon boron epitaxial loayer cap rock of growing.
2. the method for claim 1 is characterized in that, the content of germanium is 5%～30% in the described germanium silicon SiGe basal layer.
3. the method for claim 1 is characterized in that, the thickness that the SiGe basal layer of described recess sidewall stays is that 5 dusts are to 50 dusts.
4. the method for claim 1 is characterized in that, the content of the germanium of described germanium and silicon epitaxial layer is 5%～35%.
5. such as the arbitrary described method of claim 1～4, it is characterized in that described germanium silicon boron epitaxial loayer adopts original position B to mix and forms the SiGeB epitaxial loayer, the concentration of B is that 1E19 is to every cubic centimetre in 1E23 atom.
6. the method for claim 1 is characterized in that, describedly before the selective growth germanium and silicon epitaxial layer, also comprises in groove:
Growth SiGe Seed Layer in groove;
The interior selective growth germanium and silicon epitaxial layer of described groove is that the SiGe Seed Layer in groove is epontic.
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| CN103872118A (en) * | 2014-02-21 | 2014-06-18 | 上海华力微电子有限公司 | Field effect transistor and preparing method thereof |
| CN104851783A (en) * | 2014-02-14 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Growth method for germanium-silicon-boron epitaxial layer |
| CN105590852A (en) * | 2014-10-21 | 2016-05-18 | 上海华力微电子有限公司 | Method for decreasing dislocation defects of embedded silicon-germanium epitaxial growth |
| CN106783622A (en) * | 2016-12-16 | 2017-05-31 | 上海华力微电子有限公司 | High pressure low heat budget K post growth annealings high |
| US10804270B2 (en) | 2017-10-18 | 2020-10-13 | International Business Machines Corporation | Contact formation through low-tempearature epitaxial deposition in semiconductor devices |
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| CN104851783A (en) * | 2014-02-14 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Growth method for germanium-silicon-boron epitaxial layer |
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| US10804270B2 (en) | 2017-10-18 | 2020-10-13 | International Business Machines Corporation | Contact formation through low-tempearature epitaxial deposition in semiconductor devices |
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