CN106783622A - High pressure low heat budget K post growth annealings high - Google Patents
High pressure low heat budget K post growth annealings high Download PDFInfo
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- CN106783622A CN106783622A CN201611168041.7A CN201611168041A CN106783622A CN 106783622 A CN106783622 A CN 106783622A CN 201611168041 A CN201611168041 A CN 201611168041A CN 106783622 A CN106783622 A CN 106783622A
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- 238000000137 annealing Methods 0.000 title description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 208
- 230000007704 transition Effects 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims description 22
- 229910052732 germanium Inorganic materials 0.000 claims description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 239000002210 silicon-based material Substances 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 7
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- 230000037431 insertion Effects 0.000 abstract 1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052986 germanium hydride Inorganic materials 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
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- 230000008901 benefit Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
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- 241000194386 Coelosis Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000406668 Loxodonta cyclotis Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of method of insertion SiGe during there is provided manufacture PMOS device.Multilayer can be formed has the SiGe layer of different Ge contents, to cause to increase to (crowd) intermediate layer Ge contents from (crowd) bottom, and reduces from (crowd) intermediate layer to (crowd) top layer Ge contents.In certain embodiments, the embedded SiGe has the SiGe transition zones on the SiGe Seed Layers of substrate, the SiGe Seed Layers, the SiGe intermediate layers on a SiGe transition zones and the 2nd SiGe transition zones on the SiGe intermediate layers.First SiGe transition zones can have the Ge contents of the top increase from the bottom of a SiGe transition zones toward a SiGe transition zones.2nd SiGe transition zones can have the Ge contents that the top from the bottom of the 2nd SiGe transition zones toward the 2nd SiGe transition zones reduces.
Description
Technical field
The present invention relates to semiconductor technology and device.
Background technology
Since one's early years Texas Instrument Jack doctors Kilby invented integrated circuit from, scientists and engineer
Made numerous inventions and improvement in semiconductor devices and process aspect.Immediate and mid-term, semiconductor dimensions have had
Obvious to reduce, this changes into ever-increasing processing speed and the power consumption for constantly reducing.So far, the development of semiconductor is big
Cause follows Moore's Law, and the quantity that Moore's Law is about being densely integrated transistor in circuit is about every two years double.Now,
Semiconductor technology develops towards below 20nm, and 14nm techniques are being set about by some of them company.One ginseng is only provided here
Examine, a silicon atom is about 0.2nm, it means that the distance between two stand-alone assemblies produced by 20nm techniques are only
About 100 silicon atoms.
Therefore semiconductor devices manufacture becomes more and more challenging, and is advanced towards the physically possible limit.
Hua Li Microtronics A/STMIt is directed to one of leading Semiconductor Manufacturing Company of semiconductor devices and technique research and development.
The conventional device structure based on SiGe (SiGe) technology has been developed to produce field-effect transistor (FET).For example,
Covered by depositing by the SiGe layer of the latent pseudomorphic crystal type strain buried and with strainless silicon (Si) layer, had been developed that for p ditches
The SiGe technologies of road metal-oxide semiconductor (MOS) (PMOS) transistor.This silicon deck portion is oxidized to form gate-dielectric.
Due to the skew of valence band, hole can be limited to SiGe raceway grooves.In this design, if SiGe film thickness be made it is very thin if can
To avoid the dislocation in SiGe film.The manufacture of this device and complementary metal oxide semiconductors (CMOS) (CMOS) place of state of the art
Reason is mutually compatible.
The content of the invention
The brief overview of one or more aspects given below is providing to the basic comprehension in terms of these.This general introduction is not
The extensive overview of all aspects for contemplating, and it is also non-to be both not intended to identify the key or decisive key element of all aspects
Attempt to define the scope in terms of any or all.Its unique purpose is to provide the one of one or more aspects in simplified form
A little concepts think the sequence of more detailed description given later.
According to an aspect of the present invention, there is provided one kind is for forming p-channel metal-oxide semiconductor (MOS) (PMOS) device
Method, the method includes：Substrate is formed, the substrate includes silicon materials；The substrate is etched to form chamber；And sunk in the chamber
Product SiGe with the SiGe Seed Layers on the surface for forming the substrate, the SiGe transition zones on the SiGe Seed Layers, should
The 2nd SiGe transition zones on SiGe intermediate layers and the SiGe intermediate layers on first SiGe transition zones, wherein this
The germanium Ge that one SiGe transition zones have the top increase from the bottom of a SiGe transition zones to a SiGe transition zones contains
Amount, the wherein Ge contents of the bottom of a SiGe transition zones are identical or higher with the Ge contents in the SiGe Seed Layers；Should
SiGe intermediate layers have the Ge content same or higher with the Ge contents at the top of a SiGe transition zones；And this second
SiGe transition zones have the Ge contents that the top from the bottom of the 2nd SiGe transition zones to the 2nd SiGe transition zones reduces, its
In the 2nd SiGe transition zones bottom Ge contents it is identical or lower with the Ge contents in the SiGe intermediate layers.
According to another aspect of the present invention, there is provided a kind of p-channel metal-oxide semiconductor (MOS) (PMOS) device, including：
Substrate, the substrate includes silicon materials；It is formed at the HKMG gate stacks of the substrate；And positioned at the HKMG gate stacks
The embedded SiGe region of opposite sides, SiGe Seed Layers on the surface of each silicon Germanium regions including the substrate, should
In SiGe intermediate layers on a SiGe transition zones, a SiGe transition zones and the SiGe on SiGe Seed Layers
The 2nd SiGe transition zones on interbed, wherein a SiGe transition zones have from the bottom of a SiGe transition zones to this
The germanium Ge contents of the top increase of the first SiGe transition zones, wherein the Ge contents of the bottom of a SiGe transition zones and the SiGe
Ge contents in Seed Layer are identical or higher；The SiGe intermediate layers have the Ge contents with the top of a SiGe transition zones
Same or higher Ge contents；And the 2nd SiGe transition zones have from the bottom of the 2nd SiGe transition zones to this second
The Ge contents that the top of SiGe transition zones reduces, wherein the Ge contents of the bottom of the 2nd SiGe transition zones and the SiGe intermediate layers
In Ge contents it is identical or lower.
Brief description of the drawings
Figure 1A explanations may include in whole substrate deposited hard mask according to the embedded SiGe techniques of present disclosure.
Figure 1B explanations may include after the hard mask is formed in PMOS according to the embedded SiGe techniques of present disclosure
Every side on form Σ shapes chambers.
Fig. 1 C are explained can grow SiGe kinds after chamber is formed according to the embedded SiGe techniques of present disclosure in chamber
Sublayer 114.
Fig. 1 D are explained can form First Transition SiGe layer in the technique after the formation of SiGe Seed Layers.
Fig. 1 E are explained can be grown according to the embedded SiGe techniques of present disclosure after SiGe transition zones formation
SiGe intermediate layers.
Fig. 1 F are explained can be formed in the embedded SiGe techniques according to present disclosure after interbed is formed in sige
Second transitional SiGe layer.
Fig. 1 G are explained and can formed on the 2nd SiGe transition zones in the embedded SiGe techniques according to present disclosure
Cap rock.
With reference to the following drawings, further understanding to the nature and advantages of each embodiment is capable of achieving.In the accompanying drawings, it is similar to
Component or feature can have identical reference.Additionally, each component of same type can by reference followed by
Dash and the pair made a distinction between similar assembly mark to distinguish.If in the description using only the first accompanying drawing mark
Note, then description is applied to any one similar assembly with identical first reference but regardless of secondary reference.
Specific embodiment
Present disclosure is related to the manufacture of k/ metal gates (HKMG) lamination high for semiconductor, more particularly to reduction should
O after the formation of HKMG laminations2To the diffusion in IL.
Be given it is following description with enable those skilled in the art implement and using the present invention and be incorporated into specifically
In application background.Various modifications and the various uses in different application will be readily apparent for those skilled in the art
, and general principle defined herein is applicable to the embodiment of relative broad range.Thus, the present invention is not limited to herein
The embodiment for being given, but the broadest scope consistent with principle disclosed herein and novel features should be awarded.
In the following detailed description, many specific details are elaborated to provide to more thorough understanding of the invention.However, right
In it should be apparent to those skilled in the art that practice of the invention can need not be confined to these details.In other words, it is known
Structure and device show in form of a block diagram without displaying the details of, to avoid the fuzzy present invention.
Please reader note with this specification simultaneously submit to and to public inspection this specification open All Files and text
Offer, and the content of all such files and document is incorporated herein in way of reference.Unless otherwise directly explanation, otherwise this explanation
All features disclosed in book (including any appended claims, summary and accompanying drawing) all can be by identical, equivalent for reaching
Or the alternative feature of similar purpose is replaced.Therefore, unless expressly stated otherwise, each otherwise disclosed feature is only
One group of equivalent or similar characteristics example.
And, it is not known in claim and represents for performing the device of specific function or for performing specific function
The random component of step is all understood not to such as the device or step clause of defined in the 6th section of the 112nd chapters and sections of 35USC.It is special
Not, the step of " ... " or " ... the action of " is used to be not offered as being related to the chapters of 35USC the 112nd the in the claim herein
6 sections of regulation.
Note, it is mark left, right, front and rear, top, bottom, positive and negative, clockwise and anticlockwise only in the case where using
It is in order at what convenient purpose was used, and does not imply that any specific fixed-direction.In fact, they be used to reflect right
Relative position and/or direction between the various pieces of elephant.
In the embedded SiGe techniques of manufacture PMOS device, the shape typically in the regions and source/drain of PMOS device
Coelosis.It is general by more dry etch process, be followed by wet etching process and realize the formation in chamber.First dry etching is walked
Suddenly it is that the etching of first time anisotropic dry penetrates deposited hard mask layer (for example, silicon nitride) to start for etching
The etching of substrate (for example, silicon) lumen, is followed by isotropism dry method lateral etches (dry method lateral etches) to expand (including horizontal stroke
To towards MOS transistor raceway groove) chamber, then the etching of the second anisotropic dry is followed by define the bottom wall in chamber.
Figure 1A -1G explain the technological process for adding embedded SiGe in PMOS according to present disclosure.As shown in Figure 1A,
The technique may include the deposited hard mask 104 on whole substrate 102.In various implementations, hard mask 104 can according to comprising
The application of the device of PMOS 100 is formed to a thickness by SiN.As illustrated, hard mask 104 can be deposited on workfunction metal 108
On such as titanium nitride (TiN), workfunction metal 108 may be provided on the k dielectric layer high 110 on substrate 102.Such as this area
What technical staff will be understood that, the structure shown in Fig. 1 is the HKMG laminations of grid-first, its generally may include it is as shown in Figure 1 between
Parting 106a and 106b.Substrate 102 can be the silicon materials commonly used in such as semi-conductor industry, such as relatively pure silicon and
It is mixed with the silicon of the other elements such as germanium, carbon.Alternatively, the semi-conducting material can be germanium, GaAs etc..The semiconductor material
Material may be provided in block semiconductor substrate, or may be provided on SOI (SOI) substrate, and SOI substrate includes support
The silicon material layer on insulator layer and the insulator layer in substrate, the support substrate.Additionally, substrate 102 can be insulation
Silicon (SOI) on body.In some instances, substrate 102 may include doped epitaxial (epi) layer.In other examples, substrate 102 can
Including multilayer compound semiconductor structure.
In various embodiments, substrate 102 may depend on design requirement including various doped regions (for example, p-type trap or n
Type trap).These doped regions can be doped with p-type dopant, such as boron or BF2, and/or n-type dopant, such as phosphorus or arsenic.
These doped regions can be formed directly into substrate with p-well structure, with N well structures, with Dual Well Structure or using bulge-structure
On 102.The Semiconductor substrate 102 may also include various active regions, such as be configured to N-type metal-oxide semiconductor (MOS) crystal
The region of tube device (referred to as NMOS) and the area for being configured to P-type mos transistor device (referred to as PMOS)
Domain.For example, substrate 102 can have the doped region and epitaxial layer formed for limiting source region and drain region.
Figure 1B explanations according to the embedded SiGe techniques of present disclosure may include the hard mask 100 formed after
Σ shapes chamber 112a-b is formed on every side of PMOS 100.In some implementations, chamber 112a-b can be by the PMOS in substrate 102
Every side of 100 gate stacks carries out wet etching to be formed using tetramethylammonium hydroxide (TMAH).Although other shapes are also
It is possible, but Σ shapes chamber allow very close to the degree of approach and the thus maximum stress in transistor channel region inside.With
There is crystal orientation selectivity, the such as etchant including TMAH to backing material in the Wet-etching agent of crystallographic etch, this can by with
In the etching substrate since the U-shaped recess that more dry etching process is provided.In wet method crystallographic etch technical process,<111
>The etch-rate of crystal orientation is less than such as<100>Deng the etch-rate of other crystal orientation.As a result, U-shaped recess is changed into diamond recess.
As illustrated, after chamber 112a-b is formed, SiGe 113 can be grown in the 112a-b of chamber.In some implementations,
For example by low-pressure chemical vapor deposition (LPCVD) technique as the deep source/drain region for PMOS 100 original position
The boron doping deposition of classification, grows SiGe 113 in the 112a-b of chamber.Original position doping can be used to obtain high and uniform doping
Level, which in turn reduces dead resistance and contact resistance, thus allows driving current higher.And, by male extension
Between adulterate the regions and source/drain of PMOS, special source/drain injection can be cancelled, thereby saving for mask and injection
Process costs, reduce circulation time and reduce the Stress Release from implant damage.Additionally, boron dope agent is by outer
Prolong activation, thus without additional annealing.Slight undue growth can help to be formed firmer encapsulation and for follow-up
Encroach on the surplus of the cleaning procedure of the silicon area of active opening.The undue growth is additionally provided for forming firm autoregistration silication
The extra margin of thing such as nickle silicide (NiSi), and with preferably contact resistance.
In the embedded SiGe technical process according to present disclosure, the SiGe 114 grown in the 112a-b of chamber is can control
The concentration of middle Ge is with the compression stress in the channel region for increasing PMOS device improving device performance.However, it has been viewed that
When the concentration of Ge between substrate 102 and SiGe layer increases, the lattice mismatch between this two-layer can also increase.This can cause substrate
Interface dislocation and SiGe layer between, and thus reduce PMOS device performance.
Further, since above-mentioned SiGe epitaxial growths crystal orientation selectivity (<100>On SiGe growths it is most fast,<110>On
SiGe growth regulations two it is fast and<111>On SiGe growth it is most slow), when SRAM regions SiGe epitaxial layers be higher than substrate plane when,
Can all be formed in the both sides of epitaxial layer<111>Crystal face.However,<111>Crystal face can negatively influence the growth of follow-up cap rock so as to
So that in SRAM regions the cap rock of SiGe may grow it is uneven (for example, cap rock exists<111>On crystal growth may be not enough to
With sufficient thickness, or not grow).And, the SiGe domain with Ge content high may not be with epitaxial layer
Metal nickel reactant or insufficient reaction are forming NiSi or NiGeSi.This can cause contact poor between follow-up CT and SiGe layer
So as to cause leakage, resistance increase, resistance control difficulty increase, and/or any other problem.
In order to solve the above problems, the embedded SiGe techniques according to present disclosure propose a kind of new method,
The Ge contents in the source electrode and drain region of embedded SiGe can be increased under this method.Under this new method, can eliminate or drop
Dislocation between low substrate and embedded SiGe.In addition, under this new method, can also improve above-mentioned cap rock content to help NiSi
Growth.
According to the one side of present disclosure, as the embedded SiGe in the 112a-b of chamber, can form multilayer has different Ge
The SiGe layer of content, to cause to increase toward (crowd) intermediate layer Ge contents from (crowd) bottom, and pushes up from (crowd) intermediate layer toward (crowd)
Layer Ge content reductions.In certain embodiments, one or more of SiGe can be grown first on the bottom of chamber 112a-b and side wall
Seed Layer.Then one or more layers germanium can be grown in (a little) the SiGe Seed Layers, to form one or more SiGe mistakes
Cross layer.(a little) the first SiGe transition zones can have past (a little) the first SiGe mistakes in bottom from (a little) the first SiGe transition zones
Cross the Ge contents of the top increase of layer.Still in these embodiments, one can be formed on (a little) the first SiGe transition zones
Individual or multiple SiGe intermediate layers with high Ge content.Being somebody's turn to do (a little) SiGe intermediate layers can have equal to or higher than a SiGe transition
The Ge contents of the most high Ge content in layer.Finally, in these embodiments, one can be grown on (a little) the SiGe intermediate layers
Or multiple second transitional SiGe layers.Should (a little) the 2nd SiGe transition zones can be with from the bottom of those transition zones toward those transition zones
Top reduce Ge contents.Cap rock finally can be formed on (a little) the 2nd SiGe transition zones.
The additional aspect and other features of present disclosure will state in the following description, and common in this area
Technical staff in part will become it is clear that or can know from the implementation of present disclosure after analyzing herein below.This
The advantage of disclosure can be realized and obtained especially as pointed by the following claims.
Fig. 1 C-F are explained and are grown embedded SiGe step by step in the embedded SiGe techniques according to present disclosure.They
To be described with reference to Figure 1A -1B.Fig. 1 C explain the technique can grow SiGe seeds after chamber 112a-b formation in the 112a-b of chamber
Ge contents in layer 114, and SiGe Seed Layers 114 can be between 1%-28%.In some implementations, SiGe Seed Layers 114
Thickness can be between 100-300 angstroms.Fig. 1 D are explained can form the first mistake in the technique after the formation of SiGe Seed Layers 114
Cross SiGe layer 116.The content of Ge can be between 20%-50% in first SiGe transition zones 116.As illustrated, a SiGe
Ge contents in transition zone 116 can be from the bottom 116b of a SiGe transition zones to the top 116a of a SiGe transition zones gradually
Increase.For example, near the 116b of bottom, Ge contents are about 30%, and near the 116a of top, Ge contents are about 50%.
In some implementations, First Transition layer 116 bottom 116b Ge contents can it is identical with the Ge contents in SiGe Seed Layers 114 or
Substantially it is close.For example, SiGe Seed Layers 114 and bottom 116b can have about 20% Ge contents.In some implementations, first
The thickness of SiGe transition zones 116 can be between 30-500 angstroms.
Fig. 1 E explain the technique can grow SiGe intermediate layers 118 after the formation of a SiGe transition zones 116.In the middle of SiGe
Ge contents in layer 118 can be between 30%-50%.Ge contents in SiGe intermediate layers 118 can be with a SiGe transition zones
Ge contents in 116 top 116a are identical or substantially close.For example, near the 116a of top, a SiGe transition zones can have
There is 40% Ge, SiGe intermediate layers 118 then can also have about 40% Ge contents.In some implementations, SiGe intermediate layers 118
Thickness can be between 100-800 angstroms.In some implementations, the top in SiGe intermediate layers 118 can be deposited in the 112a-b of chamber
It is to maintain an equal level or remain basically stable with the surface of substrate 102.However, this is not restricted.In some other realizations, in SiGe
The top of interbed 118 can be deposited as the surface below or above substrate 102 in the 112a-b of chamber.
Fig. 1 F are explained can form the second transitional SiGe layer 120 by interbed 118 after being formed in sige in this process.Second
The content of Ge can be between 0-50% in SiGe transition zones 120.As illustrated, the Ge contents in the 2nd SiGe transition zones 120
Can gradually be reduced to the top 120a of the 2nd SiGe transition zones from the bottom 120b of the 2nd SiGe transition zones.For example, in bottom
Near 120b, Ge contents are about 50%, and near the 120a of top, Ge contents are about 0%.In some implementations, second
Transition zone 120 can be identical with the Ge contents in SiGe intermediate layers 118 or substantially close in the Ge contents of bottom 120b.For example,
SiGe intermediate layers 118 can have 50% Ge contents.In some implementations, the thickness of the 2nd SiGe transition zones can be between 100-
Between 300 angstroms.
In some implementations, the embedded SiGe as shown in Fig. 1 C-1F can be grown by any suitable technique, note
Enter chemical vapor deposition (CVD), ald (ALD), low pressure chemical vapor deposition (LPCVD) or any suitable life known in the art
Other techniques of the embedded SiGe of length.The gas that can be used to grow the embedded SiGe as shown in Fig. 1 C-1F may include SiH4、
SiH2Cl2、HCL、H2、GeH4、B2H6And/or any other gas.When using H2When, can be by H2Flow control in 1000sccm
Between~60000sccm, and by the control of gaseous gas flow between 0.1sccm~1200sccm.When using GeH4And
SiH4Or SiH2Cl2When, GeH4And SiH4Or SiH2Cl2Flow-rate ratio can be controlled in 1:0.01 to 1:100.When using GeH4And HCl
When, their flow-rate ratio can be controlled in 1:0.05 to 1:50.In various embodiments, reaction temperature can be controlled in 500~1000
DEG C, and reaction chamber pressure controllable system is in 1~800 support.
Fig. 1 G are explained and cap rock 122 can be formed on the 2nd SiGe transition zones 120.The thickness of cap rock 122 can be controlled in 10
To between 300 angstroms.The content of cap rock can include Ge in certain embodiments, or can not include in some other embodiments
Ge.In some implementations, each of layer 116,118,120 and 122 or multiple can include the SiGe doping in situ of B, and B's is dense
Degree is less than 2x1021cm-3。
As what is explained through the various pieces of the application, embodiments of the invention can be carried compared to prior art and method
For many advantages.It is to be appreciated that various embodiments of the present invention are mutually compatible with existing system and technique.For example, reality of the invention
The forming cavity described by example is applied existing weaponry and equipment can be used to manufacture.Forming cavity can readily be used system according to an embodiment of the invention
Make various types of devices such as CMOS, PMOS, NMOS.
Although being above the comprehensive description to specific embodiment, various modifications, replacing structure and equivalent also can be used
Scheme.In addition to the foregoing, also in the presence of other embodiments.Therefore, foregoing description and explanation is not construed as limit
The scope of the present invention that system is defined by the following claims.
Claims (19)
1. one kind is used for the method for forming p-channel metal-oxide semiconductor (MOS) (PMOS) device, and methods described includes：
Substrate is formed, the substrate includes silicon materials；
The substrate is etched to form chamber；And
SiGe is deposited in the chamber with the SiGe Seed Layers on the surface for forming the substrate, on the SiGe Seed Layers
A SiGe transition zones, on the SiGe intermediate layers on a SiGe transition zones and the SiGe intermediate layers
2nd SiGe transition zones, wherein
The first SiGe transition zones have from the bottom of a SiGe transition zones to the top of a SiGe transition zones
The germanium Ge contents of portion's increase, wherein the Ge contents of the bottom of the first SiGe transition zones contain with the Ge in the SiGe Seed Layers
Amount is identical or higher；
The SiGe intermediate layers have the Ge content same or higher with the Ge contents at the top of a SiGe transition zones；With
And
The 2nd SiGe transition zones have from the bottom of the 2nd SiGe transition zones to the top of the 2nd SiGe transition zones
The Ge contents that portion reduces, wherein the Ge contents in the Ge contents of the bottom of the second SiGe transition zones and the SiGe intermediate layers
It is identical or lower.
2. the method for claim 1, it is characterised in that in a SiGe transition zones percentage of Ge contents between
Between 20% to 50%.
3. the method for claim 1, it is characterised in that the percentage of Ge contents is between 30% in the SiGe intermediate layers
To between 50%.
4. the method for claim 1, it is characterised in that in the 2nd SiGe transition zones percentage of Ge contents between
Between 0% to 50%.
5. the method for claim 1, it is characterised in that the Ge contents at the top of the 2nd SiGe transition zones are 0.
6. the method for claim 1, it is characterised in that be additionally included in and lid is formed on the 2nd SiGe transition zones
Layer.
7. the method for claim 1, it is characterised in that a SiGe transition zones are characterized as being thickness between 30 angstroms
To between 500 angstroms.
8. the method for claim 1, it is characterised in that the SiGe intermediate layers are characterized as being thickness between 100 angstroms extremely
Between 800 angstroms.
9. the method for claim 1, it is characterised in that the 2nd SiGe transition zones are characterized as being thickness between 100
Angstrom between 300 angstroms.
10. the method for claim 1, it is characterised in that the top in the SiGe intermediate layers and the surface of the substrate
Maintain an equal level or remain basically stable.
A kind of 11. p-channel metal-oxide semiconductor (MOS) (PMOS) devices, including：
Substrate, the substrate includes silicon materials；
It is formed at the HKMG gate stacks of the substrate；And
Positioned at the embedded SiGe region of the opposite sides of the HKMG gate stacks, each silicon Germanium regions include the lining
A SiGe transition zones, a SiGe transition on SiGe Seed Layers, the SiGe Seed Layers on the surface at bottom
SiGe intermediate layers on layer and the 2nd SiGe transition zones on the SiGe intermediate layers, wherein
The first SiGe transition zones have from the bottom of a SiGe transition zones to the top of a SiGe transition zones
The germanium Ge contents of portion's increase, wherein the Ge contents of the bottom of the first SiGe transition zones contain with the Ge in the SiGe Seed Layers
Amount is identical or higher；
The SiGe intermediate layers have the Ge content same or higher with the Ge contents at the top of a SiGe transition zones；With
And
The 2nd SiGe transition zones have from the bottom of the 2nd SiGe transition zones to the top of the 2nd SiGe transition zones
The Ge contents that portion reduces, wherein the Ge contents in the Ge contents of the bottom of the second SiGe transition zones and the SiGe intermediate layers
It is identical or lower.
12. PMOS devices as claimed in claim 11, it is characterised in that the percentage of Ge contents in a SiGe transition zones
Than between 20% to 50%.
13. PMOS devices as claimed in claim 11, it is characterised in that the percentage of Ge contents is situated between in the SiGe intermediate layers
Between 30% to 50%.
14. PMOS devices as claimed in claim 11, it is characterised in that the percentage of Ge contents in the 2nd SiGe transition zones
Than between 0% to 50%.
15. PMOS devices as claimed in claim 11, it is characterised in that the Ge contents at the top of the 2nd SiGe transition zones
It is 0.
16. PMOS devices as claimed in claim 11, it is characterised in that a SiGe transition zones are characterized as being thickness Jie
Between 30 angstroms to 500 angstroms.
17. PMOS devices as claimed in claim 11, it is characterised in that the SiGe intermediate layers be characterized as being thickness between
Between 100 angstroms to 800 angstroms.
18. PMOS devices as claimed in claim 11, it is characterised in that the 2nd SiGe transition zones are characterized as being thickness Jie
Between 100 angstroms to 300 angstroms.
19. PMOS devices as claimed in claim 11, it is characterised in that the top in the SiGe intermediate layers and the substrate
Surface maintains an equal level or remains basically stable.
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| CN110400844A (en) * | 2019-07-25 | 2019-11-01 | 上海华力集成电路制造有限公司 | Germanium silicon epitaxial layer, its forming method and a PMOS device |
| CN110444473A (en) * | 2019-08-29 | 2019-11-12 | 上海华力集成电路制造有限公司 | The manufacturing method of embedded SiGe device and embedded SiGe device structure |
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