CN103187269B - The formation method of transistor - Google Patents
The formation method of transistor Download PDFInfo
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- CN103187269B CN103187269B CN201110457018.0A CN201110457018A CN103187269B CN 103187269 B CN103187269 B CN 103187269B CN 201110457018 A CN201110457018 A CN 201110457018A CN 103187269 B CN103187269 B CN 103187269B
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Abstract
A formation method for transistor, comprising: provide substrate, and described substrate comprises Semiconductor substrate, is positioned at the grid structure of described semiconductor substrate surface; Etch semiconductor substrates, forms opening in the Semiconductor substrate of grid structure both sides; Annealing in process is carried out to described opening, makes the bottom of described opening and sidewall become round and smooth; Adopt wet-etching technology, continue the described opening after etching annealing in process, described opening is extended to channel region; After wet etching, fill full described opening and form stress liner layer.During formation stress liner layer, growth rate is fast, and the quality of the stress liner layer of formation is good, and the stress of transistor channel region is large, and meet process requirements, channel region carrier mobility is high, and the performance of transistor is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of transistor.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach higher arithmetic speed, larger memory data output and more function, and semiconductor device is towards higher component density, higher integrated level future development.Therefore, the grid of complementary metal oxide semiconductors (CMOS) (ComplementaryMetalOxideSemiconductor, CMOS) transistor becomes more and more thinner and length becomes shorter than ever.But the change in size of grid can affect the electric property of semiconductor device, at present, performance of semiconductor device is improved mainly through controlling carrier mobility.A key element of this technology controls the stress in transistor channel.Such as suitable proof stress, improves charge carrier (electronics in n-channel transistor, the hole in p-channel transistor) mobility, just can improve drive current.Thus stress greatly can improve the performance of transistor.
Because silicon, germanium have identical lattice structure, i.e. " diamond " structure, at room temperature, the lattice constant of germanium is greater than the lattice constant of silicon, so in the source of PMOS transistor, drain region formed SiGe (SiGe), the compression that between silicon and germanium silicon, lattice mismatch is formed can be introduced, improve compression further, improve the performance of PMOS transistor.Correspondingly, in the source of nmos pass transistor, drain region forms carbon silicon (CSi) and can introduce the tension stress that lattice mismatch between silicon and carbon silicon formed, and improves tension stress further, improves the performance of nmos pass transistor.
In prior art, the formation method with the transistor of stress is:
Please refer to Fig. 1, Semiconductor substrate 100 is provided; Shallow channel isolation area 103 is formed in described Semiconductor substrate 100; Formation is positioned at the surperficial gate insulation layer 105 of described Semiconductor substrate 100; Form the gate electrode layer 107 covering described gate insulation layer 105; Formed on described Semiconductor substrate 100 surface and be positioned at described gate insulation layer 105, gate electrode layer 107 both sides and the side wall 109 be in contact with it;
Please refer to Fig. 2, is that mask forms opening 111 in described Semiconductor substrate 100 with described side wall 109;
Please refer to Fig. 3, in described opening, fill full SiGe, form source/drain region 113.
But the stress that the method that prior art forms germanium silicon at the source and drain areas of transistor is formed is limited, and the raising of the carrier mobility of channel region is less, the performance of transistor improves limited.
Manyly see that publication number is the application documents of " CN101789447A " about transistor and forming method thereof.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, and the carrier mobility of channel region is high, and the performance of transistor is good.
For solving the problem, The embodiment provides a kind of formation method of transistor, comprising:
There is provided substrate, described substrate comprises Semiconductor substrate, is positioned at the grid structure of described semiconductor substrate surface;
Etch semiconductor substrates, forms opening in the Semiconductor substrate of grid structure both sides;
Annealing in process is carried out to described opening, makes the bottom of described opening and sidewall become round and smooth;
Adopt wet-etching technology, continue the described opening after etching annealing in process, described opening is extended to channel region;
After wet etching, fill full described opening and form stress liner layer.
Alternatively, the process parameters range of described annealing in process is: annealing temperature is 650-1000 DEG C, and the pressure of annealing chamber is 1Torr-600Torr, and anneal duration is 30S-150S.
Alternatively, also comprise: when annealing in process, pass into inert gas or hydrogen to anneal chamber indoor.
Alternatively, the flow of described inert gas or hydrogen is 20-50slm.
Alternatively, before annealing in process, the degree of depth of described opening is 3-30nm.
Alternatively, after wet etching, the shape of described opening is sigma shape.
Alternatively, after wet etching, the degree of depth of described opening is 40-100nm, and the distance of the drift angle distance semiconductor substrate surface of described opening near channel region is 5-20nm.
Alternatively, the material of described stress liner layer is SiGe or SiC.
Alternatively, the formation process of described stress liner layer is selective epitaxial depositing operation.
Alternatively, the parameter area of described selective epitaxial depositing operation is: temperature is 550 DEG C-800 DEG C, and pressure is 5-20Torr, silicon source gas SiH
2cl
2, SiH
4or Si
2h
6flow be the flow of 30-500sccm, HCl be 50-500sccm, H
2flow be 5slm-50slm, germanium source gas GeH
4flow be 5sccm-500sccm, the flow of carbon doping gas is 5-500sccm.
Compared with prior art, embodiments of the invention have the following advantages:
Annealing in process has been carried out to opening, silicon during annealing in process in Semiconductor substrate there occurs migration, the bottom of described opening and sidewall become round and smooth, the bottom of described opening and the crystal orientation of sidewall there occurs change, and during wet-etching technology, etch rate is relevant with the crystal orientation of sidewall with the bottom of opening, longitudinal etch rate is greater than along the etch rate in direction, channel region during wet-etching technology, or both are more or less the same, subsequent wet etching formed extended distance Semiconductor substrate bottom distant, not easily produce leakage current at base semiconductor, and there is not wedge angle in open bottom, growth rate when forming stress liner layer is fast, the quality of the stress liner layer formed is good, and the stress of transistor channel region is large, meet process requirements, channel region carrier mobility is high, the performance of transistor is good.
Accompanying drawing explanation
Fig. 1-Fig. 3 is the cross-sectional view of the forming process of the transistor of prior art;
Fig. 4 is the schematic flow sheet of the formation method of transistor in embodiments of the invention;
Fig. 5-Fig. 9 is the cross-sectional view of the forming process of transistor in embodiments of the invention.
Embodiment
As described in background, the mobility of the channel region charge carrier of the transistor of prior art is low, the poor performance of transistor.
Through research, inventor finds, the distance dependent of the mobility of channel region charge carrier and stress liner layer distance channel region, and the distance of stress liner leafing channel region is nearer, the stress that channel region produces is larger, is more conducive to being formed the transistor that the mobility of charge carrier is high.After opening 111 (as shown in Figure 2), wet-etching technology can be adopted to etch described opening 111, the sidewall of opening 111 is caved in towards the direction of channel region, recharge germanium silicon or carbon silicon formation stress liner layer.
After further research, inventor finds, when adopting wet-etching technology to etch above-mentioned opening 111, because opening 111 sidewall is different with the crystal orientation of bottom, the sidewall 1nm of the every lateral etching opening 111 of wet-etching technology, the degree of depth of the bottom of longitudinal etching opening 111 then reaches 3-4nm, when the opening 111 that wet etching is formed meets process requirements from the distance of channel region, the degree of depth of opening 111 is very likely excessive, cause the stress liner layer of follow-up formation bottom Semiconductor substrate, produce larger stress, produce electric leakage, and the stress of channel region is less, and, due to the etching speed of longitudinal direction during wet-etching technology, easily wedge angle is formed bottom opening 111, described wedge angle can affect speed during follow-up formation stress liner layer, and the stress liner layer formed is second-rate, easily there is defect in inside.
Further, inventor finds, during wet-etching technology, etch rate is relevant with the crystal orientation of semiconductor substrate surface, when the bottom of opening and sidewall become round and smooth after, the crystal orientation on surface creates change thereupon, longitudinal etch rate is greater than towards the etch rate in direction, channel region during wet-etching technology, or both are more or less the same, the degree of depth of the opening longitudinal direction formed after making wet-etching technology is less, and bottom does not exist wedge angle.Leakage current is there is not bottom the Semiconductor substrate of therefore follow-up formation, and fast growth during follow-up formation stress liner layer, the quality of the stress liner layer of formation is good.
In order to make those skilled in the art better understand the present invention, below in conjunction with accompanying drawing and specific embodiment, the present invention is described in detail.
Please refer to Fig. 4, the formation method of the transistor of the embodiment of the present invention, comprising:
Step S201, provides substrate, and described substrate comprises Semiconductor substrate, is positioned at the grid structure of described semiconductor substrate surface;
Step S203, etch semiconductor substrates, forms opening in the Semiconductor substrate of grid structure both sides;
Step S205, carries out annealing in process to described opening, makes the bottom of described opening and sidewall become round and smooth;
Step S207, adopts wet-etching technology, continues the described opening after etching annealing in process, described opening is extended to channel region;
Step S209, after wet etching, fills full described opening and forms stress liner layer.
Concrete, please refer to Fig. 5-Fig. 9, Fig. 5-Fig. 9 shows the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
Please refer to Fig. 5, provide substrate, described substrate comprises Semiconductor substrate 300, is positioned at the grid structure (sign) on described Semiconductor substrate 300 surface.
The material of described Semiconductor substrate 300 is monocrystalline silicon, is formed with fleet plough groove isolation structure 303, for isolated transistor in described Semiconductor substrate 300.In an embodiment of the present invention, the crystal orientation on described Semiconductor substrate 300 surface is <110> or <100>.
Described grid structure comprises the gate dielectric layer 305 being positioned at described Semiconductor substrate 300 surface, the gate electrode layer 307 being positioned at described gate dielectric layer 305 surface and is positioned at described gate dielectric layer 305 and gate electrode layer 307 both sides and the side wall 309 on Semiconductor substrate 300 surface be in contact with it.
In an embodiment of the present invention, the forming step of described grid structure is: adopt depositing operation to form gate dielectric layer 305 on described Semiconductor substrate 300 surface; Depositing operation is adopted to form gate electrode layer 307 on described gate dielectric layer 305 surface; Deposition, etching technics is adopted to form side wall 309 on Semiconductor substrate 300 surface of described gate dielectric layer 305 and gate electrode layer 307 both sides.
Wherein, the material of described gate dielectric layer 305 is silicon dioxide or high K dielectric, and the material of described gate electrode layer 307 is polysilicon or metal, and the material of described side wall 309 is silicon dioxide.
It should be noted that, described gate electrode layer 307 surface is also formed with mask layer (not shown), not damaged for grill-protected electrode layer 307 in subsequent technique.
Please refer to Fig. 6, etch described Semiconductor substrate 300, in the Semiconductor substrate 300 of grid structure both sides, form opening 311.
Described opening 311 is for providing platform for the stress liner layer of follow-up formation near channel region.The degree of depth of described opening 311 is 3-30nm.The formation process of described opening 311 is dry etch process, and the etching gas that described dry etch process adopts comprises HBr or Cl
2deng.In described dry etch process process, the flow adopting HBr is 200-800sccm, Cl
2flow be 20-100sccm, the pressure of etching cavity is 2-200 millitorr (mTorr), and etch period is 15-60 second (S).
It should be noted that, in embodiments of the invention, also pass into the inert gas that flow is 50-1000sccm during dry etch process, such as He.
Please refer to Fig. 7, annealing in process is carried out to described opening 311, make the bottom of described opening 311 and sidewall become round and smooth.
Inventor finds, due to the sidewall of opening 311 that formed after dry etching and bottom comparatively smooth, if directly adopt wet-etching technology to etch above-mentioned opening 311, because opening 311 sidewall is different with the crystal orientation of bottom, the sidewall 1nm of the every lateral etching opening 311 of wet-etching technology, the degree of depth of the bottom of longitudinal etching opening 311 then reaches 3-4nm, when the opening 311 that wet etching is formed meets process requirements from the distance of channel region, the degree of depth of opening 311 is very likely excessive, the stress liner layer of follow-up formation is caused to produce larger stress bottom Semiconductor substrate 300, produce electric leakage, and the stress of channel region is less, and, because during wet-etching technology, the etching speed of longitudinal direction is large, easily wedge angle is formed bottom opening 311, described wedge angle can affect speed during follow-up formation stress liner layer, and the stress liner layer formed is second-rate, easily there is defect in inside.
Further, inventor finds, during wet-etching technology, etch rate is relevant with the crystal orientation on Semiconductor substrate 300 surface, and bottom and the round and smooth opening 311 of sidewall are conducive to the opening that follow-up formation extends to channel region.In an embodiment of the present invention, inventor carries out annealing in process to described opening 311, and under high-temperature low-pressure condition, there occurs migration with the silicon atom of sidewall bottom opening 311, bottom and the sidewall of described opening 311 become round and smooth.
In an embodiment of the present invention, the process parameters range of described annealing in process is: annealing temperature is 650-1000 DEG C, and the pressure of annealing chamber is 1Torr-600Torr, and anneal duration is 30S-150S.The bottom of opening 311 formed within the scope of above-mentioned parameter and sidewall comparatively round and smooth, do not possess wedge angle bottom the opening 311 extended to channel region of follow-up formation, when forming stress liner layer, growth rate is fast, and the carrier mobility of the transistor formed is high.
For bottom oxygen when avoiding annealing treating process and opening 311 and the silicon of sidewall to react formation oxide film; in an embodiment of the present invention; during annealing treating process, simultaneously pass into inert gas or hydrogen to anneal chamber indoor, with the bottom of protective opening 311 and sidewall not oxidized.Wherein, the flow of described inert gas or hydrogen is 20-50slm.
Please refer to Fig. 8, adopt wet-etching technology, continue the described opening 311 after etching annealing in process, described opening 311 is extended to channel region.
Described opening 311 after wet etching is for providing platform for follow-up formation stress liner layer.The formation process of described opening 311 is wet-etching technology.Due to the bottom of opening during wet etching and sidewall become round and smooth after, bottom it and the crystal orientation of sidewall creates change thereupon, longitudinal etch rate is greater than towards the etch rate in direction, channel region during wet-etching technology, or both are more or less the same, the opening 311 formed after making wet-etching technology is parallel to the direction on Semiconductor substrate 300 surface more near channel region, the degree of depth of its longitudinal direction is less, and bottom does not exist wedge angle.Leakage current is there is not bottom the Semiconductor substrate 300 of therefore follow-up formation, and fast growth during follow-up formation stress liner layer, the quality of the stress liner layer of formation is good.
In an embodiment of the present invention, the chemical reagent that described wet-etching technology adopts is potassium hydroxide (KOH), ammoniacal liquor (NH
4oH) or tetramethyl aqua ammonia (TMAH), the shape of the opening 311 formed after wet etching is sigma shape.The degree of depth of the opening that described wet etching is formed is 40-100nm, described opening 311 has drift angle near channel region place, the distance of described drift angle distance semiconductor substrate surface is 5-20nm, the opening 311 that wet etching is formed, on the basis of the opening 311 formed before annealing in process, etch the Semiconductor substrate 300 of 10-30nm along direction, channel region, made opening more near channel region, be conducive to the follow-up stress larger in channel region formation.
Please refer to Fig. 9, after wet etching, fill full described opening and form stress liner layer 315.
Described stress liner layer 315, for increasing the compression of channel region or tension stress, to improve the carrier mobility of channel region, improves the performance of transistor.The material of described stress liner layer 315 is SiGe or SiC.The formation process of described stress liner layer 315 is depositing operation or selective epitaxial growth process.In an embodiment of the present invention, the material of described stress liner layer 315 is SiGe, and the formation process of described stress liner layer 315 is selective epitaxial growth process.
When adopting selective epitaxial growth process to form described stress liner layer 315, the reactant of employing comprises: silicon source gas SiH
4, SiH
2cl
2or Si
2h
6, and germanium source gas GeH
4, for the formation of SiGe.In order to avoid stress liner layer 315 is interior or other do not need the place forming SiGe to produce impurity, also HCl is comprised in described reactant, and, in order to avoid the silicon on Semiconductor substrate 300 surface is oxidized, form the performance that oxide film affects transistor, when adopting selective epitaxial growth process to form stress liner layer 315, also pass into hydrogen simultaneously.
In an embodiment of the present invention, the reactant that described selective epitaxial depositing operation adopts is SiH
2cl
2, SiH
4, GeH
4and H
2, its parameter area is: temperature is 550 DEG C-800 DEG C, and pressure is 5-20Torr, silicon source gas SiH
2cl
2, SiH
4or Si
2h
6flow be the flow of 30-500sccm, HCl be 50-500sccm, H
2flow be 5slm-50slm, germanium source gas GeH
4flow be 5sccm-500sccm, the flow of carbon doping gas is 5-500sccm.
It should be noted that, in other embodiments of the invention, if the material of stress liner layer 315 is SiC, the reactant adopted when adopting selective epitaxial growth process to form stress liner layer 315 comprises: SiH
4with dimethylamine silane, HCl and H can also be comprised
2.
After above-mentioned steps completes, completing of the transistor of the embodiment of the present invention.Because the embodiment of the present invention has carried out annealing in process to opening, silicon atom during annealing in process in Semiconductor substrate there occurs migration, the bottom of described opening and sidewall become round and smooth, the bottom of described opening and the crystal orientation of sidewall there occurs change, and during wet-etching technology, etch rate is relevant with the crystal orientation of sidewall with the bottom of opening, longitudinal etch rate is greater than along the etch rate in direction, channel region during wet-etching technology, or both are more or less the same, subsequent wet etching formed extended distance Semiconductor substrate bottom distant, not easily produce leakage current at base semiconductor, and there is not wedge angle in open bottom, growth rate when forming stress liner layer is fast, the quality of the stress liner layer formed is good, and the stress of transistor channel region is large, meet process requirements, channel region carrier mobility is high, the performance of transistor is good.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for transistor, is characterized in that, comprising:
There is provided substrate, described substrate comprises Semiconductor substrate, is positioned at the grid structure of described semiconductor substrate surface;
Etch semiconductor substrates, forms opening in the Semiconductor substrate of grid structure both sides;
Annealing in process is carried out to described opening, makes the bottom of described opening and sidewall become round and smooth;
Adopt wet-etching technology, continue the described opening after etching annealing in process, be greater than longitudinal etch rate towards the etch rate in direction, channel region during opening described in wet etching, the length that the opening that wet etching is formed extends to channel region is greater than the length of longitudinal extension;
After wet etching, fill full described opening and form stress liner layer.
2. the formation method of transistor as claimed in claim 1, it is characterized in that, the process parameters range of described annealing in process is: annealing temperature is 650-1000 DEG C, and the pressure of annealing chamber is 1Torr-600Torr, and anneal duration is 30S-150S.
3. the formation method of transistor as claimed in claim 1, is characterized in that, also comprise: when annealing in process, pass into inert gas or hydrogen to anneal chamber indoor.
4. the formation method of transistor as claimed in claim 3, it is characterized in that, the flow of described inert gas or hydrogen is 20-50slm.
5. the formation method of transistor as claimed in claim 1, it is characterized in that, before annealing in process, the degree of depth of described opening is 3-30nm.
6. the formation method of transistor as claimed in claim 1, it is characterized in that, after wet etching, the shape of described opening is sigma shape.
7. the formation method of transistor as claimed in claim 1, it is characterized in that, after wet etching, the degree of depth of described opening is 40-100nm, and the distance of the drift angle distance semiconductor substrate surface of described opening near channel region is 5-20nm.
8. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described stress liner layer is SiGe or SiC.
9. the formation method of transistor as claimed in claim 1, it is characterized in that, the formation process of described stress liner layer is selective epitaxial depositing operation.
10. the formation method of transistor as claimed in claim 9, it is characterized in that, the parameter area of described selective epitaxial depositing operation is: temperature is 550 DEG C-800 DEG C, and pressure is 5-20Torr, silicon source gas SiH
2cl
2, SiH
4or Si
2h
6flow be the flow of 30-500sccm, HCl be 50-500sccm, H
2flow be 5slm-50slm, germanium source gas GeH
4flow be 5sccm-500sccm, the flow of carbon doping gas is 5-500sccm.
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|---|---|---|---|
| CN201110457018.0A CN103187269B (en) | 2011-12-30 | 2011-12-30 | The formation method of transistor |
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| CN104465486B (en) * | 2013-09-18 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN105097457A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN105448715B (en) * | 2014-06-19 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113281920B (en) * | 2021-05-07 | 2024-08-20 | 三明学院 | First-order electro-optic effect silicon modulator and preparation process thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101454874A (en) * | 2006-06-07 | 2009-06-10 | Asm美国公司 | Selective epitaxial formation of semiconductor films |
| CN101743627A (en) * | 2007-03-30 | 2010-06-16 | 英特尔公司 | Method of forming improved EPI fill on narrow isolation bounded source/drain regions and structure formed thereby |
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| US20080227267A1 (en) * | 2007-03-14 | 2008-09-18 | Theodorus Gerardus Maria Oosterlaken | Stop mechanism for trench reshaping process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101454874A (en) * | 2006-06-07 | 2009-06-10 | Asm美国公司 | Selective epitaxial formation of semiconductor films |
| CN101743627A (en) * | 2007-03-30 | 2010-06-16 | 英特尔公司 | Method of forming improved EPI fill on narrow isolation bounded source/drain regions and structure formed thereby |
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