CN105448715B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN105448715B CN105448715B CN201410276851.9A CN201410276851A CN105448715B CN 105448715 B CN105448715 B CN 105448715B CN 201410276851 A CN201410276851 A CN 201410276851A CN 105448715 B CN105448715 B CN 105448715B
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Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, comprising: provides semiconductor substrate, is formed with gate structure on a semiconductor substrate；Arciform groove is formed in the part that will form source/drain region of semiconductor substrate；The high temperature anneal is executed, the U-shaped groove of arciform groove transition is made；The U-shaped groove formed after the high annealing is etched, to form ∑ shape groove, and low-temperature annealing processing is implemented to ∑ shape groove；Embedded germanium silicon layer is formed in ∑ shape groove.According to the present invention, the homogeneity of the thickness for the embedded germanium silicon layer that the distributing homogeneity and subsequent technique that ∑ shape groove profile can further be promoted are formed, reduce the temperature of selective epitaxial growth germanium silicon, and then the compression that embedded germanium silicon layer applies device channel region is further enhanced, the uniformity that device electrical performance is distributed in wafer can also be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method for forming embedded germanium silicon.
Background technique
With the continuous reduction of dimensions of semiconductor devices, for metal-oxide semiconductor fieldeffect transistor
(MOSFET) for, various stress techniques are generallyd use to increase the electric current by MOS transistor, such as double line of tensions (DSL),
Stress memory technique (SMT), embedded germanium silicon etc..
For PMOS transistor, in order to improve the mobility of carrier in its channel, PMOS transistor will shape
The hot spot widely paid close attention to is had become with the technology of the embedded germanium silicon of epitaxial growth at the part production groove of source/drain region.For
It is scaled due to device size with 45nm with the semiconductor fabrication process of lower node, the length of device channel also phase
It should shorten, therefore, there is correlative study to point out that the part that will form source/drain region in PMOS transistor makes side wall to device channel
The groove of direction indent can effectively shorten the length of device channel, meet the scaled requirement of device size；Meanwhile this
Kind of groove has the characteristics that the larger incision below grid gap wall, as a result, in this groove epitaxial growth embedded germanium
Silicon can generate bigger stress to device channel region.
It includes: as shown in Figure 1A, partly to lead first with dry etching that making, which has the basic step of the groove of These characteristics,
Bowl-shape groove 101 is formed in body substrate 100；As shown in Figure 1B, recycle wet etching in the constituent material of semiconductor substrate 100
Different crystal orientations on etch-rate difference, i.e., the composition material relative to semiconductor substrate 100 that the described wet etching has
The feature that the etch-rate both horizontally and vertically of material is fast, other direction etch-rates are slow, forms in semiconductor substrate 100
Groove 102 of the side wall to device channel direction indent.After the dry etch process terminates, the side of bowl-shape groove 101
The influence of wall and the bombardment of the surface subject plasma of bottom generates distortion of lattice dislocation, and then leads to the wet process implemented in next step
Silicon etching speed in etching process is uneven, causes the inhomogeneities of wafer indent channel profiles, so that device electrical performance
There are greatest differences for distribution in wafer；Meanwhile the surface of the side wall of bowl-shape groove 101 also will receive the dry etching and adopt
Doping pollution caused by oxygen or nitrogen-atoms bombardment in etching gas, above-mentioned phenomenon can make the side of bowl-shape groove 101
The surface appearance of wall is deteriorated.Since the anisotropic wet etching of subsequent implementation is to the surface shape of the side wall of bowl-shape groove 101
Condition is extremely sensitive, i.e., the surface appearance of the side wall of bowl-shape groove 101 is poorer, and the effect of the wet etching is poorer, finally leads
Cause can not be effectively formed groove 102 of the side wall to device channel direction indent.In addition, relatively slow for etch-rate
Crystal orientation for, such as<111>crystal orientation of semiconductor substrate 100, after the wet etch process terminates, the side wall is to device
The groove 102 of part channel direction indent will generate the poor point of physical property on the crystal face of the crystal orientation, these points
Bombardment of the position derived from etching plasma-based.During subsequently epitaxial growing embedded germanium silicon, the germanium silicon growth technological temperature that needs
It is higher, and germanium silicon is affected in the growth of these points, is easy to appear stacking fault defects, and then influence to the embedded of formation
The control of the caliper uniformity of germanium silicon.Finally, each section height for being formed by embedded germanium silicon is deep mixed, whole right
The stress that the channel region of PMOS transistor applies can also weaken.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, comprising: provides semiconductor
Substrate is formed with gate structure on the semiconductor substrate；In the part that will form source/drain region of the semiconductor substrate
It is middle to form arciform groove；The high temperature anneal is executed, the U-shaped groove of arciform groove transition is made；Etch the high annealing
The U-shaped groove formed afterwards to form ∑ shape groove, and implements low-temperature annealing processing to the ∑ shape groove；It is recessed in the ∑ shape
Embedded germanium silicon layer is formed in slot.
Further, the step of forming the arciform groove includes: that first will form source/drain region to the semiconductor substrate
Part carry out dry etching to form groove, then to the groove carry out wet etching.
Further, the dry etching is made of for execution order is interconvertible isotropic etching and anisotropic etching
Two step etching.
Further, it is 600-1200 DEG C that the technological parameter of the high annealing, which includes: temperature, and annealing time is 0-2 hours,
Annealing atmosphere is H2, N2 or Ar, pressure 0-15MPa.
Further, the technological parameter of the low-temperature annealing includes: the temperature that temperature is lower than the high annealing, the high temperature
Difference between the temperature of annealing and the temperature of the low-temperature annealing is 300-700 DEG C, and annealing time is 0-2 hours, gas of annealing
Atmosphere is H2, N2 or Ar, pressure 0-15MPa.
Further, the temperature of the low-temperature annealing is 500-900 DEG C.
Further, before implementing the high annealing and the low-temperature annealing, wet cleaning processes are executed respectively, with respectively
Remove the residue and impurity in the arciform groove and the ∑ shape groove.
Further, the wet etching that is etched to for forming ∑ shape groove, the corrosive liquid of the wet etching are tetramethyl
Ammonia.
Further, implement low temperature selective epitaxial growth technique and form the embedded germanium silicon layer, the temperature of the low temperature
It is 500-850 DEG C.
Further, the gate structure includes the gate dielectric stacked gradually from bottom to top, gate material layers and grid
Hard masking layer
According to the present invention it is possible to further promoted the ∑ shape groove profile distributing homogeneity and formation it is embedded
The homogeneity of the thickness of germanium silicon layer, reduces the temperature of selective epitaxial growth germanium silicon, and then further enhances embedded germanium silicon layer
To the compression that device channel region is applied, the uniformity that device electrical performance is distributed in wafer can also be improved.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A is the signal of the bowl-shape groove formed in substrate during forming embedded germanium silicon using the prior art
Property sectional view；
Figure 1B is the side wall that is formed in substrate during forming embedded germanium silicon using the prior art to device channel
The schematic cross sectional view of the groove of direction indent；
Fig. 2A-Fig. 2 E is the device that obtains respectively the step of successively implementation according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 3 is flow chart the step of successively implementation according to the method for exemplary embodiment of the present.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
The embedded germanium silicon of formation method.Obviously, the technical staff that execution of the invention is not limited to semiconductor field is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or their combination.
[exemplary embodiment]
In the following, forming embedded germanium referring to Fig. 2A-Fig. 2 E and Fig. 3 to describe method according to an exemplary embodiment of the present invention
The detailed step of silicon.
Referring to Fig. 2A-Fig. 2 E, method according to an exemplary embodiment of the present invention is shown and successively implements the step of institute
The schematic cross sectional view of the device obtained respectively.
Firstly, as shown in Figure 2 A, providing semiconductor substrate 200, the constituent material of semiconductor substrate 200, which can use, not to be mixed
The monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), silicon (SSOI), insulator upper layer is laminated on insulator in miscellaneous monocrystalline silicon
Folded SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, at this
In embodiment, the constituent material of semiconductor substrate 200 selects monocrystalline silicon.Be formed in semiconductor substrate 200 isolation structure with
And various trap (well) structures, to put it more simply, being omitted in diagram.As an example, isolation structure is shallow trench isolation (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure.
Be formed with gate structure 201 on semiconductor substrate 200, as an example, gate structure 201 include from bottom to top according to
Gate dielectric 201a, the gate material layers 201b and grid hard masking layer 201c of secondary stacking.Gate dielectric 201a includes oxygen
Compound layer, such as silica (SiO2) layer.Gate material layers 201b includes polysilicon layer, metal layer, conductive metal nitride
One of nitride layer, conductive metal oxide layer and metal silicide layer are a variety of, wherein the constituent material of metal layer can be with
It is tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride (TiN) layer；Conductive metal oxide layer
Including yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.Grid hard masking layer 201c includes oxide
One of layer, nitride layer, oxynitride layer and amorphous carbon are a variety of, wherein the constituent material of oxide skin(coating) includes boron
Phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), ethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-coating glass
(SOG), high-density plasma (HDP) or spin-on dielectric (SOD)；Nitride layer includes silicon nitride (Si3N4) layer；Nitrogen oxidation
Nitride layer includes silicon oxynitride (SiON) layer.Gate dielectric 201a, gate material layers 201b and grid hard masking layer 201c's
Any prior art that forming method can be familiar with using those skilled in the art, preferably chemical vapour deposition technique (CVD), such as
Low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), etc. from
Daughter enhances chemical vapor deposition (PECVD).
In addition, as an example, being also formed on semiconductor substrate 200 positioned at 201 two sides of gate structure and against grid
The offset by gap wall construction 202 of structure 201.Wherein, offset by gap wall construction 202 may include at least monoxide layer and/or
Nitride layer.
Then, as shown in Figure 2 B, arciform groove is formed in the part that will form source/drain region of semiconductor substrate 200
203.Formed arciform groove 203 processing step include: first to the part that will form source/drain region of semiconductor substrate 200 into
Then row dry etching carries out wet etching to the groove to form groove.The dry etching is execution order interchangeable
The two step etching being made of isotropic etching and anisotropic etching, wherein the execution order of the two step etching can be with
It is determined according to the overall size of the groove desirably formed.The source gas packet of plasma used by the dry etching
It includes: CF4、CH3F、HBr、NF3、Cl2、O2、N2Deng carrier gas includes Ar, He etc..In a preferred embodiment, implement the dry method
The processing step of etching includes: first to be etched using anisotropic dry etching to semiconductor substrate 200, in semiconductor
Will being formed for substrate 200 forms groove in the part of source/drain region, plasma used by the anisotropic dry etching
The source gas of body is mainly CF4、CH3F, HBr, power 300-500W, bias 50-200V, 40-60 DEG C of temperature, the time is according to etching
Depending on depth；Continue to etch the groove using isotropic dry etching again, isotropic dry etching uses
Cl2And NF3As the main source gas of plasma, power 100-500W, bias 0-10V, 40-60 DEG C of temperature, time 5-50s.
Next, wet cleaning processes are executed, to remove the residue that above-mentioned etching process generates in arciform groove 203
And impurity.The cleaning solution that the wet cleaning processes use can be mixture (SC1) and the dilution of ammonium hydroxide, hydrogen peroxide and water
Hydrofluoric acid (DHF) combination, be also possible to the combination of Ozone Water, SC1 and DHF.Each cleaning solution in said combination it is dense
Other conditions required for the wet-cleaning, such as temperature and processing time etc. are spent and carried out, this field can be selected
The concentration values and implementation condition that technical staff is familiar with, are no longer enumerated herein.
Then, as shown in Figure 2 C, the high temperature anneal is executed, arciform groove 203 is made to be changed into U-shaped groove 203 '.It is described
High annealing can be such that the shrinkage degree of the constituent material for the semiconductor substrate 200 for being located at 201 lower section of gate structure increases, thus
Arch channel 203 is changed into U-shaped groove 203 ', and then enhances what the embedded germanium silicon being subsequently formed applied device channel region
Compression, while the residues such as the C/O generated in previous process processing procedure can be completely removed.The technological parameter of the high annealing
Include: temperature be 600-1200 DEG C, annealing time be 0-2 hours, annealing atmosphere H2, N2 or Ar, pressure 0-15MPa.
Then, as shown in Figure 2 D, U-shaped groove 203 ' is etched using wet etching process, to form ∑ shape groove 204.Benefit
With the different characteristic of etch-rate of the etchant of the wet etching on the different crystal orientations of the material of semiconductor substrate 200
(such as the etch-rate of 100 crystal orientation and 110 crystal orientation be higher than 111 crystal orientation etch-rate), extension etches U-shaped groove 203 ' with shape
At ∑ shape groove 204.In a preferred embodiment, U-shaped groove 203 ' is handled using tetramethyl ammonium hydroxide solution (TMAH),
The processing time is 1-3min, and treatment temperature is 25-50 DEG C.
Next, another wet cleaning processes are executed, to remove etch residues and impurity in ∑ shape groove 204, from
And it is conducive to the growth of subsequent embedded germanium silicon.The cleaning solution that another wet cleaning processes use can be ammonium hydroxide, hydrogen peroxide
With the combination of the mixture (SC1) and diluted hydrofluoric acid (DHF) of water, it is also possible to the combination of Ozone Water, SC1 and DHF.On
State the concentration of each cleaning solution in combination and carry out other conditions required for another wet-cleaning, for example, temperature and
Time etc. is handled, the concentration values and implementation condition that those skilled in the art can be selected to be familiar with no longer give example herein
It lifts.
Next, implementing low-temperature annealing processing to ∑ shape groove 204.The technological parameter of the low-temperature annealing includes: temperature
Lower than the temperature of the high annealing, the difference between the temperature of the high annealing and the temperature of the low-temperature annealing is 300-
700 DEG C, the temperature of the low-temperature annealing can be 500-900 DEG C, and annealing time is 0-2 hours, annealing atmosphere H2, N2 or
Ar, pressure 0-15MPa.Implement the low-temperature annealing, the temperature of the selective epitaxial growth process of subsequent implementation can be reduced,
Be conducive to the growth of the good germanium silicon layer with stronger compression.
Then, as shown in Figure 2 E, embedded germanium silicon layer is formed in ∑ shape groove 204 using selective epitaxial growth process
205.The selective epitaxial growth process can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical gas
Mutually deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam
One of extension (MBE).In the present embodiment, the selective epitaxial growth process can be implemented at low temperature, described low
The range of temperature is 500-850 DEG C.
In the present embodiment, it is formed before embedded germanium silicon layer 205, is initially formed seed layer in the bottom of ∑ shape groove 204
(seed layer) (to put it more simply, being not shown in figure), the seed layer are that a thin layer monocrystalline silicon layer or one have low germanium
The germanium silicon layer of content；It is formed after embedded germanium silicon layer 205, forms cap layers (cap layer) on embedded germanium silicon layer 205
(to put it more simply, being not shown in figure), the cap layers are a monocrystalline silicon layer or a germanium silicon layer with low Ge content.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, next, can pass through
Subsequent technique completes the production of entire semiconductor devices.According to the present invention it is possible to further promote the distribution of ∑ shape groove profile
The homogeneity of the thickness of uniformity and the embedded germanium silicon layer of formation reduces the temperature of selective epitaxial growth germanium silicon, in turn
The compression that embedded germanium silicon layer applies device channel region is further enhanced, device electrical performance can also be improved in wafer
The uniformity of distribution.
The whole processing steps for implementing the method proposed by the present invention for forming embedded germanium silicon above are with PMOS transistor
For be illustrated, it will be appreciated by those skilled in the art that, PMOS transistor here can be CMOS transistor
The part PMOS.
Referring to Fig. 3, the flow chart for the step of method according to an exemplary embodiment of the present invention is successively implemented is shown,
For schematically illustrating the process of entire manufacturing process.
In step 301, semiconductor substrate is provided, is formed with gate structure on a semiconductor substrate；
In step 302, arciform groove is formed in the part that will form source/drain region of semiconductor substrate；
In step 303, the high temperature anneal is executed, the U-shaped groove of arciform groove transition is made；
In step 304, the U-shaped groove formed after the high annealing is etched, to form ∑ shape groove, and it is recessed to ∑ shape
Slot implements low-temperature annealing processing；
In step 305, embedded germanium silicon layer is formed in ∑ shape groove.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacturing method of semiconductor devices, comprising:
Semiconductor substrate is provided, is formed with gate structure on the semiconductor substrate；
Arciform groove is formed in the part that will form source/drain region of the semiconductor substrate；
The high temperature anneal is executed, the U-shaped groove of arciform groove transition is made, the temperature of the high annealing is 600-1200
℃；
The U-shaped groove formed after the high annealing is etched, to form ∑ shape groove, and low temperature is implemented to the ∑ shape groove and is moved back
Fire processing, the difference between the temperature of the high annealing and the temperature of the low-temperature annealing are 300-700 DEG C；
Embedded germanium silicon layer is formed in the ∑ shape groove；Wherein, it is clear that the first wet process is executed before implementing the high annealing
Journey is washed, to remove residue and impurity in the arciform groove.
2. the method according to claim 1, wherein the step of forming the arciform groove includes: first to described
The part that will form source/drain region of semiconductor substrate carries out dry etching to form groove, then carries out to the groove wet
Method etching.
3. according to the method described in claim 2, it is characterized in that, the dry etching is from isotropic etching and each to different
Property the two step etching that constitutes of etching, the execution order of the two step etching is subject to really according to the overall size of the groove desirably formed
It is fixed.
4. the method according to claim 1, wherein the technological parameter of the high annealing includes: annealing time
It is 0-2 hours, annealing atmosphere H2, N2 or Ar, pressure 0-15MPa.
5. the method according to claim 1, wherein the technological parameter of the low-temperature annealing includes: that temperature is lower than
The temperature of the high annealing, annealing time are 0-2 hours, annealing atmosphere H2、N2Or Ar, pressure 0-15MPa.
6. according to the method described in claim 5, it is characterized in that, the temperature of the low-temperature annealing is 500-900 DEG C.
7. the method according to claim 1, wherein it is clear to execute the second wet process before implementing the low-temperature annealing
Journey is washed, to remove residue and impurity in the ∑ shape groove.
8. the method according to claim 1, wherein the formation ∑ shape groove is etched to wet etching, institute
The corrosive liquid for stating wet etching is tetramethyl ammonium hydroxide solution.
9. the method according to claim 1, wherein implement low temperature selective epitaxial growth technique formed it is described embedding
Enter formula germanium silicon layer, the temperature of the low temperature is 500-850 DEG C.
10. the method according to claim 1, wherein the gate structure includes stacking gradually from bottom to top
Gate dielectric, gate material layers and grid hard masking layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187269A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
| CN103594370A (en) * | 2012-08-16 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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| US7951657B2 (en) * | 2009-05-21 | 2011-05-31 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187269A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
| CN103594370A (en) * | 2012-08-16 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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