CN103903984B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN103903984B CN103903984B CN201210568167.9A CN201210568167A CN103903984B CN 103903984 B CN103903984 B CN 103903984B CN 201210568167 A CN201210568167 A CN 201210568167A CN 103903984 B CN103903984 B CN 103903984B
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 23
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000010790 dilution Methods 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 230000006872 improvement Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor substrate is provided, grid structure is formed with the Semiconductor substrate；The first side wall body is formed in the grid structure both sides；A thermal oxidation process is performed, oxide layer is formed with the surface of the Semiconductor substrate；The second sidewall body of the covering the first side wall body is formed in the grid structure both sides；Bowl-shape groove is formed in the source/drain region of the Semiconductor substrate；A wet cleaning processes are performed, to remove the oxide layer；The bowl-shape groove is etched, to form ∑ shape groove；Embedded germanium silicon layer is formed in the ∑ shape groove.According to the present invention, the Breadth Maximum along substrate level direction of the ∑ shape groove can be efficiently controlled, while not influenceing LDD to inject the improvement for the electric property of semiconductor devices, increase forms the process window of the dry method and wet etching implemented during the ∑ shape groove.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method for forming ∑ shape germanium silicon layer.
Background technology
In the manufacturing process of advanced semiconductor device, embedded germanium silicon technology can be remarkably reinforced the performance of PMOS.When
Before, the process sequence for forming embedded germanium silicon has two kinds：One kind is to be initially formed embedded germanium silicon, is then formed in the both sides of grid
Sidewall bodies；Another kind is first to form sidewall bodies in the both sides of grid, then forms embedded germanium silicon.In order to obtain bigger technique
Window and more preferable electric property, generally form embedded germanium silicon using the latter in above-mentioned process sequence.
In embedded germanium silicon technology, ∑ shape groove generally is formed for selectivity wherein in the source/drain region of PMOS
The embedded germanium silicon of epitaxial growth, the ∑ shape groove can effectively shorten the length of device channel, meet device size in proportion
The requirement of diminution.The ∑ shape groove is generally formed using the technique of first dry etching wet etching again, in above-mentioned etch process
During, it is extremely difficult to control as shown in Figure 1 sophisticated the 101 of the ∑ shape groove for ultimately forming depth.Such as
Really described sophisticated 101 depth is too deep, it will weakens and forms the LDD injections implemented before sidewall bodies 102 for semiconductor device
The influence of the electric property of part.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate, grid structure is formed with the Semiconductor substrate；The first side wall body is formed in the grid structure both sides；Perform a heat
Oxidizing process, oxide layer is formed with the surface of the Semiconductor substrate；Covering described the is formed in the grid structure both sides
The second sidewall body of one sidewall bodies；Bowl-shape groove is formed in the source/drain region of the Semiconductor substrate；Perform a wet-cleaning mistake
Journey, to remove the oxide layer；The bowl-shape groove is etched, to form ∑ shape groove.
Further, the material of the first side wall body is silicon nitride.
Further, the thickness of the oxide layer is 40-60 angstroms.
Further, the material of the second sidewall body is silicon nitride.
Further, the processing step for forming the second sidewall body includes：First formed on the semiconductor substrate described
Silicon nitride layer；The silicon nitride layer is etched using sidewall etch technique again.
Further, the processing step for forming the bowl-shape groove includes：First using dry method etch technology to the semiconductor
Substrate carries out longitudinal etching, to form a groove in the source/drain region of the Semiconductor substrate；Isotropic dry method is used again
Etch process continues to etch the groove, makes the groove transition into the bowl-shape groove.
Further, the wet-cleaning is implemented using the hydrofluoric acid of dilution.
Further, it is described to be etched to wet etching.
Further, using tetramethyl ammonium hydroxide solution as the wet etching corrosive liquid.
Further, after the etch, it is additionally included in the ∑ shape groove to be formed and forms embedded germanium silicon layer.
Further, the grid structure includes the gate dielectric, gate material layers and the grid hard masking layer that stack gradually
According to the present invention it is possible to the Breadth Maximum along substrate level direction of the ∑ shape groove is efficiently controlled, not
While influence LDD injects the improvement for the electric property of semiconductor devices, increase forms what is implemented during the ∑ shape groove
The process window of dry method and wet etching.
Brief description of the drawings
Drawings below of the invention is in this as a part of the invention for understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining principle of the invention.
In accompanying drawing：
Fig. 1 is the schematic cross sectional view of the ∑ shape groove formed in the technical process of formation ∑ shape germanium silicon layer；
Fig. 2A-Fig. 2 G are the schematic cross sectional view of each step of the method for formation ∑ shape germanium silicon layer proposed by the present invention；
Fig. 3 is the flow chart of the method for formation ∑ shape germanium silicon layer proposed by the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Formation ∑ shape germanium silicon layer method.Obviously, the technical staff that execution of the invention is not limited to semiconductor applications is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with
With other embodiment.
It should be appreciated that when use in this manual term "comprising" and/or " including " when, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more other features, entirety,
Step, operation, element, component and/or combinations thereof.
Below, by taking PMOS as an example, reference picture 2A- Fig. 2 G and Fig. 3 describes formation ∑ shape germanium silicon layer proposed by the present invention
The detailed step of method.
Reference picture 2A- Fig. 2 G, each step that illustrated therein is the method for formation ∑ shape germanium silicon layer proposed by the present invention is shown
Meaning property profile.
First, there is provided Semiconductor substrate 200, the constituent material of the Semiconductor substrate 200 can be using the list of undoped p
Crystal silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）Deng.As an example, in the present embodiment, the semiconductor lining
Bottom 200 is constituted from single crystal silicon material.Isolation structure, buried regions can also be formed with the Semiconductor substrate 200（In figure not
Show）Deng.Additionally, for PMOS, N traps can also be formed with the Semiconductor substrate 200（Not shown in figure）, and
Before grid structure is formed, low dose of boron injection, the threshold voltage for adjusting PMOS can be carried out once to whole N traps
Vth。
Grid structure is formed with the Semiconductor substrate 200, used as an example, the grid structure may include certainly
Gate dielectric, gate material layers and the grid hard masking layer stacked gradually on down.Gate dielectric may include oxide,
Such as, silica（SiO2）Layer.Gate material layers may include polysilicon layer, metal level, conductive metal nitride layer, electric conductivity
One or more in metal oxide layer and metal silicide layer, wherein, the constituent material of metal level can be tungsten（W）, nickel
（Ni）Or titanium（Ti）；Conductive metal nitride layer may include titanium nitride（TiN）Layer；Conductive metal oxide layer may include oxygen
Change iridium（IrO2）Layer；Metal silicide layer may include titanium silicide（TiSi）Layer.Grid hard masking layer may include oxide skin(coating), nitridation
One or more in nitride layer, oxynitride layer and amorphous carbon, wherein, oxide skin(coating) may include boron-phosphorosilicate glass（BPSG）、
Phosphorosilicate glass（PSG）, tetraethyl orthosilicate（TEOS）, undoped silicon glass（USG）, spin-coating glass（SOG）, high-density plasma
（HDP）Or spin-on dielectric（SOD）；Nitride layer may include silicon nitride（Si3N4）Layer；Oxynitride layer may include silicon oxynitride
（SiON）Layer.Used as another example, the grid structure can be Semiconductor Oxide-Nitride Oxide-semiconductor
（SONOS）Layer stacked gate structure.
Next, forming the first side wall body 201 in the grid structure both sides.In the present embodiment, the first side wall body
201 material is silicon nitride.The processing step for forming the first side wall body 201 includes：The shape in the Semiconductor substrate 200
Into silicon nitride layer；Using sidewall etch（blanket etch）Technique etches the silicon nitride layer, to form the first side wall
Body 201.The first side wall body 201 can define the tip 208 of ∑ shape groove as shown in figure 2f in the Semiconductor substrate
Position in 200.
The processing step of above-mentioned formation trap (well) structure, isolation structure and grid structure has been people in the art
Member is familiar with, and is no longer been described by detail herein.Additionally, before the first side wall body 201 is formed, also being injected including LDD
Lightly doped drain is formed with source/drain region（LDD）Structure（Not shown in figure）And Halo injections are with adjusting threshold voltage VtWith prevent
The break-through of source/drain depletion layer.
Then, as shown in Figure 2 B, a thermal oxidation process is performed, is aoxidized with being formed on the surface of the Semiconductor substrate 200
Layer 202.The thickness of the oxide layer 202 is 40-60 angstroms.Implementing the thermal oxide can be familiar with using those skilled in the art
Various suitable technique, such as wet process oxidation technology or rapid thermal oxidation process.
Then, as shown in Figure 2 C, the second sidewall of the covering the first side wall body 201 is formed in the grid structure both sides
Body 203.The material of the second sidewall body 203 is silicon nitride.The processing step for forming the second sidewall body 203 includes：
Silicon nitride layer is formed in the Semiconductor substrate 200；Using sidewall etch（blanket etch）Technique etches the silicon nitride
Layer, to form the second sidewall body 203.The second sidewall body 203 can expand the dry etching and wet method of subsequent implementation
The process window of cleaning.
Then, as shown in Figure 2 D, bowl-shape groove 204 is formed in the source/drain region of the Semiconductor substrate 200.Form institute
The processing step for stating bowl-shape groove 204 includes：Longitudinal erosion is first carried out to the Semiconductor substrate 200 using dry method etch technology
Carve, to form a groove in the source/drain region of the Semiconductor substrate 200, in the present embodiment, using CF4With HBr as master
Etching gas, 40-60 DEG C of temperature, power 200-400W biases 50-200V, etching period 10-20s；Next, using it is each to
The dry method etch technology of the same sex continues to etch the groove, makes the groove transition into the bowl-shape groove 204, in the present embodiment
In, using Cl2And NF3Used as main etching gas, 40-60 DEG C of temperature, power 100-500W biases 0-10V, etching period 5-
50s。
Then, as shown in Figure 2 E, a wet cleaning processes are performed, is lost with removing the oxide layer 202 and above-mentioned dry method
Carve remained etch material and impurity.In the present embodiment, the wet-cleaning is implemented using the hydrofluoric acid of dilution.It is described wet
After method cleaning terminates, in the breach formed below 205 of the second sidewall body 203, the breach 205 can be by subsequent implementation
Wet etching etching original position and direction preferably control to be changed in less scope at one, such that it is able to more have
Effect ground controls sophisticated 208 position in the Semiconductor substrate 200 of ∑ shape groove as shown in figure 2f, relative to existing skill
For art, the formation of ∑ shape groove can be further reduced for injection region is lightly doped（LDD）Influence.
Then, as shown in Figure 2 F, the bowl-shape groove 204 is etched using wet etching process, to form ∑ shape groove
206.Using etch-rate of the etchant of the wet etching on the different crystal orientations of the material of the Semiconductor substrate 200 not
Same characteristic（Etch-rate of the etch-rate of 100 and 110 crystal orientation higher than 111 crystal orientation）, the extension etching bowl-shape groove 204
To form the ∑ shape groove 206.The temperature of the wet etching is 30-60 DEG C, the phase of ∑ shape groove 204 described in basis of time
Hope depending on size, generally 100-300s.In the present embodiment, using TMAH（TMAH）Solution is used as described wet
The corrosive liquid of method etching.
Then, as shown in Figure 2 G, embedded germanium silicon layer is formed in the ∑ shape groove 206 using epitaxial growth technology
207.The epitaxial growth technology can use low-pressure chemical vapor deposition（LPCVD）, plasma enhanced chemical vapor deposition
（PECVD）, ultra-high vacuum CVD（UHVCVD）, rapid thermal CVD（RTCVD）And molecular beam epitaxy
（MBE）In one kind.
So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed, next, can be with
The making of whole semiconductor devices is completed by subsequent technique, the subsequent technique is complete with traditional process for fabricating semiconductor device
It is exactly the same.According to the present invention it is possible to efficiently control the tip as shown in figure 2f of the ∑ shape groove 206 for ultimately forming
208 depth（Efficiently control Breadth Maximum of the ∑ shape groove 206 along substrate level direction）, noted LDD is not influenceed
While entering the improvement for the electric property of semiconductor devices, increase forms the dry method and wet method implemented during the ∑ shape groove
The process window of etching.
Reference picture 3, illustrated therein is the flow chart of the method for formation ∑ shape germanium silicon layer proposed by the present invention, for briefly showing
Go out the flow of whole manufacturing process.
In step 301, there is provided Semiconductor substrate, it is formed with grid structure in the Semiconductor substrate；
In step 302, the first side wall body is formed in the grid structure both sides；
In step 303, a thermal oxidation process is performed, oxide layer is formed with the surface of the Semiconductor substrate；
In step 304, the second sidewall body of the covering the first side wall body is formed in the grid structure both sides；
In step 305, bowl-shape groove is formed in the source/drain region of the Semiconductor substrate；
Within step 306, a wet cleaning processes are performed, to remove the oxide layer；
In step 307, the bowl-shape groove is etched, to form ∑ shape groove；
In step 308, embedded germanium silicon layer is formed in the ∑ shape groove.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching of the invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, grid structure is formed with the Semiconductor substrate；
The first side wall body is formed in the grid structure both sides；
A thermal oxidation process is performed, oxide layer is formed with the surface of the Semiconductor substrate；
The second sidewall body of the covering the first side wall body is formed in the grid structure both sides；
Bowl-shape groove is formed in the source/drain region of the Semiconductor substrate；
A wet cleaning processes are performed, in the breach formed below of the second sidewall body while removal oxide layer；
The bowl-shape groove is etched, to form ∑ shape groove, the breach controls etching original position and the direction of the etching.
2. method according to claim 1, it is characterised in that the material of the first side wall body is silicon nitride.
3. method according to claim 1, it is characterised in that the thickness of the oxide layer is 40-60 angstroms.
4. method according to claim 1, it is characterised in that the material of the second sidewall body is silicon nitride.
5. method according to claim 4, it is characterised in that the processing step for forming the second sidewall body includes：First
The silicon nitride layer is formed on the semiconductor substrate；The silicon nitride layer is etched using sidewall etch technique again.
6. method according to claim 1, it is characterised in that the processing step for forming the bowl-shape groove includes：First adopt
Longitudinal etching is carried out to the Semiconductor substrate with dry method etch technology, is formed with the source/drain region of the Semiconductor substrate
One groove；Continue to etch the groove using isotropic dry method etch technology again, make the groove transition into described bowl-shape
Groove.
7. method according to claim 1, it is characterised in that the hydrofluoric acid using dilution implements the wet-cleaning.
8. method according to claim 1, it is characterised in that described to be etched to wet etching.
9. method according to claim 8, it is characterised in that lost as the wet method using tetramethyl ammonium hydroxide solution
The corrosive liquid at quarter.
10. method according to claim 1, it is characterised in that after the etch, be additionally included in the ∑ to be formed
Embedded germanium silicon layer is formed in shape groove.
11. methods according to claim 1, it is characterised in that the grid structure includes the gate dielectric for stacking gradually
Layer, gate material layers and grid hard masking layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210568167.9A CN103903984B (en) | 2012-12-24 | 2012-12-24 | A kind of manufacture method of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210568167.9A CN103903984B (en) | 2012-12-24 | 2012-12-24 | A kind of manufacture method of semiconductor devices |
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| Publication Number | Publication Date |
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| CN103903984A CN103903984A (en) | 2014-07-02 |
| CN103903984B true CN103903984B (en) | 2017-06-16 |
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| CN102810482A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
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| US7951657B2 (en) * | 2009-05-21 | 2011-05-31 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
| US8574970B2 (en) * | 2010-09-15 | 2013-11-05 | International Business Machines Corporation | Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain |
| KR20120108338A (en) * | 2011-03-23 | 2012-10-05 | 삼성전자주식회사 | Methods for fabricating semiconducor devices |
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| CN102810482A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
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