CN103151311B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN103151311B CN103151311B CN201110400078.9A CN201110400078A CN103151311B CN 103151311 B CN103151311 B CN 103151311B CN 201110400078 A CN201110400078 A CN 201110400078A CN 103151311 B CN103151311 B CN 103151311B
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Abstract
The manufacture method that the invention provides a kind of semiconductor devices, comprising: Semiconductor substrate is provided, and described Semiconductor substrate has nmos area and PMOS district, and in described Semiconductor substrate, is formed with grid structure and is positioned at the source/drain region of grid structure both sides; In described Semiconductor substrate, form monoxide layer to cover described grid structure, and on described oxide skin(coating), form a sacrifice layer; Sacrifice layer described in etching, to expose the described oxide skin(coating) at described grid structure top; Remove the described oxide skin(coating) at described grid structure top, and remove remaining described sacrifice layer; On described oxide skin(coating), form a silicon nitride layer to cover described grid structure; Described silicon nitride layer and described oxide skin(coating) and described Semiconductor substrate above source/drain region in PMOS district described in etching, to form a groove in the source/drain region in described PMOS district; In described groove, form embedded germanium silicon layer. According to the present invention, embedded germanium silicon technology can be integrated in whole manufacture of semiconductor better.
Description
Technical field
The present invention relates to semiconductor fabrication process, form the method for embedded germanium silicon (e-SiGe) in particular to one.
Background technology
In 28nm manufacture of semiconductor, embedded germanium silicon is often the technology of application. But it is very challenging that the forming process of embedded germanium silicon is integrated in whole manufacture of semiconductor effectively.
For CMOS, be used to form the degree of depth of the groove of embedded germanium silicon in order to be controlled at better PMOS part, conventionally on substrate, first form pair of lamina sacrifice layer, the formation of this double-deck sacrifice layer is: lower floor is oxide, upper strata is silicon nitride; After PMOS part forms embedded germanium silicon, while adopting wet clean process to remove the upper silicon nitride in the grid hard masking layer (its constituent material is generally silicon nitride) of grid structure and the double-deck sacrifice layer of NMOS part of PMOS part, due to stopping of the lower floor's oxide in double-deck sacrifice layer, cannot remove the grid hard masking layer of the grid structure of NMOS part simultaneously, thereby cause the increase of corresponding operation, be unfavorable for enhancing productivity and reducing manufacturing cost.
Therefore, a kind of method need to be proposed, to address the above problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor devices, comprise: Semiconductor substrate is provided, and described Semiconductor substrate has nmos area and PMOS district, and in described Semiconductor substrate, be formed with grid structure and be positioned at the source/drain region of grid structure both sides; In described Semiconductor substrate, form monoxide layer to cover described grid structure, and on described oxide skin(coating), form a sacrifice layer; Sacrifice layer described in etching, to expose the described oxide skin(coating) at described grid structure top; Remove the described oxide skin(coating) at described grid structure top, and remove remaining described sacrifice layer; On described oxide skin(coating), form a silicon nitride layer to cover described grid structure; Described silicon nitride layer and described oxide skin(coating) and described Semiconductor substrate above source/drain region in PMOS district described in etching, to form a groove in the source/drain region in described PMOS district; In described groove, form embedded germanium silicon layer.
Further, adopt chemical vapor deposition method to form described oxide skin(coating).
Further, the thickness of described oxide skin(coating) be less than described grid structure height 10%.
Further, the material of described sacrifice layer is organic material layer.
Further, the material of described sacrifice layer is bottom antireflective coating.
Further, adopt spin coating proceeding to form described sacrifice layer.
Further, sacrifice layer described in employing dry method etch technology etch-back.
Further, adopt dry method etch technology to remove the described oxide skin(coating) at described grid structure top.
Further, adopt cineration technics to remove remaining described sacrifice layer.
Further, adopt chemical vapor deposition method to form described silicon nitride layer.
Further, described silicon nitride layer and described oxide skin(coating) form pair of lamina sacrifice layer.
Further, before forming described groove, also comprise: on described silicon nitride layer, form a photoresist layer, graphical described photoresist floor is to expose the PMOS district of described Semiconductor substrate.
Further, adopt described in dry method etch technology longitudinal etching described silicon nitride layer and described oxide skin(coating) and the described Semiconductor substrate of top, source/drain region in PMOS district.
Further, adopt selective epitaxial growth process in described groove, to form embedded germanium silicon layer.
Further, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually.
Further, after forming described embedded germanium silicon layer, also comprise: adopt wet clean process to remove the grid hard masking layer of described silicon nitride layer and described grid structure.
Further, the corrosive liquid of described wet clean process is hot phosphoric acid.
According to the present invention, after PMOS part forms embedded germanium silicon, can remove upper silicon nitride in the grid hard masking layer of grid structure and the double-deck sacrifice layer of NMOS part of PMOS part and the grid hard masking layer of grid structure simultaneously, thereby embedded germanium silicon technology is integrated in whole manufacture of semiconductor better.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention. Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 G is the schematic cross sectional view of each step of the method for the embedded germanium silicon of formation that proposes of the present invention;
Fig. 2 is the flow chart of the method for the embedded germanium silicon of formation that proposes of the present invention.
Detailed description of the invention
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided. But, it is obvious to the skilled person that the present invention can be implemented without one or more these details. In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the method for the embedded germanium silicon of formation that explaination the present invention proposes. Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of. Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other embodiments.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
The detailed step of the method for the embedded germanium silicon of formation that the present invention proposes is described with reference to Figure 1A-Fig. 1 G and Fig. 2 below.
With reference to Figure 1A-Fig. 1 G, wherein show the schematic cross sectional view of each step of the method for the embedded germanium silicon of formation of the present invention's proposition.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity. As example, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form. In Semiconductor substrate 100, be formed with isolation structure 101, described isolation structure 101 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure. As example, in the present embodiment, described isolation structure 101 be shallow trench isolation from (STI) structure, Semiconductor substrate 100 is divided into nmos area and PMOS district by it. In described Semiconductor substrate 100, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.
In described Semiconductor substrate 100, be formed with grid structure, as an example, described grid structure can comprise the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top. Gate dielectric can comprise oxide, as, silica (SiO2) layer. Gate material layers can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, and wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; Conductive metal oxide layer can comprise yttrium oxide (IrO2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer. Grid hard masking layer can comprise one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon, wherein, oxide skin(coating) can comprise boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), ethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride layer can comprise silicon nitride (Si3N4) layer; Oxynitride layer can comprise silicon oxynitride (SiON) layer. In the present embodiment, described gate dielectric is oxide skin(coating), and described gate material layers is polysilicon layer, and described grid hard masking layer is silicon nitride layer.
In addition,, as example, in described Semiconductor substrate 100, be also formed with and be positioned at grid structure both sides and the clearance wall structure near grid structure. Wherein, clearance wall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.
The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure and clearance wall structure, by those skilled in the art are had the knack of, is described no longer in detail at this. In addition,, before forming described clearance wall structure, also comprise that LDD injects to inject with adjusting threshold voltage V in source/drain region formation lightly doped drain (LDD) structure and HalotBreak-through with the source of preventing/drain depletion layer. After forming described clearance wall structure, also comprise source/leakage injection.
Here, it should be noted that, before forming described grid structure, can in described Semiconductor substrate 100, form monoxide layer, so that described Semiconductor substrate 100 and described isolation structure 101 are avoided unnecessary loss in subsequent process steps.
Next, in described Semiconductor substrate 100, form monoxide layer 102 to cover described grid structure, the thickness of described oxide skin(coating) 102 be less than described grid structure height 10%. Adopt chemical vapor deposition method to form described oxide skin(coating) 102. Then, form a sacrifice layer 103 on described oxide skin(coating) 102, the material of described sacrifice layer 103 is organic material layer, the preferred bottom antireflective coating of the present embodiment (BARC). Adopt spin coating proceeding to form described sacrifice layer 103.
Then, as shown in Figure 1B, adopt sacrifice layer 103 described in dry method etch technology etch-back, to expose the described oxide skin(coating) 102 at described grid structure top. Wherein, the etching gas using is O2，O2Flow be 10-100sccm, power is 50-500W, pressure is 3-10mTorr.
Then, as shown in Figure 1 C, adopt dry method etch technology to remove the described oxide skin(coating) 102 at described grid structure top. Wherein, the etching gas using is CF4，CF4Flow be 10-1000sccm, power is 50-500W, pressure is 3-10mTorr. Then, adopt cineration technics to remove remaining described sacrifice layer 103.
Then,, as shown in Fig. 1 D, on described oxide skin(coating) 102, form a silicon nitride layer 104 to cover described grid structure. Adopt chemical vapor deposition method to form described silicon nitride layer 104. Described silicon nitride layer 104 and described oxide skin(coating) 102 form pair of lamina sacrifice layer, and its effect is the degree of depth of controlling the groove that is used to form embedded germanium silicon of follow-up formation. Then, form a photoresist layer 105 on described silicon nitride layer 104, graphical described photoresist floor 105 is to expose the PMOS district of described Semiconductor substrate 100.
Then,, as shown in Fig. 1 E, adopt described in dry method etch technology longitudinal etching described silicon nitride layer 104 and described oxide skin(coating) 102 and the described Semiconductor substrate 100 of top, source/drain region in PMOS district, to form a groove 106 in the source/drain region in described PMOS district. The etching gas that described longitudinal etching is used comprises fluoro-gas (CF4、CHF3、CH2F2Deng), diluent gas (He, N2Deng) and oxygen.
Then,, as shown in Fig. 1 F, adopt selective epitaxial growth process in described groove 106, to form embedded germanium silicon layer 107. Described selective epitaxial growth process can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Then, as shown in Figure 1 G, adopt wet clean process to remove the grid hard masking layer of described silicon nitride layer 104 and described grid structure. The corrosive liquid of described wet clean process is hot phosphoric acid.
So far, completed whole processing steps that method is implemented according to an exemplary embodiment of the present invention, next, can complete by subsequent technique the making of whole semiconductor devices, described subsequent technique is identical with traditional process for fabricating semiconductor device. According to the present invention, after PMOS part forms embedded germanium silicon, can remove upper silicon nitride in the grid hard masking layer of grid structure and the described double-deck sacrifice layer of NMOS part of PMOS part and the grid hard masking layer of grid structure simultaneously, thereby embedded germanium silicon technology is integrated in whole manufacture of semiconductor better.
With reference to Fig. 2, wherein show the flow chart of the method for the embedded germanium silicon of formation of the present invention's proposition, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, described Semiconductor substrate has nmos area and PMOS district, and in described Semiconductor substrate, is formed with grid structure and is positioned at the source/drain region of grid structure both sides;
In step 202, in described Semiconductor substrate, form monoxide layer to cover described grid structure, and on described oxide skin(coating), form a sacrifice layer;
In step 203, sacrifice layer described in etching, to expose the described oxide skin(coating) at described grid structure top;
In step 204, remove the described oxide skin(coating) at described grid structure top, and remove remaining described sacrifice layer;
In step 205, on described oxide skin(coating), form a silicon nitride layer to cover described grid structure;
In step 206, described silicon nitride layer and described oxide skin(coating) and the described Semiconductor substrate of top, source/drain region in PMOS district described in etching, to form a groove in the source/drain region in described PMOS district;
In step 207, in described groove, form embedded germanium silicon layer;
In step 208, remove the grid hard masking layer of described silicon nitride layer and described grid structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments. In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection. Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (15)
1. a manufacture method for semiconductor devices, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has nmos area and PMOS district,And in described Semiconductor substrate, be formed with grid structure and be positioned at the source of grid structure both sides/Drain region, described grid structure comprises the gate dielectric, gate material layers and the grid that stack graduallyHard masking layer, the both sides of described grid structure are formed with clearance wall structure;
In described Semiconductor substrate, form monoxide layer to cover described grid structure and instituteState clearance wall structure, and form a sacrifice layer on described oxide skin(coating);
Sacrifice layer described in etching, to expose the described oxide skin(coating) at described grid structure top;
Remove the described oxide skin(coating) at described grid structure top, firmly shelter to expose described gridLayer, and remove remaining described sacrifice layer;
On described oxide skin(coating), form a silicon nitride layer to cover described grid structure, described nitrogenSiClx layer and described oxide skin(coating) form pair of lamina sacrifice layer;
Described silicon nitride layer and described oxide above source/drain region in PMOS district described in etchingLayer and described Semiconductor substrate, to form a groove in the source/drain region in described PMOS district;
In described groove, form embedded germanium silicon layer.
2. method according to claim 1, is characterized in that, adopts chemical gaseous phase heavyLong-pending technique forms described oxide skin(coating).
3. method according to claim 1 and 2, is characterized in that, described oxideLayer thickness be less than described grid structure height 10%.
4. method according to claim 1, is characterized in that, at described oxide skin(coating)The material of the sacrifice layer of upper formation is organic material layer.
5. method according to claim 4, is characterized in that, described in described oxidationThe material of the sacrifice layer forming on thing layer is bottom antireflective coating.
6. method according to claim 1, is characterized in that, adopts spin coating proceeding shapeThe sacrifice layer that becomes to form on described oxide skin(coating).
7. method according to claim 1, is characterized in that, adopts dry etching workThe sacrifice layer that skill etch-back forms on described oxide skin(coating).
8. method according to claim 1, is characterized in that, adopts dry etching workSkill is removed the described oxide skin(coating) at described grid structure top.
9. method according to claim 1, is characterized in that, adopts cineration technics to goExcept the remaining sacrifice layer forming on described oxide skin(coating).
10. method according to claim 1, is characterized in that, adopts chemical gaseous phase heavyLong-pending technique forms described silicon nitride layer.
11. methods according to claim 1, is characterized in that, are forming described groove, also comprise before: on described silicon nitride layer, form a photoresist layer, graphically described inPhotoresist floor is to expose the PMOS district of described Semiconductor substrate.
12. methods according to claim 1, is characterized in that, adopt dry etching workDescribed silicon nitride layer and the described oxidation of top, source/drain region in PMOS district described in the longitudinal etching of skillThing layer and described Semiconductor substrate.
13. methods according to claim 1, is characterized in that, adopt selective epitaxialGrowth technique forms embedded germanium silicon layer in described groove.
14. methods according to claim 1, is characterized in that, are forming described embeddingAfter formula germanium silicon layer, also comprise: adopt wet clean process remove described silicon nitride layer and described inThe grid hard masking layer of grid structure.
15. methods according to claim 14, is characterized in that, described wet-cleaningThe corrosive liquid of technique is hot phosphoric acid.
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| CN108666272B (en) * | 2017-03-29 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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