CN106981424A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN106981424A CN106981424A CN201610034516.7A CN201610034516A CN106981424A CN 106981424 A CN106981424 A CN 106981424A CN 201610034516 A CN201610034516 A CN 201610034516A CN 106981424 A CN106981424 A CN 106981424A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000009434 installation Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000010276 construction Methods 0.000 claims abstract description 20
- 238000001039 wet etching Methods 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 239000007788 liquid Substances 0.000 claims description 10
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000010790 dilution Methods 0.000 claims description 5
- 239000012895 dilution Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims description 3
- 230000037431 insertion Effects 0.000 claims description 3
- 229910021340 platinum monosilicide Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 150
- 239000000463 material Substances 0.000 description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 11
- 239000011521 glass Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000000470 constituent Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- -1 TiN Chemical class 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, electronic installation, and methods described includes：Semiconductor substrate is provided, grid structure and the side wall construction positioned at grid structure both sides are formed with a semiconductor substrate；Embedded germanium silicon layer is formed in Semiconductor substrate between side wall construction；Silicon cap layer is formed at the top of embedded germanium silicon layer；Silicon cap layer is pre-processed by etch process, to expand the spacing of adjacent silicon cap layer.Bridged according to the present invention it is possible to avoid the formation of between the metal silicide on adjacent silicon cap layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its
Manufacture method, electronic installation.
Background technology
When the node of semiconductor fabrication process reaches 90nm and is following, stress technique (Stress
Engineering) it is widely used to improve the carrier mobility in semiconductor device channel area
Rate.For CMOS, form dual stressed layers generally on its substrate to improve its raceway groove
Carrier mobility in area, wherein, tension layer is used to improve in NMOS channel regions
Electron mobility, compressive stress layer is used to improve the hole mobility in PMOS channel regions.This
Outside, will in PMOS device in order to improve the mobility of carrier in PMOS channel regions
The technology that the part making groove of formation source/drain region is epitaxially embedded formula germanium silicon has become widely
The focus of concern.
Scaled due to device size, the length of device channel also accordingly shortens, therefore,
There is correlative study to point out to make side wall in the part that PMOS will form source/drain region to device ditch
The groove (i.e. ∑ shape groove) of road direction indent can effectively shorten the length of device channel, full
The scaled requirement of sufficient device size；Meanwhile, this groove has in grid structure both sides
Side wall construction below larger incision the characteristics of, thus, what is formed in this groove is embedded
Germanium silicon layer can produce bigger stress to PMOS channel region.
The process sequences that embedded germanium silicon is formed in PMOS source/drain region are：Offer is partly led
Body substrate, forms grid structure and the side wall positioned at grid structure both sides on a semiconductor substrate
Structure → ∑ shape groove → use selectivity is formed in the Semiconductor substrate of side wall construction both sides
Epitaxial growth technology forms embedded germanium silicon layer → on embedded germanium silicon layer in ∑ shape groove
Silicon cap layer (cap layer) is formed, the silicon cap layer is used to be formed before follow-up metal interconnection
Self-aligned silicide, while the intrinsic of the embedded germanium silicon layer that subsequent technique causes can also be avoided
The release of stress.
Answered in order that the embedded germanium silicon layer formed applies bigger pressure to PMOS channel region
Power, the thickness for the embedded germanium silicon layer being usually formed is more than the depth of ∑ shape groove.With partly leading
The continuous reduction of body device feature size, after forming silicon cap layer at the top of embedded germanium silicon layer,
Even if the very thin thickness of silicon cap layer, when being subsequently formed metal silicide, adjacent silicon cap is formed at
Metal silicide on layer is also easily bridged, and this is undesirable appearance.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices,
Including：Semiconductor substrate is provided, grid structure and position are formed with the semiconductor substrate
Side wall construction in the grid structure both sides；Semiconductor substrate between the side wall construction
It is middle to form embedded germanium silicon layer；Silicon cap layer is formed at the top of the embedded germanium silicon layer；Pass through
Etch process is pre-processed to the silicon cap layer, to expand the spacing of adjacent silicon cap layer.
In one example, the silicon cap layer is doped with boron or carbon.
In one example, the etch process includes the wet twice of different corrosive liquids is respectively adopted
Method is etched, and the corrosive liquid of first time wet etching is the hydrofluoric acid of dilution, second of wet etching
Corrosive liquid be tetramethyl ammonium hydroxide solution.
In one example, the volume ratio in the hydrofluoric acid of the dilution between hydrofluoric acid and water is
1:100-1:300, the temperature for implementing the first time wet etching is 20 DEG C -30 DEG C.
In one example, the temperature for implementing second of wet etching is 25 DEG C -30 DEG C.
In one example, before the embedded germanium silicon layer is formed, it is additionally included in for outer
The step of inculating crystal layer is formed on the side wall of the groove of embedded germanium silicon layer described in epitaxial growth and bottom.
In one example, the silicon cap layer is formed using epitaxial growth technology in situ.
In one example, after being pre-processed to the silicon cap layer, it is additionally included in the silicon cap
The step of forming metal silicide on layer, the composition of the metal silicide includes Ni PtSi.
In one embodiment, the present invention also provides a kind of semiconductor of use above method manufacture
Device.
In one embodiment, the present invention also provides a kind of electronic installation, the electronic installation bag
Include the semiconductor devices.
According to the present invention it is possible to avoid the formation of between the metal silicide on adjacent silicon cap layer
Bridge.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 C are the step implemented successively according to the method for exemplary embodiment of the present one
The schematic cross sectional view of the rapid device obtained respectively；
Fig. 2 is stream the step of implementation successively according to the method for exemplary embodiment of the present one
Cheng Tu.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
The process sequences that embedded germanium silicon is formed in PMOS source/drain region are：Offer is partly led
Body substrate, forms grid structure and the side wall positioned at grid structure both sides on a semiconductor substrate
Structure → ∑ shape groove → use selectivity is formed in the Semiconductor substrate of side wall construction both sides
Epitaxial growth technology forms embedded germanium silicon layer → on embedded germanium silicon layer in ∑ shape groove
Silicon cap layer is formed, the silicon cap layer is used to form autoregistration silication before follow-up metal interconnection
Thing, while releasing for the natural stress for the embedded germanium silicon layer that subsequent technique causes can also be avoided
Put.
Answered in order that the embedded germanium silicon layer formed applies bigger pressure to PMOS channel region
Power, the thickness for the embedded germanium silicon layer being usually formed is more than the depth of ∑ shape groove.With partly leading
The continuous reduction of body device feature size, after the formation silicon cap layer of embedded germanium silicon layer, even if
The very thin thickness of silicon cap layer, when being subsequently formed metal silicide, is formed on adjacent silicon cap layer
Metal silicide also easily bridge, this is that undesirable occur.
In order to solve the above problems, as shown in Fig. 2 the invention provides a kind of semiconductor devices
Manufacture method, this method includes：
In step 201 there is provided Semiconductor substrate, grid knot is formed with a semiconductor substrate
Structure and the side wall construction positioned at grid structure both sides；
In step 202., embedded germanium silicon is formed in the Semiconductor substrate between side wall construction
Layer；
In step 203, silicon cap layer is formed at the top of embedded germanium silicon layer；
In step 204, the silicon cap layer of formation is pre-processed by etch process, to expand
The spacing of big adjacent silicon cap layer.
According to the manufacture method of semiconductor devices proposed by the present invention, formed metal silicide it
It is preceding that the silicon cap layer of formation is pre-processed by etch process, expand adjacent silicon cap layer
Spacing, it is to avoid bridged between the metal silicide that is formed on adjacent silicon cap layer.
In order to thoroughly understand the present invention, will be proposed in following description detailed structure and/or
Step, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is retouched in detail
State it is as follows, but except these detailed description in addition to, the present invention can also have other embodiment.
[exemplary embodiment one]
Reference picture 1A- Fig. 1 C, illustrated therein is according to an exemplary embodiment of the present one side
The schematic cross sectional view for the device that the step of method is implemented successively obtains respectively.
First, as shown in Figure 1A there is provided Semiconductor substrate 100, Semiconductor substrate 100
Constituent material can use undoped with monocrystalline silicon, the monocrystalline silicon doped with impurity, on insulator
Be laminated on silicon (SOI), insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator,
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example,
In the present embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.
Isolation structure is formed with Semiconductor substrate 100, as an example, isolation structure is shallow
Trench isolations (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Isolation structure will
100 points of Semiconductor substrate is nmos area and PMOS areas, to put it more simply, only showing in diagram
Go out PMOS areas.Various traps (well) structure is also formed with Semiconductor substrate 100, for letter
Change, it is illustrated that in omitted.
Grid structure is formed with a semiconductor substrate 100, as an example, grid structure includes
Gate dielectric 102a, the gate material layers 102b and grid hard masking layer 102c stacked gradually.
Gate dielectric 102a includes oxide skin(coating), such as silica (SiO2) layer.Grid
Pole material layer 102b includes polysilicon layer, metal level, conductive metal nitride layer, conduction
One or more in property metal oxide layer and metal silicide layer, wherein, the structure of metal level
Can be tungsten (W), nickel (Ni) or titanium (Ti) into material；Conductive metal nitride layer bag
Include titanium nitride (TiN) layer；Conductive metal oxide layer includes yttrium oxide (IrO2) layer；
Metal silicide layer includes titanium silicide (TiSi) layer.
Grid hard masking layer 102c includes oxide skin(coating), nitride layer, oxynitride layer and nothing
One or more in setting carbon, wherein, the constituent material of oxide skin(coating) includes boron-phosphorosilicate glass
(BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass
(USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric
(SOD)；Nitride layer includes silicon nitride (Si3N4) layer；Oxynitride layer includes nitrogen oxidation
Silicon (SiON) layer.
Gate dielectric 102a, gate material layers 102b and grid hard masking layer 102c shape
Any prior art that can be familiar with into method using those skilled in the art, preferably chemical gas
Phase sedimentation (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition
(PECVD)。
In addition, as an example, being also formed with being located at grid structure two on a semiconductor substrate 100
Side and the side wall construction 101 for abutting grid structure.Wherein, side wall construction 101 by oxide,
Nitride or combination are constituted.
Before side wall construction 101 is formed, in addition to LDD injects to be formed gently in source/drain region
Doped drain (LDD) structure and Halo injections are with adjusting threshold voltage VtWith prevent source/drain from consuming
The break-through of layer to the greatest extent.After side wall construction 101 is formed, in addition to source drain implant.
Next, the Semiconductor substrate 100 between the side wall construction 101 positioned at PMOS areas
Middle formation groove 103.In order to effectively shorten the length of device channel, meet device size by than
The requirement that example reduces, the cross sectional shape of groove 103 is usually ∑ shape.
As an example, forming the processing step of the ∑ shape groove includes：First use anisotropy
Dry etching formation U-shaped groove, etching gas include HBr, Cl2, He and O2, no
Containing fluorine base gas, implement only to cover NMOS, it is necessary to be initially formed before the dry etching
The mask layer in area, as an example, mask layer can be the cushion and stress being laminated from bottom to top
Material layer, wherein, cushion can be oxide skin(coating) or silicon oxynitride layer, and stress material layer is
It can be the silicon nitride layer with tension；The U-shaped groove is etched again, it is described to be formed
∑ shape groove, implements the etching using wet etching process, utilizes the etchant of wet etching
The different characteristic of etch-rate on the different crystal orientations of the constituent material of Semiconductor substrate 100
(etch-rate of 100 crystal orientation and 110 crystal orientation is higher than the etch-rate of 111 crystal orientation), extension erosion
The U-shaped groove is carved to form the ∑ shape groove 104, as an example, the wet etching
Corrosive liquid be TMAH (TMAH) solution, temperature be 30 DEG C -60 DEG C, hold
Depending on the desired size of ∑ shape groove described in continuous basis of time, generally 100s-300s.
Then, as shown in Figure 1B, embedded germanium silicon is formed using selective epitaxial growth process
Layer 105, to be filled up completely with groove 103.In order that embedded germanium silicon layer 105 is to PMOS's
Channel region applies bigger compression, and the thickness of embedded germanium silicon layer 105 is more than groove 103
Depth.
Before the selective epitaxial growth process is implemented, can groove 103 side wall and
Inculating crystal layer 104 is formed on bottom.As an example, (germanium is former for the Ge content of embedded germanium silicon layer 105
Sub- percentage) it is 5-30%, it is necessary to explanation, the embedded germanium silicon layer 105 of formation can be with
Adulterate boron.The selective epitaxial growth process can use low-pressure chemical vapor deposition
(LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical
Outside vapour deposition (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam
Prolong one kind in (MBE).
Then, as shown in Figure 1 C, silicon cap layer 106 is formed at the top of embedded germanium silicon layer 105.
As an example, using epitaxial growth technology formation silicon cap layer 106 in situ, that is, forming silicon cap layer 106
The epitaxial growth technology used is with forming the epitaxial growth that embedded germanium silicon layer 105 is used
Technique is carried out in same reaction chamber.As an example, silicon cap layer 106 can adulterate boron and
Carbon, wherein, the dopant dose of the boron atom is 5.0 × e14-5.0×e20atom/cm2, it is described
The dopant dose of carbon atom is 5.0 × e14-5.0×e20atom/cm2。
Next, being pre-processed by etch process to the silicon cap layer 106 of formation, to expand
The spacing of adjacent silicon cap layer 106.
As an example, the etch process includes the erosion of wet method twice of different corrosive liquids is respectively adopted
Carve, the corrosive liquid of first time wet etching for dilution hydrofluoric acid (DHF), hydrofluoric acid and water it
Between proportioning (volume ratio) be 1:100-1:300, temperature is 20 DEG C -30 DEG C, silicon cap layer 106
Removal amount be 10 angstroms -30 angstroms；The corrosive liquid of second of wet etching is TMAH
Solution, temperature is 25 DEG C -30 DEG C, and the removal amount of silicon cap layer 106 is 10 angstroms -30 angstroms.
It can be removed positioned at the domatic top of embedded germanium silicon layer 105 by first time wet etching
The silicon cap layer 106 in face, can be located at embedded germanium silicon layer by second of wet etching with etch-back
The silicon cap layer 106 of 105 remaining top surface, it is possible thereby between increasing adjacent silicon cap layer 106
Away from.
So far, the technique step that according to an exemplary embodiment of the present one method is implemented is completed
Suddenly.It is understood that the present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps,
Before above-mentioned steps, among or may also include other desired step afterwards, it is included in
In the range of this implementation preparation method.
Compared with the prior art, according to the proposed method, by etch process to being formed
Silicon cap layer 106 pre-processed, to expand the spacing of adjacent silicon cap layer 106, thus may be used
Bridged with avoiding the formation of between the metal silicide on adjacent silicon cap layer 106.
[exemplary embodiment two]
The processing step implemented first there is provided according to an exemplary embodiment of the present one method is obtained
The semiconductor devices obtained, as shown in Figure 1 C, including：Semiconductor substrate 100, in semiconductor
Isolation structure and various traps (well) structure are formed with substrate 100, as an example, isolation
Structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
Grid structure on a semiconductor substrate 100 is formed, as an example, grid structure includes
Gate dielectric 102a, gate material layers 102b and the grid hard masking layer being laminated from bottom to top
102c。
Gate dielectric 102a includes oxide skin(coating), such as silica (SiO2) layer.Grid
Pole material layer 102b includes polysilicon layer, metal level, conductive metal nitride layer, conduction
One or more in property metal oxide layer and metal silicide layer, wherein, the structure of metal level
Can be tungsten (W), nickel (Ni) or titanium (Ti) into material；Conductive metal nitride layer bag
Include titanium nitride (TiN) layer；Conductive metal oxide layer includes yttrium oxide (IrO2) layer；
Metal silicide layer includes titanium silicide (TiSi) layer.
Grid hard masking layer 102c includes oxide skin(coating), nitride layer, oxynitride layer and nothing
One or more in setting carbon, wherein, the constituent material of oxide skin(coating) includes boron-phosphorosilicate glass
(BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass
(USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric
(SOD)；Nitride layer includes silicon nitride (Si3N4) layer；Oxynitride layer includes nitrogen oxidation
Silicon (SiON) layer.
Gate dielectric 102a, gate material layers 102b and grid hard masking layer 102c shape
Any prior art that can be familiar with into method using those skilled in the art, preferably chemical gas
Phase sedimentation (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition
(PECVD)。
It is formed at grid structure both sides and against the side wall construction 101 of grid structure, side wall construction
101 are made up of oxide, nitride or combination.
It is formed at the embedded germanium silicon layer in the Semiconductor substrate 100 of the both sides of side wall construction 101
105, the inculating crystal layer 104 that embedded germanium silicon layer 105 is located at part in Semiconductor substrate 100 is wrapped up,
And it is formed at the silicon cap layer 106 at the embedded top of germanium silicon layer 105.
Then, the making of whole semiconductor devices is completed by subsequent technique, including：In insertion
Metal silicide is formed on the top of formula germanium silicon layer 105.
As an example, forming the processing step of the metal silicide includes：
Metal level is initially formed, to cover silicon cap layer 106, side wall construction 101 and grid structure
Top, formed the metal level technique can using method conventional in the art, for example,
Physical vaporous deposition or vapour deposition method etc., the material of the metal level can be containing certain proportion
The nickel (Ni) of platinum (Pt), the ratio can be 0-15%, and the thickness of the metal level can
Think 50-300 angstroms, meanwhile, protective layer, the protective layer can be formed on the metal level
Material can be refractory metal nitride, such as TiN, the effect of the protective layer is to keep away
Exempt from the metal level to aoxidize exposed to the environment of non-inert, the thickness of the protective layer can
Think 50-200 angstroms；
The metal level is annealed using low-temperature rapid thermal annealing (RTA) technique again, institute
The temperature for stating low-temperature rapid thermal annealing can be 200-350 DEG C, by annealing, the gold
Belong to and being spread in silicon materials of the material in layer into silicon cap layer 106, and formed with the silicon materials
Metal silicide, as an example, the composition of metal silicide be Ni PtSi, Ni PtSiGeC,
Ni PtSiC etc.；
Finally, the metal silicide of formation is entered using high-temperature quick thermal annealing (RTA) technique
Row annealing, the temperature of the high-temperature quick thermal annealing can be 300-600 DEG C.
Implement the stress of channel region of the nearly casual labourer's skill of stress with humidification in PMOS areas, according to
Secondary formation contact etch stop layer and interlayer dielectric layer.
Form insertion interlayer dielectric layer and contact etch stop layer is respectively communicated with grid material
Layer 102b and metal silicide contact hole；Contact plug is formed in the contact hole.
Multiple interconnecting metal layers are formed, are generally completed using dual damascene process；Form gold
Belong to pad, wire bonding when being encapsulated for subsequent implementation device.
The silicon cap layer 106 of formation is pre-processed by etch process, to expand adjacent silicon
The spacing of cap layers 106, it is possible thereby to avoid the formation of in the metallic silicon on adjacent silicon cap layer 106
Bridged between compound.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and it includes according to an exemplary embodiment of the present two
Semiconductor devices.The electronic installation can be mobile phone, tablet personal computer, notebook computer,
Net book, game machine, television set, VCD, DVD, navigator, camera, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment or any bag
Include the intermediate products of the semiconductor devices.The electronic installation, due to partly being led using described
Body device, thus with better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that including：
Semiconductor substrate is provided, grid structure is formed with the semiconductor substrate and is located at
The side wall construction of the grid structure both sides；
Embedded germanium silicon layer is formed in Semiconductor substrate between the side wall construction；
Silicon cap layer is formed at the top of the embedded germanium silicon layer；
The silicon cap layer is pre-processed by etch process, to expand adjacent silicon cap layer
Spacing.
2. according to the method described in claim 1, it is characterised in that the silicon cap layer doping
There are boron or carbon.
3. according to the method described in claim 1, it is characterised in that the etch process bag
The wet etching twice that different corrosive liquids are respectively adopted is included, the corrosive liquid of first time wet etching is
The hydrofluoric acid of dilution, the corrosive liquid of second of wet etching is tetramethyl ammonium hydroxide solution.
4. method according to claim 3, it is characterised in that the hydrogen fluorine of the dilution
Volume ratio in acid between hydrofluoric acid and water is 1:100-1:300, implement the first time wet method erosion
The temperature at quarter is 20 DEG C -30 DEG C.
5. method according to claim 3, it is characterised in that implement described second
The temperature of wet etching is 25 DEG C -30 DEG C.
6. according to the method described in claim 1, it is characterised in that forming the insertion
Before formula germanium silicon layer, the side for the groove of embedded germanium silicon layer described in epitaxial growth is additionally included in
The step of inculating crystal layer is formed on wall and bottom.
7. according to the method described in claim 1, it is characterised in that using extension life in situ
Long technique forms the silicon cap layer.
8. according to the method described in claim 1, it is characterised in that the silicon cap layer is entered
After row pretreatment, the step of forming metal silicide on the silicon cap layer, the gold are additionally included in
Belonging to the composition of silicide includes Ni PtSi.
9. the semiconductor devices of the method manufacture described in a kind of one of use claim 1-8.
10. a kind of electronic installation, it is characterised in that the electronic installation includes claim 9
Described semiconductor devices.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817579A (en) * | 2017-11-20 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113013231A (en) * | 2021-02-24 | 2021-06-22 | 上海华力集成电路制造有限公司 | Method for improving device performance through selective epitaxy |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120097977A1 (en) * | 2010-10-22 | 2012-04-26 | Renesas Electronics Corporation | Semiconductor device and a method for manufacturing a semiconductor device |
| CN104183491A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN104217952A (en) * | 2013-06-04 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN104934323A (en) * | 2014-03-18 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104979291A (en) * | 2014-04-10 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
-
2016
- 2016-01-19 CN CN201610034516.7A patent/CN106981424A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120097977A1 (en) * | 2010-10-22 | 2012-04-26 | Renesas Electronics Corporation | Semiconductor device and a method for manufacturing a semiconductor device |
| CN104183491A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN104217952A (en) * | 2013-06-04 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN104934323A (en) * | 2014-03-18 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104979291A (en) * | 2014-04-10 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817579A (en) * | 2017-11-20 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113013231A (en) * | 2021-02-24 | 2021-06-22 | 上海华力集成电路制造有限公司 | Method for improving device performance through selective epitaxy |
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