CN106558550A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN106558550A CN106558550A CN201510622381.1A CN201510622381A CN106558550A CN 106558550 A CN106558550 A CN 106558550A CN 201510622381 A CN201510622381 A CN 201510622381A CN 106558550 A CN106558550 A CN 106558550A
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- germanium silicon
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000009434 installation Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 31
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052796 boron Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 21
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 19
- CHYRFIXHTWWYOX-UHFFFAOYSA-N [B].[Si].[Ge] Chemical compound [B].[Si].[Ge] CHYRFIXHTWWYOX-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000013078 crystal Substances 0.000 claims description 15
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical group C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 85
- 230000008569 process Effects 0.000 description 15
- 239000000463 material Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000010276 construction Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, electronic installation, and methods described includes：Semiconductor substrate is provided, and is formed with grid structure on a semiconductor substrate, groove is formed in the Semiconductor substrate of grid structure both sides；In a groove epitaxial growth adulterate boron germanium silicon layer while doped carbon.According to the present invention, doped carbon while forming the germanium silicon layer of doping boron, the pile up effect that can effectively suppress the boron for being doped in germanium silicon layer to produce to the interface diffusion between germanium silicon layer and Semiconductor substrate, the performance of boost device.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its
Manufacture method, electronic installation.
Background technology
In advanced cmos device manufacturing process, embedded germanium silicon technology Jing is often used
To lift the performance of the PMOS parts of cmos device.
For prior art, embedded germanium silicon layer is formed in the source/drain region of PMOS
Process sequences are：Semiconductor substrate is provided, grid structure and position is formed on a semiconductor substrate
In the side wall construction → formation in the Semiconductor substrate of side wall construction both sides of grid structure both sides
Groove → inculating crystal layer (seed is sequentially formed in a groove using selective epitaxial growth process
Layer) (optional), unadulterated germanium silicon layer (optional), the germanium silicon layer of doping boron and cap layers (can
Choosing).The germanium silicon layer of formation doping boron can further lift the carrier of the channel region of PMOS
Mobility, however, boron is easy to germanium silicon layer with inculating crystal layer (if not forming inculating crystal layer, for half
Conductor substrate) between interface diffusion, and then pile up (when mixing for boron in the interface
Miscellaneous concentration is higher than 1.0 × e20atom/cm3, this packing phenomenon is more notable), cause PMOS's
The reduction of performance, for example, cause more electric leakage.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
For the deficiencies in the prior art, the present invention provides a kind of manufacture method of semiconductor devices,
Including：Semiconductor substrate is provided, grid structure is formed with the semiconductor substrate, in institute
Groove is formed in the Semiconductor substrate for stating grid structure both sides；The epitaxial growth in the groove is mixed
Doped carbon while the germanium silicon layer of miscellaneous boron.
In one example, the groove is ∑ shape groove.
In one example, the ∑ shape is formed using the technique of first dry etching wet etching again
Groove.
In one example, the carbon source of the doped carbon be ethene, methyl-monosilane or methane, institute
The concentration for stating doped carbon is 1.0 × e18atom/cm3-1.0×e21atom/cm3, temperature is
400 DEG C -1000 DEG C, pressure is 0.1torr-760torr.
In one example, before forming the germanium silicon layer of the doping boron, it is additionally included in described recessed
The step of cushion is formed in groove.
In one example, before forming the cushion, formed in being additionally included in the groove
The step of inculating crystal layer.
In one example, adulterate described in epitaxial growth after the germanium silicon layer of boron, be additionally included in institute
State the step of cap layers being formed on the germanium silicon layer of doping boron.
In one embodiment, the present invention also provides a kind of semiconductor of employing said method manufacture
Device.
In one embodiment, the present invention also provides a kind of electronic installation, the electronic installation bag
Include the semiconductor devices.
According to the present invention, doped carbon while forming the germanium silicon layer of the doping boron can be effective
Suppression be doped in the boron of the germanium silicon layer to the germanium silicon layer with the inculating crystal layer (if not forming seed
Crystal layer, then be the Semiconductor substrate) between interface diffusion and the pile up effect that produces, carry
Rise the performance of PMOS.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 D are the step implemented according to the method for exemplary embodiment of the present one successively
The schematic cross sectional view of the rapid device for obtaining respectively；
Fig. 2 is the stream of the step of being implemented according to the method for exemplary embodiment of the present one successively
Cheng Tu.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to
Explain semiconductor devices proposed by the present invention and its manufacture method, electronic installation.Obviously, this
Bright execution is not limited to the specific details is familiar with by the technical staff of semiconductor applications.This
Bright preferred embodiment is described in detail as follows, but in addition to these detailed descriptions, the present invention is also
There can be other embodiment.
It should be appreciated that ought in this manual using term "comprising" and/or " including "
When, which indicates there is the feature, entirety, step, operation, element and/or component, but
Do not preclude the presence or addition of one or more other features, entirety, step, operation, element,
Component and/or combinations thereof.
[exemplary embodiment one]
Reference picture 1A- Fig. 1 D, illustrated therein is according to an exemplary embodiment of the present one side
The schematic cross sectional view of the device that the step of method is implemented successively obtains respectively.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, Semiconductor substrate 100
Constituent material can be using on unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, insulator
Be laminated on silicon (SOI), insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example,
In the present embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.Serve as a contrast in semiconductor
Isolation structure and various traps (well) structure are formed with bottom 100, to put it more simply, in diagram
Omitted.As an example, isolation structure is that shallow trench isolates (STI) structure or local oxygen
SiClx (LOCOS) isolation structure.For PMOS, the well structure is N traps, and
And before grid structure is formed, low dose of phosphorus injection can be carried out once to whole N traps,
For adjusting the threshold voltage V of PMOSth。
Grid structure 101, as an example, grid structure are formed with a semiconductor substrate 100
The 101 gate dielectric 101a for including stacking gradually from bottom to top, gate material layers 101b and
Grid hard masking layer 101c.Gate dielectric 101a includes oxide skin(coating), such as silica
(SiO2) layer.Gate material layers 101b include polysilicon layer, metal level, conductive metal
One or more in nitride layer, conductive metal oxide layer and metal silicide layer, its
In, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti)；Electric conductivity
Metal nitride layer includes titanium nitride (TiN) layer；Conductive metal oxide layer includes oxidation
Iridium (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.Grid hard masking layer
101c include the one kind in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon or
It is various, wherein, the constituent material of oxide skin(coating) includes boron-phosphorosilicate glass (BPSG), phosphorus silicon glass
Glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-coating glass
(SOG), high-density plasma (HDP) or spin-on dielectric (SOD)；Nitride layer
Including silicon nitride (Si3N4) layer；Oxynitride layer includes silicon oxynitride (SiON) layer.Grid
The forming method of pole dielectric layer 101a, gate material layers 101b and grid hard masking layer 101c
Any prior art that those skilled in the art can be adopted to be familiar with, preferred chemical vapor deposition
Method (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition
(PECVD)。
Additionally, as an example, it is also formed with positioned at grid structure on a semiconductor substrate 100
101 both sides and the offset by gap wall construction 102 against grid structure 101.Wherein, between skew
Gap wall construction 102 can include at least monoxide layer and/or nitride layer.
Then, as shown in Figure 1B, the process window for being constituted by offset by gap wall construction 102
Mouthful, ∑ shape groove 103 is formed in Semiconductor substrate 100.Generally using first dry etching again
The technique of wet etching forms ∑ shape groove 103, and the technique is comprised the following steps that：First adopt
Dry method etch technology Semiconductor substrate 100 longitudinally between etching offset by gap wall construction 102 with
Groove is formed, as an example, using CF4With HBr as main etching gas, temperature
40 DEG C -60 DEG C, power 200W-400W biases 50V-200V, and etching period is according to etching
Depending on depth；The etching groove is continued using isotropic dry method etch technology again, in institute
The oval-shaped groove formed below of groove is stated, that is, forms bowl-shape groove, as an example, adopted
Cl2And NF3As main etching gas, 40 DEG C -60 DEG C of temperature, power 100W-500W, partially
Pressure 0V-10V, etching period is according to the side wall of the bowl-shape groove to Semiconductor substrate 100
Depending on the recessed depth of channel region；It is finally described bowl-shape recessed using wet etching process extension etching
Groove, to form ∑ shape groove 103, the temperature of the wet etching is 30 DEG C -60 DEG C, the time
Depending on desired size according to ∑ shape groove 103, generally 100s-300s, as an example,
Using TMAH (TMAH) solution as the wet etching corrosive liquid.
Next, ∑ shape groove 103 is pre-processed, to guarantee the side of ∑ shape groove 103
Wall and bottom have the surface of cleaning.The pretreatment comprises the steps：First, perform wet
Method is cleaned, and residues in the side wall of ∑ shape groove 103 and the etch residues of bottom and miscellaneous to remove
Matter；Then, implement baking to Semiconductor substrate 100 to process.
As an example, the cleaning fluid of the wet-cleaning can be the mixed of ammoniacal liquor, hydrogen peroxide and water
Compound (SC1) and dilution hydrofluoric acid (DHF) combination, or Ozone Water,
The combination of SC1 and DHF.The concentration of each cleaning fluid in combinations thereof and carry out described
Other conditions required for wet-cleaning, such as temperature and process time etc., can be from this
Concentration values and implementation condition that art personnel are familiar with, here are no longer enumerated.
As an example, implement the baking under the atmosphere of hydrogen to process, it is described to bakee what is processed
Temperature is 780 DEG C -850 DEG C, and process time is 60s-120s.
Then, as shown in Figure 1 C, in the side wall and bottom formation undoped p of ∑ shape groove 103
Germanium silicon as cushion 104.The various suitable work being familiar with using those skilled in the art
Skill technology forms cushion 104, such as selective epitaxial growth process, including ultrahigh vacuum
Vapour deposition (UHVCVD), molecular beam epitaxy (MBE), rapid temperature chemical vapor sink
Product (RTCVD), plasma enhanced chemical vapor deposition (PECVD) etc..Form buffering
Before layer 104, an inculating crystal layer, the seed can also be formed using selective epitaxial growth process
Crystal layer can be silicon layer.As the germanium silicon layer for needing the doping boron to be subsequently formed reserves foot
Enough spaces, so the cushion 104 and inculating crystal layer that are formed can not be too thick, in case filling up whole
∑ shape groove 103.
Next, doping boron is formed on cushion 104 using selective epitaxial growth process
Germanium silicon layer 105, to be filled up completely with ∑ shape groove 103.As an example, the germanium silicon layer of doping boron
105 Ge content (germanium atom percentage) is 5-30%.The selective epitaxial growth process
Low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition can be adopted
(PECVD), ultra-high vacuum CVD (UHVCVD), rapid temperature chemical vapor
One kind in deposition (RTCVD) and molecular beam epitaxy (MBE).In the present embodiment,
When forming the germanium silicon layer 105 of doping boron, increase carbon source in source of the gas to suppress boron in germanium silicon layer
105 with inculating crystal layer (if not forming inculating crystal layer, for Semiconductor substrate 100) between interface
The accumulation at place.As an example, the carbon source can be ethene, methyl-monosilane, methane etc., mix
The concentration of miscellaneous carbon is 1.0 × e18atom/cm3-1.0×e21atom/cm3, temperature is
400 DEG C -1000 DEG C, pressure is 0.1torr-760torr.Due to the concentration of doped carbon it is low, Bu Huiying
Ring the stress intensity that the germanium silicon layer 105 of doping boron is produced to the channel region of PMOS.
Then, as shown in figure ip, the formation cap layers 106 on the germanium silicon layer 105 of doping boron.
Cap layers 106 are formed using epitaxial growth technology in situ, that is, forms the extension adopted by cap layers 106
The epitaxial growth technology adopted with the germanium silicon layer 105 for forming doping boron by growth technique is same
Carry out in individual reaction chamber.As an example, the constituent material of cap layers 106 can be silicon (Si)
Or borosilicate (SiB), wherein, in the borosilicate, the dopant dose of boron atom is 5.0 × e14
atom/cm3-5.0×e20atom/cm3；Can also be the monocrystalline silicon (SiCB) of doping boron and carbon,
Wherein, the dopant dose of the boron atom is 5.0 × e14atom/cm3-5.0×e20atom/cm3,
The dopant dose of the carbon atom is 5.0 × e14atom/cm3-5.0×e20atom/cm3。
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed,
Next, the making of whole semiconductor devices can be completed by subsequent technique.Implement this above
Whole processing steps of the method for the lifting PMOS performances that invention is proposed are with PMOS crystal
Illustrate as a example by pipe, it will be appreciated by those skilled in the art that, PMOS here
Transistor can be the PMOS parts of CMOS transistor.Additionally, ∑ shape groove 103
It is example, said method is equally applicable to be lifted with the epitaxial growth in other shapes of groove
Doping boron germanium silicon layer PMOS performance.According to the present invention, the germanium of doping boron is formed
Doped carbon while silicon layer, carbon can occupy the interstitial position in lattice, it is possible thereby to effectively press down
System be doped in the boron of germanium silicon layer 105 to germanium silicon layer 105 and inculating crystal layer (if not forming inculating crystal layer,
Then for Semiconductor substrate 100) between interface diffusion and the pile up effect that produces, lifting PMOS
Performance.
With reference to Fig. 2, illustrated therein is according to an exemplary embodiment of the present one method it is real successively
The flow chart of the step of applying, for schematically illustrating the flow process of manufacturing process.
In step 201, there is provided Semiconductor substrate, grid knot is formed with a semiconductor substrate
Structure, forms groove in the Semiconductor substrate of grid structure both sides；
In step 202., in a groove epitaxial growth adulterate boron germanium silicon layer while adulterate
Carbon；
In step 203, cap layers are formed on the germanium silicon layer of doping boron.
[exemplary embodiment two]
Next, the making of whole semiconductor devices can be completed by subsequent technique, including：
Implement the nearly casual labourer's skill of stress with humidification in the stress of the channel region in PMOS areas；Shape successively
Into contact etch stop layer and interlayer dielectric layer, and form insertion interlayer dielectric layer and contact hole
The source for being respectively communicated with gate material layers 101b, cap layers 106 and nmos area of etching stopping layer/
The contact hole in drain region；In 106 and of gate material layers 101b, cap layers exposed by contact hole
Silicide layer is formed on the top of the source/drain region of nmos area；Contact plug is formed in the contact hole；
Multiple interconnecting metal layers are formed, is completed generally using dual damascene process；Form metal welding
Disk, wire bonding when encapsulating for subsequent implementation device.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and which includes according to an exemplary embodiment of the present two
Method manufacture semiconductor devices.The electronic installation can be mobile phone, panel computer, pen
Remember this computer, net book, game machine, television set, VCD, DVD, navigator, photograph
Any electronic product such as machine, video camera, recording pen, MP3, MP4, PSP or equipment,
Can be any intermediate products including the semiconductor devices.The electronic installation, due to making
With the semiconductor devices, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, teaching of the invention can also be made more kinds of modifications and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (9)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, grid structure is formed with the semiconductor substrate, described
Groove is formed in the Semiconductor substrate of grid structure both sides；
The doped carbon while germanium silicon layer of epitaxial growth doping boron in the groove.
2. method according to claim 1, it is characterised in that the groove is ∑ shape
Groove.
3. method according to claim 2, it is characterised in that using first dry etching
The technique of wet etching forms the ∑ shape groove again.
4. method according to claim 1, it is characterised in that the carbon of the doped carbon
Source is ethene, methyl-monosilane or methane, and the concentration of the doped carbon is
1.0×e18atom/cm3-1.0×e21atom/cm3, temperature is 400 DEG C -1000 DEG C, and pressure is
0.1torr-760torr。
5. method according to claim 1, it is characterised in that form the doping boron
Germanium silicon layer before, be additionally included in the step of forming cushion in the groove.
6. method according to claim 5, it is characterised in that form the cushion
Before, the step of forming inculating crystal layer in being additionally included in the groove.
7. method according to claim 1, it is characterised in that mix described in epitaxial growth
After the germanium silicon layer of miscellaneous boron, it is additionally included on the germanium silicon layer of the doping boron and forms the step of cap layers
Suddenly.
8. the semiconductor devices that the method described in a kind of one of employing claim 1-7 is manufactured.
9. a kind of electronic installation, the electronic installation include the semiconductor described in claim 8
Device.
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| CN201510622381.1A CN106558550A (en) | 2015-09-25 | 2015-09-25 | A kind of semiconductor devices and its manufacture method, electronic installation |
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| CN201510622381.1A CN106558550A (en) | 2015-09-25 | 2015-09-25 | A kind of semiconductor devices and its manufacture method, electronic installation |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962987A (en) * | 2017-05-19 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
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|---|---|---|---|---|
| US20080242032A1 (en) * | 2007-03-29 | 2008-10-02 | Texas Instruments Incorporated | Carbon-Doped Epitaxial SiGe |
| US20080277699A1 (en) * | 2007-05-11 | 2008-11-13 | Texas Instruments Incorporated | Recess Etch for Epitaxial SiGe |
| CN103794546A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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2015
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080242032A1 (en) * | 2007-03-29 | 2008-10-02 | Texas Instruments Incorporated | Carbon-Doped Epitaxial SiGe |
| US20080277699A1 (en) * | 2007-05-11 | 2008-11-13 | Texas Instruments Incorporated | Recess Etch for Epitaxial SiGe |
| CN103794546A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962987A (en) * | 2017-05-19 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| CN108962987B (en) * | 2017-05-19 | 2020-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
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