CN107464741A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN107464741A CN107464741A CN201610392070.5A CN201610392070A CN107464741A CN 107464741 A CN107464741 A CN 107464741A CN 201610392070 A CN201610392070 A CN 201610392070A CN 107464741 A CN107464741 A CN 107464741A
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- semiconductor substrate
- side wall
- layer
- rinse bath
- germanium silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
Abstract
The present invention, which provides a kind of semiconductor devices and its manufacture method, electronic installation, methods described, to be included：The Semiconductor substrate with PMOS areas is provided, on a semiconductor substrate the side wall construction formed with grid structure and positioned at grid structure both sides；Mask layer is formed on a semiconductor substrate, covers grid structure and side wall construction；The mask layer is patterned, to form mask side wall in the outside of side wall construction；Embedded germanium silicon layer is formed in the Semiconductor substrate of the grid structure both sides in the PMOS areas exposed；Remove the mask side wall；Semiconductor substrate is placed in rinse bath and got express developed, and fast evacuation rinse bath, the defects of formation when forming embedded germanium silicon with effective removing in wafer.According to the present invention it is possible to effectively remove the defects of implementing to be formed in wafer during embedded germanium silicon technology, product yield is lifted.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacture method, electronics
Device.
Background technology
In the manufacturing process of advanced semiconductor device, embedded germanium silicon technology can be remarkably reinforced PMOS performance.For
Bigger process window and more preferable electric property are obtained, is typically first to form side wall construction in the both sides of grid, then shape
Into embedded germanium silicon.
In existing embedded germanium silicon technology, ∑ shape groove is generally formed in PMOS source/drain region for wherein
The embedded germanium silicon of selective epitaxial growth, ∑ shape groove can effectively shorten the length of device channel, meet device size by than
The requirement that example reduces.Generally use elder generation dry etching again wet etching technique formed ∑ shape groove, formed ∑ shape groove it
It is preceding, it is necessary to be initially formed the mask layer of bridging effect, formed after ∑ shape groove, using wet etching of the phosphoric acid as corrosive liquid
Technique removes the mask layer.However, after removing the mask layer, defect and residual are constantly present on wafer, to follow-up
Process implementing has undesirable effect.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Offer has
The Semiconductor substrate in PMOS areas, on the semiconductor substrate formed with grid structure and positioned at the grid structure both sides
Side wall construction；Mask layer is formed on the semiconductor substrate, covers the grid structure and the side wall construction；Patterning institute
Mask layer is stated, to form mask side wall in the outside of the side wall construction；In the grid structure both sides in the PMOS areas exposed
Semiconductor substrate in form embedded germanium silicon layer；Remove the mask side wall；The Semiconductor substrate is placed in the cleaning
Got express developed in groove, and rinse bath described in fast evacuation, when forming the embedded germanium silicon with effective removing in wafer
The defects of formation.
In one example, the Semiconductor substrate is placed in the rinse bath and get express developed simultaneously fast evacuation institute
The duration for stating rinse bath is 5s-15s.
In one example, the Semiconductor substrate is placed in the rinse bath and get express developed simultaneously fast evacuation institute
After stating rinse bath, in addition to by the Semiconductor substrate immersion hydrogen peroxide and be dissolved in deionized water ozone form it is mixed
Step in compound, the defect of residual is aoxidized, duration 30s-300s.
In one example, implement overflow processing and remove the defect through peroxidating, duration 60s-300s.
In one example, the mask layer includes the cushion and stress material layer being laminated from bottom to top.
In one example, at the top of the embedded germanium silicon layer formed with cap layers.
In one example, the mask side wall is removed using wet etching process of the phosphoric acid as corrosive liquid.
In one embodiment, the present invention also provides a kind of semiconductor devices manufactured using the above method.
In one embodiment, the present invention also provides a kind of electronic installation, and the electronic installation includes the semiconductor device
Part.
According to the present invention it is possible to the defects of implementing to be formed in wafer during embedded germanium silicon technology is effectively removed, lifting production
Product yield.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 E are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present one
The schematic cross sectional view of part；
Fig. 2 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present one；
Fig. 3 is the schematic diagram according to the electronic installation of exemplary embodiment of the present three.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In existing embedded germanium silicon technology, ∑ shape groove is generally formed in PMOS source/drain region for wherein
The embedded germanium silicon of selective epitaxial growth, ∑ shape groove can effectively shorten the length of device channel, meet device size by than
The requirement that example reduces.Generally use elder generation dry etching again wet etching technique formed ∑ shape groove, formed ∑ shape groove it
It is preceding, it is necessary to be initially formed the mask layer of bridging effect, formed after ∑ shape groove, using wet etching of the phosphoric acid as corrosive liquid
Technique removes the mask layer.However, after removing the mask layer, defect and residual are constantly present on wafer, to follow-up
Process implementing has undesirable effect.
In order to solve the above problems, as shown in Fig. 2 the invention provides a kind of manufacture method of semiconductor devices, the party
Method includes：
In step 201, there is provided have PMOS areas Semiconductor substrate, on a semiconductor substrate formed with grid structure with
And the side wall construction positioned at grid structure both sides；
In step 202, mask layer is formed on a semiconductor substrate, covers grid structure and side wall construction；
In step 203, the mask layer is patterned, to form mask side wall in the outside of side wall construction；
In step 204, embedded germanium silicon is formed in the Semiconductor substrate of the grid structure both sides in the PMOS areas exposed
Layer；
In step 205, the mask side wall is removed；
In step 206, Semiconductor substrate is placed in rinse bath and got express developed, and fast evacuation rinse bath, with
Effectively remove the defects of being formed when forming embedded germanium silicon in wafer.
Get express developed simultaneously fast evacuation rinse bath by the way that Semiconductor substrate is placed in rinse bath, can effectively remove
Implement the defects of previous process is formed in wafer, while may insure that wafer is exposed in air to avoid causing in short time
Undesirable oxidation.
Semiconductor substrate is placed in rinse bath and get express developed and after fast evacuation rinse bath, by Semiconductor substrate
Immersion hydrogen peroxide aoxidizes with the defects of being dissolved in the mixture of ozone composition of deionized water, will can still remain, and
Removed by the overflow processing of subsequent implementation.
According to the manufacture method of semiconductor devices proposed by the present invention, can effectively remove when implementing embedded germanium silicon technology
The defects of being formed in wafer, lift product yield.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to explain this
Invent the technical scheme proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
[exemplary embodiment one]
Reference picture 1A- Fig. 1 E, the step of according to an exemplary embodiment of the present one method of illustrated therein is is implemented successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, the constituent material of Semiconductor substrate 100, which can use, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), silicon (SSOI), insulator upper strata are laminated on insulator
Folded SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, at this
In embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.
Formed with isolation structure 101 in Semiconductor substrate 100, as an example, isolation structure 101 is isolated for shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.Isolation structure 101 Semiconductor substrate 100 is divided for nmos area and
PMOS areas.Various traps (well) structure is also formed with Semiconductor substrate 100, to put it more simply, being omitted in diagram.
By taking fleet plough groove isolation structure as an example, hard mask layer is first formed on the substrate, using those skilled in the art institute
The various suitable technologies being familiar with form the hard mask layer, such as chemical vapor deposition method, the hard mask layer
The preferred silicon nitride of material.
The hard mask layer is patterned again, and opening for fleet plough groove isolation structure pattern is formed to be formed in the hard mask layer
Mouthful, the process includes：The photoresist layer with fleet plough groove isolation structure pattern is formed on the hard mask layer, with the photoetching
Glue-line is mask, etches the hard mask layer until exposing the substrate, and the photoresist layer is removed using cineration technics.
Then, using the hard mask layer of the patterning as mask, etched in the substrate for formed shallow trench every
From the groove of structure.Then, depositing isolation material, the isolated material are usually oxygen in the trench and on hard mask layer
Compound, preferably HARP.Next, performing chemical mechanical milling tech to grind the isolated material, described covered firmly until exposing
Film layer.
In above process, in order to ensure realizing that the zero-clearance of isolated material is filled in the trench, the isolated material
Deposition (be usually three times) completes several times, the composition of the isolated material formed each time is identical.In the deposition
Afterwards, annealing is performed, so that the isolated material densification formed, lifts its mechanical strength.After the grinding, perform another
Annealing, to repair damage of the said process to the substrate, the interface improved between fleet plough groove isolation structure and the substrate is special
Property.
It should be noted that in the examples described above, being formed before the hard mask layer, one layer of oxide thin layer can be initially formed
Thing is as cushion, to discharge the stress between the hard mask layer and the substrate；Before depositing the isolated material, in institute
State on hard mask layer and another oxide thin layer thing structure is formed on the side wall of the groove for forming fleet plough groove isolation structure and bottom
Into backing layer.
On a semiconductor substrate 100 formed with grid structure, as an example, the grid that grid structure includes stacking gradually is situated between
Electric layer 102a, gate material layers 102b and grid hard masking layer 102c.Gate dielectric 102a includes oxide skin(coating), such as dioxy
SiClx (SiO2) layer.Gate material layers 102b includes polysilicon layer, metal level, conductive metal nitride layer, conductive metal
One or more in oxide skin(coating) and metal silicide layer, wherein, the constituent material of metal level can be tungsten (W), nickel (Ni)
Or titanium (Ti)；Conductive metal nitride layer includes titanium nitride (TiN) layer；Conductive metal oxide layer includes yttrium oxide
(IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.Grid hard masking layer 102c includes oxide skin(coating), nitride
One or more in layer, oxynitride layer and amorphous carbon, wherein, the constituent material of oxide skin(coating) includes boron-phosphorosilicate glass
(BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high density
Plasma (HDP) or spin-on dielectric (SOD)；Nitride layer includes silicon nitride (Si3N4) layer；Oxynitride layer includes nitrogen oxygen
SiClx (SiON) layer.
Gate dielectric 102a, gate material layers 102b and grid hard masking layer 102c forming method can use this
Any prior art that art personnel are familiar with, preferably chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), PECVD
Deposit (PECVD).
In addition, as an example, it is also formed with a semiconductor substrate 100 positioned at grid structure both sides and abuts grid structure
Side wall construction 103.Wherein, side wall construction 103 is made up of oxide, nitride or combination.
Before side wall construction 103 is formed, in addition to LDD injection with source/drain region formed lightly doped drain (LDD) structure and
Halo is injected with adjusting threshold voltage VtWith the break-through for preventing source/drain depletion layer.After side wall construction 103 is formed, in addition to
Source drain implant.
Next, being sequentially depositing cushion 104 and stress material layer 105 on a semiconductor substrate 100, grid structure is covered
With side wall construction 103.As an example, cushion 104 can be oxide skin(coating) or silicon oxynitride layer, thickness is 80-150 angstroms, excellent
Select 100 angstroms；For stress material layer 105 for that can be the silicon nitride layer with tension, thickness be 150-500 angstroms.The He of cushion 104
Stress material floor 105 collectively forms subsequently forms the mask layer of ∑ shape groove in PMOS areas.
Next, bottom antireflective coating (BARC layer) 106 and photoresist are sequentially formed on stress material layer 105
Layer 107, the photoresist layer 107 for being covered in PMOS areas is then removed by the technique such as expose, develop.
Then, as shown in Figure 1B, the BARC layer 106 for being covered in PMOS areas is removed, and etches and answers dead-wood positioned at PMOS areas
The bed of material 105 and cushion 104, to form mask side wall in the outside of side wall construction 103.
As an example, implementing three step etchings completes the removal：Perform the first step etching and be covered in PMOS areas to remove
BARC layer 106, etching gas include SO2And N2；Perform the second step etching and be covered in the stress material floor 105 in PMOS areas to etch,
Second step etching, which includes the main etching implemented successively and overetch, the etching gas of main etching, includes CF4, Ar and O2, cross and lose
The etching gas at quarter includes CH3F, He and O2；Perform the 3rd step etching and be covered in the cushion 104 in PMOS areas to etch, etch gas
Body includes CF4And Ar.
Then, as shown in Figure 1 C, the photoresist layer 107 and BARC layer 106 for being covered in nmos area are removed.
Then, ashing processing is implemented, to remove the Semiconductor substrate that PMOS areas are residued in caused by foregoing etching process
100 and the mask side wall positioned at the outside of side wall construction 103 surface on polymer.As an example, ashing processing be
N2And H2Atmosphere under carry out, wherein, H2Content be 4%-40%, temperature is 25 DEG C -400 DEG C.
Next, exposing the formation ∑ shape groove in the Semiconductor substrate 100 of the grid structure both sides in PMOS areas
109。
As an example, first exposed using anisotropic dry etching positioned at the half of the grid structure both sides in PMOS areas
Bowl-shape groove is formed in conductor substrate 100, etching gas includes HBr, Cl2, He and O2, do not contain fluorine base gas.Due to being formed
Ashing processing is had been carried out before the bowl-shape groove, can avoid removing the He of photoresist layer 107 for being covered in nmos area
The polymer remained after BARC layer 106 influences the etching selectivity of the anisotropic dry etching, and then can accurately control
Make the width of the bowl-shape groove.
Next, implement another ashing processing, it is described to be residued in after the removal implementation anisotropic dry etching
The side wall of bowl-shape groove and the polymer of bottom.As an example, another ashing processing is the H in high concentration2Atmosphere under
Carry out, wherein, H2Content be 40%-100%, temperature is 300 DEG C -400 DEG C.
Next, the bowl-shape groove is etched using wet etching process, using the etchant of wet etching in semiconductor
Different characteristic (the etch-rate of 100 crystal orientation and 110 crystal orientation of etch-rate on the different crystal orientations of the constituent material of substrate 100
Higher than the etch-rate of 111 crystal orientation), extension etches the bowl-shape groove to form ∑ shape groove 109.
As an example, the corrosive liquid of the wet etching is TMAH (TMAH) solution, temperature is 30 DEG C -60
DEG C, depending on desired size of the duration according to ∑ shape groove 109, generally 100s-300s.Due to implementing the wet method erosion
Another ashing processing is had been carried out before quarter, it is described wet that the polymer influence remained after the bowl-shape groove can be avoided the formation of
The etching characteristic of method etching, effectively controls the size of the widest part of ∑ shape groove 109, while makes the ∑ shape groove 109 to be formed
The surface of side wall and bottom is advantageous to the epitaxial growth of follow-up embedded germanium silicon.
Then, as shown in figure iD, embedded germanium silicon layer 110 is formed.As an example, the epitaxial growth in ∑ shape groove 109
Embedded germanium silicon layer 110, the epitaxial growth technology can use low-pressure chemical vapor deposition (LPCVD), plasma enhancing
Chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and
One kind in molecular beam epitaxy (MBE).
As an example, the Ge content (germanium atom percentage) of embedded germanium silicon layer 110 is 5-50%, embedded germanium silicon layer
110 can be single layer structure or sandwich construction, and the Ge content difference in the sandwich construction is needed with forming ge concentration variation gradient
It is noted that the embedded germanium silicon layer 110 formed can adulterate boron.
Then, cap layers 111 are formed on embedded germanium silicon layer 110.As an example, formed using epitaxial growth technology in situ
Cap layers 111, that is, extension is given birth to used by forming used by cap layers 111 epitaxial growth technology and forming embedded germanium silicon layer 110
Long technique is carried out in same reaction chamber.As an example, the constituent material of cap layers 111 can be silicon (Si) or borosilicate
(SiB) or doping boron and carbon monocrystalline silicon (SiCB).
Then, as referring to figure 1E, remove when PMOS areas form ∑ shape groove as mask layer positioned at the slow of nmos area
Rush floor 104 and stress material floor 105 and the mask side wall positioned at the outside of side wall construction 103 in PMOS areas.As an example, using
Phosphoric acid implements the removal as corrosive liquid wet etching process.
Before the removal is implemented, Semiconductor substrate 100 is made annealing treatment, to activate device source/drain regions, simultaneously
Make device grids again crystallization to remember tension caused by stress material layer 105, so as to remove stress material layer 105 it
After make device grids that this tension continuingly acted on into device channel region, the annealing can be laser peak annealing, move back
Fiery temperature is 500-1300 DEG C.
Get express developed simultaneously rinse bath described in fast evacuation next, Semiconductor substrate 100 is placed in rinse bath, hold
The continuous time is 5s-15s.Then, the immersion hydrogen peroxide of Semiconductor substrate 100 is formed with the ozone for being dissolved in deionized water mixed
In compound, duration 30s-300s.Finally, overflow (over flow) processing is implemented to Semiconductor substrate 100, when continuing
Between be 60s-300s.
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is understood that
The present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include afterwards
Other desired step, it is included in the range of this implementation preparation method.
Compared with the prior art, according to the proposed method, its masking when PMOS areas form ∑ shape groove is removed
After the mask layer of effect, Semiconductor substrate 100 is placed in rinse bath and get express developed simultaneously rinse bath described in fast evacuation, can
The defects of previous process is formed in wafer is implemented with effective remove, while may insure that wafer is exposed in air in short time
To avoid causing undesirable oxidation；The immersion hydrogen peroxide of Semiconductor substrate 100 and the ozone for being dissolved in deionized water are formed
Mixture in, the defects of can still remaining, aoxidizes, and is removed by the overflow processing of subsequent implementation.
[exemplary embodiment two]
First, there is provided the semiconductor device that the processing step that one method is implemented according to an exemplary embodiment of the present obtains
Part, as referring to figure 1E, including：Semiconductor substrate 100, formed with isolation structure 101 and various traps in Semiconductor substrate 100
(well) structure, (STI) structure or selective oxidation silicon (LOCOS) isolation are isolated as an example, isolation structure 101 is shallow trench
Structure.Isolation structure 101 divides Semiconductor substrate 100 for nmos area and PMOS areas.
Grid structure on a semiconductor substrate 100 is formed, as an example, grid structure includes the grid being laminated from bottom to top
Pole dielectric layer 102a, gate material layers 102b and grid hard masking layer 102c.
It is formed at grid structure both sides and against the side wall construction 103 of grid structure, side wall construction 103 is by oxide, nitrogen
Compound or combination are formed.Before side wall construction 103 is formed, in addition to LDD injections are gently mixed with being formed in source/drain region
Miscellaneous leakage (LDD) structure and Halo injections are with adjusting threshold voltage VtWith the break-through for preventing source/drain depletion layer.Forming side wall construction
After 103, in addition to source drain implant.
It is formed at the embedded germanium silicon layer 110 in PMOS areas.As an example, embedded germanium silicon is formed using epitaxial growth technology
Layer 110, the epitaxial growth technology can use low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, superelevation
One kind in chemical vapor deposition, rapid thermal CVD and molecular beam epitaxy.
As an example, the Ge content (germanium atom percentage) of embedded germanium silicon layer 110 is 5-50%, embedded germanium silicon layer
110 can be single layer structure or sandwich construction, and the Ge content difference in the sandwich construction is needed with forming ge concentration variation gradient
It is noted that the embedded germanium silicon layer 110 formed can adulterate boron.
It is formed at the cap layers 111 at the embedded top of germanium silicon layer 110.As an example, formed using epitaxial growth technology in situ
Cap layers 111, that is, extension is given birth to used by forming used by cap layers 111 epitaxial growth technology and forming embedded germanium silicon layer 110
Long technique is carried out in same reaction chamber.As an example, the constituent material of cap layers 111 can be silicon or borosilicate, also may be used
To be the monocrystalline silicon for adulterating boron and carbon.
Then, the making of whole semiconductor devices is completed by subsequent technique, including：Interlayer dielectric layer is formed, and in institute
State the source/drain region for being formed in interlayer dielectric layer and being respectively communicated with gate material layers 102b, embedded germanium silicon layer 110 and the nmos area
Contact hole；In gate material layers 102b, embedded germanium silicon layer 110 and the nmos area exposed by the contact hole
Silicide layer is formed on the top of source/drain region；Contact plug is formed in the contact hole；Multiple interconnecting metal layers are formed, are generally adopted
Completed with dual damascene process；Form metal pad, wire bonding when being encapsulated for subsequent implementation device.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and it includes according to an exemplary embodiment of the present two semiconductor devices.
The electronic installation can be mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD, DVD, navigation
Any electronic product such as instrument, camera, video camera, recording pen, MP3, MP4, PSP or equipment or any including described
The intermediate products of semiconductor devices.
Wherein, Fig. 3 shows the example of mobile phone.The outside of mobile phone 300 is provided with the display portion being included in shell 301
302nd, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
The inner member of the electronic installation includes the semiconductor devices described in exemplary embodiment two.The electronics dress
Put, due to having used the semiconductor devices, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that including：The Semiconductor substrate with PMOS areas is provided, on the semiconductor substrate formed with grid structure and positioned at the grid The side wall construction of pole structure both sides；Mask layer is formed on the semiconductor substrate, covers the grid structure and the side wall construction；The mask layer is patterned, to form mask side wall in the outside of the side wall construction；Embedded germanium silicon layer is formed in the Semiconductor substrate of the grid structure both sides in the PMOS areas exposed；Remove the mask side wall；The Semiconductor substrate is placed in rinse bath and got express developed, and rinse bath described in fast evacuation, effectively to remove The defects of being formed when forming the embedded germanium silicon in wafer.
- 2. according to the method for claim 1, it is characterised in that the Semiconductor substrate is placed in the rinse bath and carried out Get express developed and the duration of rinse bath described in fast evacuation is 5s-15s.
- 3. according to the method for claim 1, it is characterised in that the Semiconductor substrate is placed in the rinse bath and carried out Get express developed and after rinse bath described in fast evacuation, in addition to by the Semiconductor substrate immersion hydrogen peroxide and be dissolved in Step in the mixture that the ozone of ionized water is formed, the defect of residual is aoxidized, duration 30s-300s.
- 4. according to the method for claim 3, it is characterised in that implement overflow processing and remove the defect through peroxidating, Duration is 60s-300s.
- 5. according to the method for claim 1, it is characterised in that the mask layer include the cushion that is laminated from bottom to top and Stress material layer.
- 6. according to the method for claim 1, it is characterised in that at the top of the embedded germanium silicon layer formed with cap layers.
- 7. according to the method for claim 1, it is characterised in that removed using wet etching process of the phosphoric acid as corrosive liquid The mask side wall.
- A kind of 8. semiconductor devices that method using described in one of claim 1-7 manufactures.
- 9. a kind of electronic installation, it is characterised in that the electronic installation includes the semiconductor devices described in claim 8.
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| CN201610392070.5A CN107464741A (en) | 2016-06-03 | 2016-06-03 | A kind of semiconductor devices and its manufacture method, electronic installation |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994370A (en) * | 2019-03-04 | 2019-07-09 | 上海华力集成电路制造有限公司 | The method stained in the manufacturing method and removal nitride film of MOS transistor |
| CN110620084A (en) * | 2019-08-29 | 2019-12-27 | 上海华力微电子有限公司 | Method for forming semiconductor device |
| CN113764263A (en) * | 2020-06-01 | 2021-12-07 | 爱思开海力士有限公司 | Semiconductor device using hard mask and method of manufacturing the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431022A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Wafer grid curb wall removing method |
| KR20100026223A (en) * | 2008-08-29 | 2010-03-10 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| CN102842614A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US20130026557A1 (en) * | 2011-07-25 | 2013-01-31 | United Microelectronics Corp. | Sonos non-volatile memory cell and fabricating method thereof |
| CN103730420A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | CMOS transistor manufacturing method |
| CN103871968A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MOS (metal oxide semiconductor) transistor |
| CN104183491A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
-
2016
- 2016-06-03 CN CN201610392070.5A patent/CN107464741A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431022A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Wafer grid curb wall removing method |
| KR20100026223A (en) * | 2008-08-29 | 2010-03-10 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| CN102842614A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US20130026557A1 (en) * | 2011-07-25 | 2013-01-31 | United Microelectronics Corp. | Sonos non-volatile memory cell and fabricating method thereof |
| CN103730420A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | CMOS transistor manufacturing method |
| CN103871968A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MOS (metal oxide semiconductor) transistor |
| CN104183491A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994370A (en) * | 2019-03-04 | 2019-07-09 | 上海华力集成电路制造有限公司 | The method stained in the manufacturing method and removal nitride film of MOS transistor |
| CN110620084A (en) * | 2019-08-29 | 2019-12-27 | 上海华力微电子有限公司 | Method for forming semiconductor device |
| CN110620084B (en) * | 2019-08-29 | 2022-04-08 | 上海华力微电子有限公司 | Method for forming semiconductor device |
| CN113764263A (en) * | 2020-06-01 | 2021-12-07 | 爱思开海力士有限公司 | Semiconductor device using hard mask and method of manufacturing the same |
| US11823904B2 (en) | 2020-06-01 | 2023-11-21 | SK Hynix Inc. | Semiconductor device using hard mask and method for fabricating the same |
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