CN107180764A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN107180764A CN107180764A CN201610140142.7A CN201610140142A CN107180764A CN 107180764 A CN107180764 A CN 107180764A CN 201610140142 A CN201610140142 A CN 201610140142A CN 107180764 A CN107180764 A CN 107180764A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000009434 installation Methods 0.000 title claims abstract description 13
- 238000002347 injection Methods 0.000 claims abstract description 98
- 239000007924 injection Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 69
- 239000000463 material Substances 0.000 claims description 33
- -1 phosphonium ion Chemical class 0.000 claims description 20
- 239000000470 constituent Substances 0.000 claims description 13
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910001449 indium ion Inorganic materials 0.000 claims description 9
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 74
- 229910052751 metal Inorganic materials 0.000 description 23
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- 238000005229 chemical vapour deposition Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 14
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 10
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
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- 239000010703 silicon Substances 0.000 description 6
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
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- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 4
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- 239000000126 substance Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 3
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- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 3
- RWNKSTSCBHKHTB-UHFFFAOYSA-N Hexachloro-1,3-butadiene Chemical compound ClC(Cl)=C(Cl)C(Cl)=C(Cl)Cl RWNKSTSCBHKHTB-UHFFFAOYSA-N 0.000 description 2
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
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- 241000790917 Dioxys <bee> Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
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- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, electronic installation, and methods described includes：Semiconductor substrate is provided, implements source and drain and injects and anneal, to form source and drain injection region in the semiconductor substrate；The hard mask layer of patterning is formed on source and drain injection region, and etches the source and drain injection region do not covered by the hard mask layer, until exposing Semiconductor substrate；Side wall is formed on the side wall of the groove formed by the etching；Grid structure is formed, to be filled up completely with the remainder of the groove；Remove after side wall and hard mask layer, implement LDD injections, to form LDD injection regions in the Semiconductor substrate of grid structure both sides；Form contact etch stop layer, covering grid structure and Semiconductor substrate.According to the present invention, more shallow LDD injection zones can be obtained by implementing LDD injections, effectively to suppress short-channel effect；Bigger stress can be obtained in channel region simultaneously, so as to be obviously improved the performance of MOS device.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its
Manufacture method, electronic installation.
Background technology
With the continuous reduction of the characteristic size of MOS device, in its manufacturing process, for
The control of the channel length effective enough of MOS device becomes more challenging.Therefore,
Using the method that ultra-shallow junctions and abrupt junction are formed in MOS device, core devices can be improved
Short-channel effect.However, during ultra-shallow junctions and abrupt junction is formed, how to suppress
Finding more rational equilibrium point between short-channel effect and the performance for lifting MOS device is also
Extremely bear the task of challenge.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices,
Including：
Semiconductor substrate is provided, implements source and drain and injects and anneal, with the Semiconductor substrate
Form source and drain injection region；
The hard mask layer of patterning is formed on the source and drain injection region, and is etched not by described hard
The source and drain injection region of mask layer masking, until exposing the Semiconductor substrate；
Side wall is formed on the side wall of the groove formed by the etching；
Grid structure is formed, to be filled up completely with the remainder of the groove；
Remove after the side wall and the hard mask layer, implement LDD injections, with the grid
LDD injection regions are formed in the Semiconductor substrate of pole structure both sides.
In one example, the height of the grid structure is more than the depth of the groove.
In one example, the grid structure include the gate dielectric that is laminated from bottom to top and
Gate material layers.
In one example, the side wall is identical with the constituent material of the hard mask layer.
In one example, described remove is implemented using wet etching.
In one example, implement after the LDD injections, in addition to form contact etch
The step of stop-layer, the contact etch stop layer covers side wall and the institute of the grid structure
State Semiconductor substrate.
In one example, before implementing source and drain injection, in addition to implement well region injection with
The step of well region being formed in the Semiconductor substrate.
In one example, for NMOS, the Doped ions of the LDD injections are
Phosphonium ion or arsenic ion；For PMOS, the Doped ions of the LDD injections are
Boron ion or indium ion.
In one embodiment, the present invention also provides a kind of semiconductor of use above method manufacture
Device.
In one embodiment, the present invention also provides a kind of electronic installation, the electronic installation bag
Include the semiconductor devices.
According to the present invention, the height of the grid structure of formation is more than the depth of the groove formed, real
More shallow LDD injection zones can be obtained by applying LDD injections, thus relative to prior art energy
More shallow injection knot is obtained, effectively to suppress short-channel effect；It can be obtained in channel region simultaneously
Bigger stress, so as to be obviously improved the performance of MOS device.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is the device for being implemented to obtain after LDD injections and source and drain injection successively according to prior art
The schematic cross sectional view of part；
Fig. 2A-Fig. 2 G are the step implemented successively according to the method for exemplary embodiment of the present one
The schematic cross sectional view of the rapid device obtained respectively；
Fig. 3 is stream the step of implementation successively according to the method for exemplary embodiment of the present one
Cheng Tu；
Fig. 4 is the schematic diagram of the electronic installation according to exemplary embodiment of the present three.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
As shown in figure 1, it injects to implement LDD injections and source and drain successively according to prior art
The schematic cross sectional view of the device obtained afterwards.
Grid structure 110 is formed with a semiconductor substrate 100, as an example, grid structure
110 gate dielectric, gate material layers and grid hard masking layers including stacking gradually.Grid
Dielectric layer includes oxide skin(coating), such as silica (SiO2) layer.Gate material layers include many
Crystal silicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal
One or more in silicide layer, wherein, the constituent material of metal level can be tungsten (W),
Nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride (TiN) layer；Lead
Conductive metal oxide skin(coating) includes yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide
(TiSi) layer.Grid hard masking layer include oxide skin(coating), nitride layer, oxynitride layer and
One or more in amorphous carbon, wherein, the constituent material of oxide skin(coating) includes boron phosphorus silicon glass
Glass (BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass
Glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin coating electricity are situated between
Matter (SOD)；Nitride layer includes silicon nitride (Si3N4) layer；Oxynitride layer includes nitrogen oxygen
SiClx (SiON) layer.The shape of gate dielectric, gate material layers and grid hard masking layer
Any prior art that can be familiar with into method using those skilled in the art, preferably chemical gas
Phase sedimentation (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition
(PECVD).It is also formed with being located at the both sides of grid structure 110 and tight on a semiconductor substrate 100
By the side wall construction 111 of grid structure 110, wherein, side wall construction 111 is by oxide, nitrogen
Compound or combination are constituted.
LDD injection regions are formed with the Semiconductor substrate 100 of the both sides of grid structure 110
101.In the prior art, illustrated by taking MOS transistor as an example, with grid structure 110
For mask, LDD injections are implemented to Semiconductor substrate 100, to form LDD injection regions 101.
When MOS transistor is nmos pass transistor, the Doped ions of the LDD injections
Can be phosphonium ion or arsenic ion etc..
As an example, when the Doped ions that the LDD injects are phosphonium ion, ion implanting
Energy range be 1keV-20keV, the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
When the Doped ions that the LDD injects are arsenic ion, the energy range of ion implanting is 2
KeV-35keV, the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
When MOS transistor is PMOS transistor, the Doped ions of the LDD injections
Can be boron ion or indium ion etc..
As an example, when the Doped ions that the LDD injects are boron ion, ion implanting
Energy range be 0.5keV-10keV, the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
When the Doped ions that the LDD injects are indium ion, the energy range of ion implanting is 10
KeV-70keV, the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
Implement after LDD injection, in addition to Semiconductor substrate 100 is implemented bag-like region from
The step of son injection, LDD injection regions 101 are wrapped up with being formed in Semiconductor substrate 100
Bag-like region firmly.The depth of the bag-like region ion implanting is slightly larger than the depth that the LDD injects
Degree, and the ion and the ionic conduction type of LDD injections of the bag-like region ion implanting
Conversely.Under selected ion implantation angle, rotation injection is carried out, shadow effect can be reduced simultaneously
Symmetrical Impurity Distribution is formed, its ion implantation energy, dosage, angle and the low-mix heteroion
The corresponding matching of the energy of injection, dosage, angle, its Implantation Energy ensures the bag-like region to be formed
LDD injection regions 101 are wrapped, so that effectively restrain is reduced (DIBL) by drain induced barrier
Caused short-channel effect.
When MOS transistor is nmos pass transistor, the doping of the bag-like region ion implanting
Ion can be boron ion or indium ion etc..
As an example, when the Doped ions of the bag-like region ion implanting are boron ion, ion
The energy range of injection is 3keV-20keV, and the dosage of ion implanting is
1.0×e13-9.0×e13cm-2, the incident direction of ion implanting relative to the Semiconductor substrate
100 perpendicular directions offset certain angle, and the scope of the angle is 0 degree of -45 degree.
As an example, when the Doped ions of the bag-like region ion implanting are indium ion, ion
The energy range of injection is 100keV-150keV, and the dosage of ion implanting is
1.0×e13-9.0×e13cm-2, the incident direction of ion implanting relative to the Semiconductor substrate
100 perpendicular directions offset certain angle, and the scope of the angle is 0 degree of -45 degree.
When MOS transistor is PMOS transistor, the doping of the bag-like region ion implanting
Ion can be phosphonium ion or arsenic ion etc..
As an example, when the Doped ions of the bag-like region ion implanting are phosphonium ion, ion
The energy range of injection is 5keV-35keV, and the dosage of ion implanting is
1.0×e13-1.0×e14cm-2, the incident direction of ion implanting relative to the Semiconductor substrate
100 perpendicular directions offset certain angle, and the scope of the angle is 0 degree of -45 degree.
As an example, when the Doped ions of the bag-like region ion implanting are arsenic ion, ion
The energy range of injection is 10keV-50keV, and the dosage of ion implanting is
1.0×e13-1.0×e14cm-2, the incident direction of ion implanting relative to the Semiconductor substrate
100 perpendicular directions offset certain angle, and the scope of the angle is 0 degree of -45 degree.
Formed after side wall construction 111, in the Semiconductor substrate 100 in the outside of side wall construction 111
Form source and drain injection region 112.Then, annealing process is implemented, to activate injected ion simultaneously
Eliminate the defect produced by above-mentioned ion implanting.
With the continuous reduction of feature sizes of semiconductor devices, defined between source and drain injection region 112
The length of channel region constantly reduce, implement annealing process to activate during injected ion, institute
The diffusion effect of the ion of injection causes the generation of short-channel effect, causes the increase of junction leakage,
Cause the decline of device performance.
In order to improve the short-channel effect of core devices simultaneously while lifting the performance of MOS device,
Prior art employs a variety of methods, such as pre-amorphous ion implanting, stress technique, comes
Improve the short-channel effect of core devices and further lift the performance of MOS device.But,
In place of these methods come with some shortcomings, such as pre-amorphous ion implanting can not be controlled well
The doping form of the source/drain region of MOS device processed, stress technique is answered simply by offer is extra
Power lifts its carrier mobility in the channel region of MOS device.Above-mentioned weak point enters one
Step limit suppress short-channel effect and lifted MOS device performance between determine it is more excellent
The technological progress space of equilibrium point.
As shown in figure 3, the invention provides a kind of manufacture method of semiconductor devices, obtaining
Bigger stress can be obtained in channel region while with more shallow LDD injection zones.
The method, semi-conductor device manufacturing method includes：
In step 301 there is provided Semiconductor substrate, implement source and drain and inject and anneal, partly leading
Source and drain injection region is formed in body substrate；
In step 302, the hard mask layer of patterning is formed on source and drain injection region, and is etched
The source and drain injection region do not covered by hard mask layer, until exposing Semiconductor substrate；
In step 303, side wall is formed on the side wall of the groove formed by the etching；
In step 304, grid structure is formed, to be filled up completely with the remainder of groove；
In step 305, remove after side wall and hard mask layer, implement LDD injections, with
LDD injection regions are formed in the Semiconductor substrate of grid structure both sides；
Within step 306, contact etch stop layer, covering grid structure and semiconductor are formed
Substrate.
According to the manufacture method of semiconductor devices proposed by the present invention, the height of the grid structure of formation
Degree is more than the depth of the groove formed, and more shallow LDD injections can be obtained by implementing LDD injections
Region, thus more shallow injection knot can be obtained relative to prior art, effectively to suppress short channel
Effect；Bigger stress can be obtained in channel region simultaneously, so as to be obviously improved MOS device
Performance.
Below, semiconductor device proposed by the present invention is described in detail according to exemplary embodiment one
The manufacture method of part.
[exemplary embodiment one]
Reference picture 2A- Fig. 2 G, illustrated therein is according to an exemplary embodiment of the present one side
The schematic cross sectional view for the device that the step of method is implemented successively obtains respectively.
First, as shown in Figure 2 A there is provided Semiconductor substrate 200, as an example, semiconductor
The constituent material of substrate 200 can use undoped with monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI) etc..As an example, in the present embodiment, Semiconductor substrate
100 are constituted from single crystal silicon material.Isolation structure, institute are formed with Semiconductor substrate 200
State isolation structure and isolate (STI) structure or selective oxidation silicon (LOCOS) isolation for shallow trench
Structure, to put it more simply, the isolation structure not shown in diagram.
Next, implementing well region injection, well region is formed in Semiconductor substrate 200.For
For NMOS, the doping type of the well region is p-type；It is described for PMOS
The doping type of well region is N-type.
Next, implementing source and drain injection, source and drain injection region is formed in Semiconductor substrate 200
201.Due to subsequently needing that groove is first formed in source and drain injection region 201, then formed in the trench
Grid structure, therefore, the depth of source and drain injection region 201 should be less than the grid structure formed afterwards
Height.The grid structure formed due to after can be dummy gate structure, in follow-up void
Intend to be removed in grid-metal gate process, and then use the more preferable metal gate structure of performance
Substitute, therefore, the depth of source and drain injection region 201 is set below to the grid formed afterwards here
The height of pole structure, can make the contact etch stop layer being subsequently formed expose grid structure
Top while, the LDD notes protected the surface of the source and drain injection region and formed afterwards
Enter area.
Implement after source and drain injection, perform annealing process, to activate injected ion and repair note
Enter produced defect, the annealing process can move back for laser annealing, samming annealing, peak value
Fire etc..
Then, as shown in Figure 2 B, formed on source and drain injection region 201 with groove 203
The hard mask layer 202 of pattern.As an example, first depositing hard mask on semiconductor substrate 200
Layer 202, the preferred chemical vapour deposition technique (CVD) of deposition, such as low temperature chemical vapor deposition
(LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD),
Plasma enhanced chemical vapor deposition (PECVD) etc.；Again using spin coating, exposure, development etc.
Technique forms the photoresist layer of the pattern with groove 203 on hard mask layer 202；With described
Photoresist layer is mask, implements dry etching to form groove 203 in hard mask layer 202
Pattern；The photoresist layer is removed by cineration technics.
Next, being mask with the hard mask layer 202 of the pattern with groove 203, source is etched
Drain implant is until expose Semiconductor substrate 200.As an example, described be etched to plasma
Dry etching, etching gas include mixed gas or hexachlorobutadiene of hydrogen and oxygen etc..
Then, as shown in Figure 2 C, side wall 204 is formed on the side wall of groove 203.As
Example, first passes through the material that depositing operation formation constitutes side wall 204, covers hard mask layer 202
And the side wall of groove 203 and bottom, the preferred chemical vapour deposition technique of deposition, such as low temperature
Chemical vapor deposition, low-pressure chemical vapor deposition, fast thermal chemical vapor deposition, plasma increase
Extensive chemical vapour deposition etc.；Implement blanket type etching (blanket etch) again, complete side wall 204
Making；Finally, wet-cleaning is implemented, to remove etch residues and impurity.Side wall 204
Material it is identical preferably with the material of hard mask layer 202, can be so in follow-up process
Removed in the lump in same technique.
Then, as shown in Figure 2 D, formed grid structure, be filled up completely with groove 203 its
Remaining part point.
As an example, the grid structure includes the He of gate dielectric 205 being laminated from bottom to top
Gate material layers 206.The constituent material of gate dielectric 205 includes oxide, such as dioxy
SiClx (SiO2), can be using thermal oxide or chemical oxidation process formation gate dielectric 205.
The constituent material of gate material layers 206 include polysilicon, metal, conductive metal nitride,
One or more in conductive metal oxide and metal silicide, wherein, metal can be
Tungsten (W), nickel (Ni) or titanium (Ti), conductive metal nitride include titanium nitride (TiN),
Conductive metal oxide includes yttrium oxide (IrO2), metal silicide includes titanium silicide (TiSi),
Can be using selective epitaxial growth process formation gate material layers 206, the selective epitaxial
Growth technique can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), fast speed heat
One kind in chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).
Because the grid structure of the formation can be dummy gate structure, in follow-up virtual grid
It can be removed, and then be substituted using the more preferable metal gate structure of performance in-metal gate process,
Therefore, the formation height of grid structure is more than the depth of groove 203, i.e., more than being formed before
Source and drain injection region 201 depth, the contact etch stop layer that is subsequently formed can be made in dew
While going out the top of grid structure, protect the surface of source and drain injection region 201 and formed afterwards
LDD injection regions.
Then, as shown in Figure 2 E, side wall 204 and hard mask layer 202 are removed.As an example,
The removal is implemented by wet etching, in order to improve removal efficiency, side wall 204 is formed and hard
Constituent material both during mask layer 202 should be identical, for example, be all silicon nitride, work as side wall
204 and hard mask layer 202 constituent material be silicon nitride when, the corrosive liquid of the wet etching
For hot phosphoric acid.For the corrosive liquid of the wet etching, side wall 204 and hard mask layer
202 constituent material should have higher etching speed than the constituent material of gate dielectric 205
Rate, to avoid during side wall 204 and hard mask layer 202 is removed, to gate dielectric
205 cause unnecessary erosion.
Then, as shown in Figure 2 F, LDD injections are implemented, with the grid structure both sides
LDD injection regions 207 are formed in Semiconductor substrate 200.During LDD injections are implemented,
The top of source and drain injection region 201 can also be injected into Doped ions.
When MOS transistor is nmos pass transistor, the Doped ions of the LDD injections
Can be phosphonium ion or arsenic ion etc..As an example, when the LDD inject doping from
When son is phosphonium ion, the energy range of ion implanting is 1keV-20keV, the agent of ion implanting
Measure as 1.0 × e14-1.0×e15cm-2.When the Doped ions that the LDD injects are arsenic ion,
The energy range of ion implanting is 2keV-35keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2。
When MOS transistor is PMOS transistor, the Doped ions of the LDD injections
Can be boron ion or indium ion etc..As an example, when the LDD inject doping from
When son is boron ion, the energy range of ion implanting is 0.5keV-10keV, the agent of ion implanting
Measure as 1.0 × e14-1.0×e15cm-2.When the Doped ions that the LDD injects are indium ion,
The energy range of ion implanting is 10keV-70keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2。
Then, annealing process is implemented, to activate injected ion and eliminate above-mentioned ion implanting
Produced defect.
Because above-mentioned LDD injections have narrower injection window relative to prior art, therefore
More shallow LDD injection zones can be obtained, thus can obtain more shallow relative to prior art
Injection knot, effectively to suppress short-channel effect；Bigger stress can be obtained in channel region simultaneously,
So as to be obviously improved the performance of MOS device.
Then, as shown in Figure 2 G, contact etch stop layer 208 is formed, the grid are covered
Pole structure and Semiconductor substrate 200.As an example, forming contact etch by depositing operation
Stop-layer 208, the preferred chemical vapour deposition technique of deposition, such as low temperature chemical vapor deposition,
Low-pressure chemical vapor deposition, fast thermal chemical vapor deposition, plasma enhanced chemical vapor deposition
Material Deng, contact etch stop layer 208 can be SiCN, SiC, SiN etc..Then,
Cmp is performed, until exposing the grid structure.In follow-up process, for example
In possible grid structure removing step, contact etch stop layer 208 can protect source and drain to note
Enter the surface and LDD injection regions 207 in area 201.
So far, the technique step that according to an exemplary embodiment of the present one method is implemented is completed
Suddenly.In accordance with the invention it is possible to more shallow LDD injection zones are obtained, thus relative to existing
Technology can obtain more shallow injection knot, effectively to suppress short-channel effect；Simultaneously in channel region
Bigger stress can be obtained, so as to be obviously improved the performance of MOS device.
[exemplary embodiment two]
The processing step implemented first there is provided according to an exemplary embodiment of the present one method is obtained
The semiconductor devices obtained.
As shown in Figure 2 G, including：Semiconductor substrate 200, the composition of Semiconductor substrate 200
Material can use undoped with monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator
(SOI) etc., isolation structure and various traps (well) are formed with Semiconductor substrate 200
Structure, as an example, isolation structure, which is shallow trench, isolates (STI) structure or selective oxidation silicon
(LOCOS) isolation structure.
Grid structure on semiconductor substrate 200 is formed, as an example, the grid structure
Including the gate dielectric 205 being laminated from bottom to top and gate material layers 206, gate dielectric
205 constituent material includes oxide, such as silica (SiO2), thermal oxide can be used
Or chemical oxidation process formation gate dielectric 205, the constituent material of gate material layers 206
Including polysilicon, metal, conductive metal nitride, conductive metal oxide and metallic silicon
One or more in compound, wherein, metal can be tungsten (W), nickel (Ni) or titanium (Ti),
Conductive metal nitride includes titanium nitride (TiN), and conductive metal oxide includes yttrium oxide
(IrO2), metal silicide includes titanium silicide (TiSi), can use selective epitaxial growth
Technique formation gate material layers 206, the selective epitaxial growth process can use low pressure
Learn vapour deposition, plasma enhanced chemical vapor deposition, ultra-high vacuum CVD,
One kind in rapid thermal CVD and molecular beam epitaxy.
Form the source and drain injection region 201 in Semiconductor substrate 200, the He of source and drain injection region 201
In the bottom of the grid structure is generally aligned in the same plane；It is formed at the half of the grid structure both sides
LDD injection regions 207 in conductor substrate 200, when MOS transistor is NMOS crystal
The Doped ions of Guan Shi, the LDD injection can be phosphonium ion or arsenic ion etc., when
When MOS transistor is PMOS transistor, the Doped ions of the LDD injections can be
Boron ion or indium ion etc.；It is formed at the covering LDD injection regions of the grid structure both sides
207 and the contact etch stop layer 208 of source and drain injection region 201, contact etch stop layer
208 material can be SiCN, SiC, SiN etc..
In source and drain injection region 201 and the bottom of the grid structure are generally aligned in the same plane, implement
LDD injections can obtain more shallow LDD injection zones, thus can be obtained relative to prior art
More shallow injection knot is obtained, effectively to suppress short-channel effect；It can be obtained more in channel region simultaneously
Big stress, so as to be obviously improved the performance of MOS device.
Then, the making of whole semiconductor devices is completed by subsequent technique, including：Partly leading
Interlevel dielectric deposition on body substrate 200, the preferred chemical vapour deposition technique of deposition is such as low
Warm chemical vapor deposition, low-pressure chemical vapor deposition, fast thermal chemical vapor deposition, plasma
Strengthen chemical vapor deposition etc., the material of the interlayer dielectric layer can be common selected from this area
Various low k-value dielectric materials, including but not limited to k values are 2.5-2.9 silicate compound
(Hydrogen Silsesquioxane, referred to as HSQ), k values are 2.2 methane-siliconic acid salinization
Compound (Methyl Silsesquioxane, abbreviation MSQ), k values are 2.8 HOSPTM
(the low dielectric of the mixture based on organic matter and Si oxide of Honeywell companies manufacture is normal
Number materials) and k values for 2.65 SiLKTM(one kind of Dow Chemical companies manufacture
Advanced low-k materials) etc., generally constitute the interlayer dielectric using ultra low k dielectric materials
Layer, the ultra low k dielectric materials refer to the dielectric material that dielectric constant (k values) is less than 2.
Contact hole is formed in the interlayer dielectric layer, exposes source and drain injection region 201 and the grid
The top of pole structure；Contact plug is formed in the contact hole, and forming the method for contact plug can use
Any prior art that those skilled in the art are familiar with, preferably chemical vapour deposition technique are such as low
Warm chemical vapor deposition, low-pressure chemical vapor deposition, fast thermal chemical vapor deposition, plasma
Strengthen chemical vapor deposition etc.；Multiple interconnecting metal layers are formed, dual damascene work is generally used
Skill is completed；Form metal pad, wire bonding when being encapsulated for subsequent implementation device.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and it includes according to an exemplary embodiment of the present two
Semiconductor devices.The electronic installation can be mobile phone, tablet personal computer, notebook computer,
Net book, game machine, television set, VCD, DVD, navigator, camera, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment or any bag
Include the intermediate products of the semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with including outside
Display portion 402, operation button 403, external connection port 404 in shell 401, raise one's voice
Device 405, microphone 406 etc..
The inner member of the electronic installation includes the semiconductor device described in exemplary embodiment two
Part, the semiconductor devices has more shallow LDD injection zones, thus relative to existing skill
Art can obtain more shallow injection knot, effectively to suppress short-channel effect；Simultaneously in channel region energy
Bigger stress is obtained, so as to be obviously improved the performance of device.The electronic installation, due to
The semiconductor devices has been used, thus with better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that including：
Semiconductor substrate is provided, implements source and drain and injects and anneal, with the Semiconductor substrate
Form source and drain injection region；
The hard mask layer of patterning is formed on the source and drain injection region, and is etched not by described hard
The source and drain injection region of mask layer masking, until exposing the Semiconductor substrate；
Side wall is formed on the side wall of the groove formed by the etching；
Grid structure is formed, to be filled up completely with the remainder of the groove；
Remove after the side wall and the hard mask layer, implement LDD injections, with the grid
LDD injection regions are formed in the Semiconductor substrate of pole structure both sides.
2. according to the method described in claim 1, it is characterised in that the grid structure
Highly it is more than the depth of the groove.
3. method according to claim 2, it is characterised in that the grid structure bag
Include the gate dielectric being laminated from bottom to top and gate material layers.
4. according to the method described in claim 1, it is characterised in that the side wall and described
The constituent material of hard mask layer is identical.
5. according to the method described in claim 1, it is characterised in that real using wet etching
Apply the removal.
6. according to the method described in claim 1, it is characterised in that implement the LDD notes
After entering, in addition to the step of form contact etch stop layer, the contact etch stop layer
Cover the side wall and the Semiconductor substrate of the grid structure.
7. according to the method described in claim 1, it is characterised in that implement the source and drain note
Before entering, in addition to implement well region injection to form the step of well region in the Semiconductor substrate
Suddenly.
8. according to the method described in claim 1, it is characterised in that for NMOS,
The Doped ions of the LDD injections are phosphonium ion or arsenic ion；For PMOS,
The Doped ions of the LDD injections are boron ion or indium ion.
9. the semiconductor devices of the method manufacture described in a kind of one of use claim 1-8.
10. a kind of electronic installation, it is characterised in that the electronic installation includes claim 9
Described semiconductor devices.
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| CN111192849A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
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