CN101593775A - Mos field effect transistor - Google Patents
Mos field effect transistor Download PDFInfo
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- CN101593775A CN101593775A CNA2009100497954A CN200910049795A CN101593775A CN 101593775 A CN101593775 A CN 101593775A CN A2009100497954 A CNA2009100497954 A CN A2009100497954A CN 200910049795 A CN200910049795 A CN 200910049795A CN 101593775 A CN101593775 A CN 101593775A
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- curb wall
- semiconductor substrate
- effect transistor
- field effect
- grid curb
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- Electrodes Of Semiconductors (AREA)
Abstract
The present invention discloses a kind of mos field effect transistor, comprises Semiconductor substrate; Groove is formed in the described Semiconductor substrate; Grid curb wall is respectively formed on the sidewall of described groove; Gate dielectric is formed on the groove surfaces between the described grid curb wall; Grid is formed in the receiving space that described grid curb wall and gate dielectric surround; Lightly mixed drain area is respectively formed in the Semiconductor substrate of described grid curb wall below; Source area and drain region are respectively formed in the Semiconductor substrate of described grid curb wall both sides, and link to each other with the lightly mixed drain area of both sides.The present invention is by forming a groove earlier on Semiconductor substrate, form grid curb wall again and growth formation gate dielectric and grid between grid curb wall, break through the long restriction of minimum gate that lithographic equipment can be realized, dwindled the channel length that forms between source area and the drain region.
Description
Technical field
The present invention relates to a kind of semiconductor device, specifically, relate to a kind of mos field effect transistor.
Background technology
Along with the progress of semiconductor technology technology, cost is lower, power consumption is littler, speed faster semiconductor device become one of target of generally pursuing of semiconductor and electronic industry.In order to realize above-mentioned target, improve integrated level, dwindle cellar area, in the chip of same area, make more transistor, size of semiconductor device needs to carry out along with technical development constantly micro, and grid length becomes the shorter parasitic capacitance of reduction source leakage that needs simultaneously to improve the switching speed of device.Long in order to obtain shorter grid, usual way is the upgrading lithographic equipment.Mask aligner has become equipment the most expensive in the semiconductor manufacturing at present, and the price of the mask aligner of a 193nm is up to tens million of dollars.The upgrading lithographic equipment needs huge input.
In the mos field effect transistor, the parasitic capacitance of source, drain region can be divided into two parts: the parasitic capacitance of bottom and the parasitic capacitance of side.The parasitic capacitance of bottom is directly proportional with the area of source, drain region, and the parasitic capacitance of side is directly proportional with the girth and the degree of depth of source, drain region.For the parasitic capacitance of reduction source, drain region, present method is to use super shallow junction (ultra-shallow junction) technology to reduce the degree of depth of source, drain region.Yet this method need surpass shallow ion injection device and flash annealing (flash annealing) equipment, needs the input on the increase equipment equally.Simultaneously, because spiking (puncture) problem that exists when forming metal silicide, super shallow junction is very easy to run into the electric leakage problem that spiking causes.
Summary of the invention
The technical problem to be solved in the present invention is: a kind of mos field effect transistor is provided, breaks through the long restriction of minimum gate that lithographic equipment can be realized, reduce the parasitic capacitance of source area, drain region.
For solving the problems of the technologies described above, the invention provides a kind of mos field effect transistor, this mos field effect transistor comprises:
Semiconductor substrate;
Groove is formed in the described Semiconductor substrate;
Grid curb wall is respectively formed on the sidewall of described groove;
Gate dielectric is formed on the groove floor between the described grid curb wall;
Grid is formed in the receiving space that described grid curb wall and gate dielectric surround;
Lightly mixed drain area is respectively formed in the Semiconductor substrate of described grid curb wall below;
Source area and drain region are respectively formed at below the semiconductor substrate surface of described grid curb wall both sides, and link to each other with the lightly mixed drain area of both sides.
Further, also be formed with metal silicide on described source area, the drain region.
Further, described grid is N type or the P type polysilicon bar utmost point or metal gates.
Further, described gate dielectric is oxide, the nitrogen oxide of silicon, the HfO of silicon
2The perhaps dielectric layer of other high-ks.
Further, described grid curb wall is combination or other medium of oxide, nitride, oxide and nitride.
Further, described silicide is the silicide of titanium or cobalt or nickel, and preferably, the silicide of described cobalt is CoSi
2
Compare with traditional mos field effect transistor, the present invention is by forming a groove earlier on Semiconductor substrate, form grid curb wall again and growth formation gate dielectric and grid between grid curb wall, thereby broken through the long restriction of minimum gate that lithographic equipment can be realized, dwindled the channel length that forms between source area and the drain region.
And, this mos field effect transistor is by forming source area and drain region respectively below the semiconductor substrate surface of described grid curb wall both sides, make source area and drain region exceed channel plane, thereby when guaranteeing lower source-drain electrode series resistance, reduced the parasitic capacitance of source area and drain region, improved the performance of device.
Description of drawings
Fig. 1 is the structural representation of mos field effect transistor in the embodiment of the invention.
Embodiment
For clearer understanding technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
See also Fig. 1, Fig. 1 is the mos field effect transistor knot schematic diagram in the embodiment of the invention.At first on silicon chip as required dopant ion form P type or N type ion trap Semiconductor substrate 1, and on this Semiconductor substrate 1, dig fluted, and on the sidewall of described groove, forming grid curb wall (spacer) 6, described grid curb wall 6 can be for the composition of oxide, nitride or oxide and nitride, such as silicon dioxide (SiO
2), silicon nitride (SiN) or other media, as FSG (fluorinated silicate glass: the silex glass of doped with fluorine) etc.
Form gate dielectric 2 by deposit on the groove floor between the described grid curb wall 6, described gate dielectric 2 is the oxide of silicon, as silicon dioxide (SiO
2) nitrogen oxide of silicon, as silicon oxynitride, HfO
2The dielectric layer of (hafnium oxide) or other high-ks is as Al
2O
3, Si
3N
4, ZrO
2Deng all can.In the present embodiment, described gate dielectric 2 is the oxide silicon dioxide of silicon.
In the receiving space that described grid curb wall 6 and gate dielectric 2 surround, form grid 7, described grid 7 is N type or the P type polysilicon bar utmost point or metal gates, select corresponding type according to ion trap, source area 4 and drain region 5 types that described Semiconductor substrate 1 forms, such as being that P type ion trap, source area 4 and drain region 5 are during for the N type when Semiconductor substrate 1, grid 7 need be the N type, otherwise, when Semiconductor substrate 1 is a N type ion trap, when source area 4 and drain region 5 were the P type, grid 7 need be the P type.
As mentioned above, in the present embodiment, by on Semiconductor substrate 1, forming the groove of a broad earlier, and on the sidewall of this groove, form grid curb wall (spacer) 6, and in described grid curb wall 6, precipitation forms gate dielectric 2 and grid 7 on the groove floor, thereby realize reduction of gate length accordingly, overcome the lithographic accuracy restriction of lithographic equipment, greatly reduce the requirement of lithographic accuracy, this means that also the older lithographic equipment of use makes more advanced semiconductor, can postpone to use 0.09um processing procedure of future generation such as the lithographic equipment that is used to make the 0.13um processing procedure, thereby reduce the investment of equipment, save a large amount of costs.
Lightly mixed drain area (LDD) 3 is respectively formed in the Semiconductor substrate 1 of described grid curb wall 6 belows.The LDD structure can reduce the drain terminal maximum field of device effectively, has effectively suppressed hot carrier's effect, thereby can slow down the degeneration of device, prolongs the useful life of device.
In addition, in order to reduce the dead resistance of source area 4 and drain region 5, also deposit metal silicide (sillicide) 8 on described source area 4 and the drain region 5, described metal silicide is the silicide of Ti (titanium) or Co (cobalt) or Ni (nickel), forms silicide TiSi through the reaction back
2(titanium silicide) or CoSi
2(cobalt silicide) or NiSi (nickle silicide) are because CoSi
2Resistance characteristic lower, in the present embodiment, be preferably CoSi
2(cobalt silicide).
More than show and described basic principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (7)
1. a mos field effect transistor is characterized in that, comprising:
Semiconductor substrate;
Groove is formed in the described Semiconductor substrate;
Grid curb wall is respectively formed on the sidewall of described groove;
Gate dielectric is formed on the groove floor between the described grid curb wall;
Grid is formed in the receiving space that described grid curb wall and gate dielectric surround;
Lightly mixed drain area is respectively formed in the Semiconductor substrate of described grid curb wall below;
Source area and drain region are respectively formed at below the semiconductor substrate surface of described grid curb wall both sides, and link to each other with the lightly mixed drain area of both sides.
2. mos field effect transistor as claimed in claim 1 is characterized in that: described source area, drain region also are formed with metal silicide.
3. mos field effect transistor as claimed in claim 1 is characterized in that: described grid is N type or the P type polysilicon bar utmost point or metal gates.
4. mos field effect transistor as claimed in claim 1 is characterized in that: described gate dielectric is oxide, the nitrogen oxide of silicon, the HfO of silicon
2The perhaps dielectric layer of other high-ks.
5. mos field effect transistor as claimed in claim 1 is characterized in that: described grid curb wall is combination or other medium of oxide, nitride, oxide and nitride.
6. mos field effect transistor as claimed in claim 2 is characterized in that: described metal silicide is the silicide of titanium or cobalt or nickel.
7. mos field effect transistor as claimed in claim 6 is characterized in that: the silicide of described cobalt is CoSi
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100497954A CN101593775A (en) | 2009-04-22 | 2009-04-22 | Mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100497954A CN101593775A (en) | 2009-04-22 | 2009-04-22 | Mos field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101593775A true CN101593775A (en) | 2009-12-02 |
Family
ID=41408330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2009100497954A Pending CN101593775A (en) | 2009-04-22 | 2009-04-22 | Mos field effect transistor |
Country Status (1)
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|---|---|
| CN (1) | CN101593775A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107180764A (en) * | 2016-03-11 | 2017-09-19 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN109616447A (en) * | 2018-12-13 | 2019-04-12 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor devices and its manufacturing method |
-
2009
- 2009-04-22 CN CNA2009100497954A patent/CN101593775A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107180764A (en) * | 2016-03-11 | 2017-09-19 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN107180764B (en) * | 2016-03-11 | 2020-09-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN109616447A (en) * | 2018-12-13 | 2019-04-12 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor devices and its manufacturing method |
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Application publication date: 20091202 |