CN103560153B - A kind of tunneling field-effect transistor and preparation method thereof - Google Patents
A kind of tunneling field-effect transistor and preparation method thereof Download PDFInfo
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- 230000005641 tunneling Effects 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 83
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 83
- 239000010703 silicon Substances 0.000 claims abstract description 83
- 230000005669 field effect Effects 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 13
- 238000005457 optimization Methods 0.000 description 8
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- 230000008901 benefit Effects 0.000 description 4
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- 238000006731 degradation reaction Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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Abstract
The present invention provides a kind of tunneling field-effect transistor and preparation method thereof, and described preparation method at least includes step: provides a SOI substrate with top layer silicon, oxygen buried layer and bottom silicon, carries out ion implanting in described top layer silicon both sides and form source electrode and drain electrode respectively；Intrinsic silicon layer, gate dielectric layer and grid layer is sequentially formed from bottom to top on described SOI substrate surface；Utilizing photoetching and lithographic technique to etch described intrinsic silicon layer, gate dielectric layer and grid layer and form stacked structure, described stacked structure overlaps with described source electrode portion and described drain electrode has a predeterminable range in the horizontal direction.The present invention utilizes the overlapping of described stacked structure and source electrode, it is possible to increases tunnelling area, and then increases large-drive-current；It addition, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, the bipolar electrode effect in tunneling field-effect transistor can be suppressed by this predeterminable range, reduce sub-threshold current.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of tunneling field-effect transistor and preparation method thereof.
Background technology
In recent years, obtaining rapid development with the microelectric technique that silicon integrated circuit is core, Moore's Law is substantially followed in the development of IC chip, and namely semiconductor chip integrated level is with every speed increment doubled for 18 months.In the past period, the progress of microelectric technique is based on the cost benefit to continue to optimize material, technique and flow process.But, along with the development of microelectric technique, conventional silicon-based CMOS transistors is scaled has become more and more difficult.And, utilize the MOSFET most of electronic products manufactured now, following subject matter occur: first, cause that electric leakage becomes big owing to MOSFET channel shortens, though shutdown or standby in also can continuous power consumption.IBM quotes the report of European Union and points out, the family of 10% and office's electric power are all the holding states being wasted in electronic product.Second, conventional MOS FET is by the restriction of physical mechanism, and its subthreshold swing is higher.
One of scheme solving problem above adopts tunneling field-effect transistor (TunnelFET:TFET) structure exactly, tunneling field-effect transistor (TFET) is a kind of Novel work mechanism device, short-channel effect can be suppressed, effectively reducing leakage current, therefore it has the advantage of low speed paper tape reader static power disspation.Its subthreshold slope can break the restriction (for 60mV/dec under room temperature) of KT/q simultaneously, and this is conducive to working at low supply voltages.But, tunneling effect transistor (TFET) is faced with the problem that the galvanic areas driving the little and low subthreshold slope of electric current is little.At present, in field, propose various prioritization schemes, including thinning gate oxide thickness, adopt high K grid material, employing double-gate structure etc.；Also include using non-silicon material, such as the other materials such as Ge of small gap material, the III-V material of Broken-gap structure etc..And when thinning gate oxide thickness or use hafnium, or when using low-gap semiconductor, bipolar electrode effect (ambipolarbehavior) is also resulted in obvious while improving device performance, bipolar leakage current (ambipolarleakage) is increased, showing as sub-threshold current to increase, this will make the performance degradation of device.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of tunneling field-effect transistor and preparation method thereof, for solving in prior art the problem that common tunneling field-effect crystal-driven electric current is low, have bipolar electrode effect.
For achieving the above object and other relevant purposes, the present invention provides a kind of tunneling field-effect transistor and preparation method thereof, and the preparation method of described tunneling field-effect transistor at least includes step:
1) SOI substrate with top layer silicon, oxygen buried layer and bottom silicon is provided, carries out ion implanting in described top layer silicon both sides and form source electrode and drain electrode respectively；
2) intrinsic silicon layer, gate dielectric layer and grid layer are sequentially formed from bottom to top on described SOI substrate surface；
3) photoetching and lithographic technique is utilized to etch described intrinsic silicon layer, gate dielectric layer and grid layer, being formed by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface is constituted, described stacked structure overlaps with described source electrode portion and described drain electrode has a predeterminable range in the horizontal direction.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, the size range of described predeterminable range is 1/4Lg～Lg, and wherein, Lg is grid length.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described source electrode is P type heavily-doped semiconductor, and described drain electrode is N-type heavily-doped semiconductor.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described source electrode is N-type heavily-doped semiconductor, and described drain electrode is P type heavily-doped semiconductor.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, chemical vapor deposition method is adopted to sequentially form intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top on described SOI substrate surface.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described oxygen buried layer is SiO2；Described gate dielectric layer is HfO2Or SiO2。
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described grid is metal gates, monocrystal silicon or polysilicon.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described grid is TiN.
The present invention also provides for a kind of tunneling field-effect transistor, and described tunneling field-effect pipe at least includes:
SOI substrate, described SOI substrate includes top layer silicon, oxygen buried layer and bottom silicon；
Source electrode and drain electrode, be respectively formed in described top layer silicon both sides；
Stacked structure, is formed in described SOI substrate, and described stacked structure includes intrinsic silicon, is positioned at the gate medium on described intrinsic silicon surface and is positioned at the grid on described gate medium surface；Described stacked structure overlaps with described source electrode portion and described drain electrode has a predeterminable range in the horizontal direction.
As the structure of a kind of optimization of tunneling field-effect transistor of the present invention, the size range of described predeterminable range is 1/4Lg～Lg, and wherein, Lg is grid length.
As mentioned above, tunneling field-effect transistor of the present invention and preparation method thereof, have the advantages that and the stacked structure including intrinsic silicon, gate medium and grid is formed in described SOI substrate, make the overlapping of described stacked structure and described source electrode, utilize the overlapping of described stacked structure and source electrode, tunnelling area can be increased, and then increase large-drive-current；It addition, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, the bipolar electrode effect in tunneling field-effect transistor can be suppressed by this predeterminable range, reduce sub-threshold current.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of tunneling field-effect transistor preparation method of the present invention.
Fig. 2～Fig. 3 is the structural representation that the step 1) of tunneling field-effect transistor preparation method of the present invention presents.
Fig. 4 is the step 2 of tunneling field-effect transistor preparation method of the present invention) structural representation that presents.
Fig. 5 is the structural representation that the step 3) of tunneling field-effect transistor preparation method of the present invention presents.
Element numbers explanation
S1～S3 step
1SOI substrate
11 top layer silicon
12 oxygen buried layers
13 bottom silicon
2 drain electrodes
3 source electrodes
4 top layer intrinsic silicons
5 intrinsic silicon layer
6 gate dielectric layers
7 grid layers
8 intrinsic silicons
9 gate mediums
10 grids
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art the content disclosed by this specification can understand other advantages and effect of the present invention easily.The present invention can also be carried out by additionally different detailed description of the invention or apply, and the every details in this specification based on different viewpoints and application, can also carry out various modification or change under the spirit without departing from the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates the basic conception of the present invention in a schematic way, then assembly that in graphic, only display is relevant with the present invention but not component count when implementing according to reality, shape and size drafting, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
Embodiment one
The preparation method that the present invention provides a kind of tunneling field-effect transistor, preparation method flow chart as shown in Figure 1, the preparation method of described tunneling field-effect transistor at least comprises the following steps:
S1, it is provided that one has the SOI substrate of top layer silicon, oxygen buried layer and bottom silicon, carries out ion implanting in described top layer silicon both sides and forms source electrode and drain electrode respectively；
S2, sequentially forms intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top on described SOI substrate surface；
S3, photoetching and lithographic technique is utilized to etch described intrinsic silicon layer, gate dielectric layer and grid layer, being formed by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface is constituted, described stacked structure overlaps with described source electrode portion and described drain electrode has a predeterminable range in the horizontal direction.
Below in conjunction with the preparation method that accompanying drawing specifically describes tunneling field-effect transistor provided by the invention.
Step S1 is first carried out, it is provided that one has the SOI substrate of top layer silicon, oxygen buried layer and bottom silicon, carries out ion implanting in described top layer silicon both sides and forms source electrode and drain electrode respectively.
Refer to Fig. 1, it is provided that SOI substrate 1 in, be followed successively by bottom silicon 13, oxygen buried layer 12 and top layer silicon 11 from bottom to top.Described oxygen buried layer 12 includes but not limited to as silicon dioxide.
As a preferred version of the embodiment of the present invention, the optional 20～30nm of thickness of described top layer silicon 11, described oxygen buried layer 12 thickness is 50nm～100nm, and the thickness of described bottom silicon 13 is 60nm～150nm.In the present embodiment, the thickness of described top layer silicon 11 elects 30nm temporarily as, the thickness of described oxygen buried layer 12 elects 100 nanometers temporarily as, the thickness of described bottom silicon 13 elects 150nm temporarily as, but it is not limited to this, also can be other thickness in other embodiments, for instance thickness desirable 20nm, 22nm, 25nm or 28nm etc. of top layer silicon 11, thickness desirable 50nm, 70nm, 80nm or 90nm etc. of oxygen buried layer 12, thickness desirable 60nm, 80nm, 100nm, 120nm or 140nm etc. of described bottom silicon 13.
Refer to Fig. 2, adopt ion implantation technology to carry out heavy doping in the both sides of described top layer silicon 11 to form source electrode 3 and drain electrode 2.Wherein, if the source electrode 3 that doping is formed is P type heavily-doped semiconductor, then the drain electrode 2 of opposite side is then N-type heavily-doped semiconductor；If the source electrode 3 that doping is formed is N-type heavily-doped semiconductor, then the drain electrode 2 of opposite side is then P type heavily-doped semiconductor.In the present embodiment for source electrode 3 be P type heavily-doped semiconductor, drain electrode 2 be N-type heavily-doped semiconductor, refer to accompanying drawing 3.In described source electrode 3, P type dopant ion is boron, and doping content is 1E16cm-3～1E20cm-3, but it is not limited to this, in other embodiments, also can be selected for other P type dopant ion.In described drain electrode 2, n-type doping ion is phosphorus or arsenic, and doping content is 1E16cm-3～1E20cm-3, but it is not limited to this, in other embodiments, also can be selected for other n-type doping ion.
After carrying out ion implanting, it is necessary to be annealed SOI substrate 1 processing, damage during to reduce ion implanting, lattice caused.The temperature being annealed processing is 900～1100 DEG C.
After described top layer silicon 11 carries out both sides doping, residue mid portion is top layer intrinsic silicon 4, is used as the raceway groove that between source electrode 3 and drain electrode 2, carrier passes through.
Then perform step S2, sequentially form intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top on described SOI substrate surface.
Refer to Fig. 4, described SOI substrate 1 adopts chemical vapour deposition technique grow intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7 successively.Certainly, it is possible to adopt the techniques such as molecular beam epitaxy to form described intrinsic silicon layer 5.Form gate dielectric layer 6 and grid layer 7 can also be other techniques being suitable for.
Optional 10～the 20nm of thickness of the intrinsic silicon layer 5 formed, the thickness of described gate dielectric layer 6 is 25nm～40nm, and the thickness of described grid layer 7 is 60nm～150nm.In the present embodiment, the thickness of the intrinsic silicon layer 5 of formation is 20nm, and the thickness of described gate dielectric layer is 40nm, and the thickness of described grid layer 7 is 150nm.
Finally perform step S3, photoetching and lithographic technique is utilized to etch described intrinsic silicon layer, gate dielectric layer and grid layer, being formed by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface is constituted, described stacked structure overlaps with described source electrode portion and described drain electrode has a predeterminable range in the horizontal direction.
All sides part of described intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7 is etched away according to predetermined width, specifically, dry method or wet etching method can be adopted to etch away all sides part of described intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7, to form the stacked structure being made up of described intrinsic silicon 8, gate medium 9 and grid 10 on described top layer silicon 11 surface, as shown in Figure 5.More specifically, in the present embodiment, etching described intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7 with wet-etching technology.Process is: first described grid layer 7 surface spin coating photoresist layer (diagram), and graphical photoresist layer forms opening, then the intrinsic silicon layer 5 below opening, gate dielectric layer 6 and grid layer 7 are carried out wet etching, thus forming described stacked structure.
Wherein, described gate dielectric layer 6 is HfO2Or SiO2, but it is not limited to this.
Described grid 10 can be metal gates, monocrystal silicon or polysilicon, and in the present embodiment, described grid 10 is metal gates.Further, described grid is TiN.
Described intrinsic silicon 8 and aforementioned top layer intrinsic silicon 4 are together as the raceway groove of carrier circulation between source electrode 3 and drain electrode 2.
The stacked structure formed is as it is shown in figure 5, described stacked structure overlaps with described source electrode 3 part and described drain electrode 2 has a predeterminable range in the horizontal direction, and this horizontal direction refers to the X-direction in Fig. 5.In the X direction, the crossover region of described stacked structure and source electrode 3 is of a size of D1, and described stacked structure and described drain electrode 2 have a predeterminable range D2.Described crossover region is of a size of 0 < D1≤1/2Lg；Described predeterminable range D2 ranges for 1/4Lg～Lg, and wherein, Lg is grid 10 length in X direction.
Overlapping owing to existing between source electrode 3 and stacked structure, therefore can increase the area of tunnelling, make the driving electric current of device be improved.
The bipolar electrode effect of tunneling field-effect transistor is owing to also can produce band-to-band-tunneling (band-to-bandtunneling) electric current at drain terminal knot place so that subthreshold leakage current increases, the performance degradation of transistor.Due to the fact that between described stacked structure and described drain electrode 2, there is a predeterminable range, it is possible to suppress bipolar electrode effect, it is prevented that drain terminal produces tunnelling current, makes subthreshold leakage current reduce, improve device overall performance.
It should be noted that, after forming source electrode 3, drain electrode 2 and grid 10, insulating barrier (diagram) is formed at SOI substrate surface deposition earth silicon material, then mask exposure etching insulating layer, on described source electrode 3, drain electrode 2 and grid 10, form source electrode through hole, drain electrode through hole and gate via (diagram) respectively, also need to fill through hole with metallic aluminum material afterwards and form interconnection wiring.
Embodiment two
The present invention also provides for a kind of tunneling field-effect transistor, makes by the described preparation method of a kind of offer of embodiment, and described tunneling field-effect transistor at least includes:
SOI substrate 1, described SOI substrate 1 includes top layer silicon 11, oxygen buried layer 12 and bottom silicon 13；
Source electrode 3 and drain electrode 2, be respectively formed in described top layer silicon 11 both sides；
Stacked structure, is formed in described SOI substrate 1, and described stacked structure includes intrinsic silicon 8, is positioned at the gate medium 9 on described intrinsic silicon 8 surface and is positioned at the grid 10 on described gate medium 9 surface；Described stacked structure overlaps with described source electrode 3 part and described drain electrode 2 has a predeterminable range in the horizontal direction.
The stacked structure formed is as it is shown in figure 5, described stacked structure overlaps with described source electrode 3 part and described drain electrode 2 has a predeterminable range in the horizontal direction, and this horizontal direction refers to X-direction in Fig. 5.In this X-direction, the crossover region of described stacked structure and source electrode 3 is of a size of D1, and described stacked structure and described drain electrode 2 have a predeterminable range D2.Described crossover region is of a size of 0 < D1≤1/2Lg；Described predeterminable range D2 ranges for 1/4Lg～Lg, and wherein, Lg is grid 10 length in X direction.
Overlapping owing to existing between source electrode 3 and stacked structure, therefore can increase the area of tunnelling, make the driving electric current of device be improved.
The bipolar electrode effect of tunneling field-effect transistor is owing to also can produce band-to-band-tunneling (band-to-bandtunneling) electric current at drain terminal knot place so that subthreshold leakage current increases, the performance degradation of transistor.Due to the fact that between described stacked structure and described drain electrode 2, there is a predeterminable range, it is possible to suppress bipolar electrode effect, it is prevented that drain terminal produces tunnelling current, makes subthreshold leakage current reduce, improve device overall performance.
In sum, the present invention provides a kind of tunneling field-effect transistor and preparation method thereof, the stacked structure including intrinsic silicon, gate medium and grid is formed in described SOI substrate, make the overlapping of described stacked structure and described source electrode, utilize the overlapping of described stacked structure and source electrode, increase tunnelling area, and then increase large-drive-current；It addition, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, the bipolar electrode effect in tunneling field-effect transistor can be suppressed by this predeterminable range, reduce sub-threshold current.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment is illustrative principles of the invention and effect thereof only, not for the restriction present invention.Above-described embodiment all under the spirit and category of the present invention, can be modified or change by any those skilled in the art.Therefore, art has usually intellectual such as modifying without departing from all equivalences completed under disclosed spirit and technological thought or change, must be contained by the claim of the present invention.
Claims (7)
1. the preparation method of a tunneling field-effect transistor, it is characterised in that the preparation method of described tunneling field-effect transistor at least includes step:
A) one SOI substrate with top layer silicon, oxygen buried layer and bottom silicon is provided, carries out ion implanting in described top layer silicon both sides and form source electrode and drain electrode respectively；
B) intrinsic silicon layer, gate dielectric layer and grid layer are sequentially formed from bottom to top on described SOI substrate surface；
C) photoetching and lithographic technique is utilized to etch described intrinsic silicon layer, gate dielectric layer and grid layer, formed by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface is constituted, described stacked structure and described source electrode have a crossover region in the horizontal direction, the size range of described crossover region is more than 0Lg and less than or equal to 1/2Lg, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, the size range of described predeterminable range is 1/4Lg～Lg, wherein, Lg is grid length.
2. the preparation method of tunneling field-effect transistor according to claim 1, it is characterised in that: described source electrode is P type heavily-doped semiconductor, and described drain electrode is N-type heavily-doped semiconductor.
3. the preparation method of tunneling field-effect transistor according to claim 1, it is characterised in that: described source electrode is N-type heavily-doped semiconductor, and described drain electrode is P type heavily-doped semiconductor.
4. the preparation method of tunneling field-effect transistor according to claim 1, it is characterised in that: adopt chemical vapor deposition method to sequentially form intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top on described SOI substrate surface.
5. the preparation method of tunneling field-effect transistor according to claim 1, it is characterised in that: described oxygen buried layer is SiO2；Described gate dielectric layer is HfO2Or SiO2。
6. the preparation method of tunneling field-effect transistor according to claim 1, it is characterised in that: described grid is metal gates, monocrystal silicon or polysilicon.
7. a tunneling field-effect transistor, it is characterised in that described tunneling field-effect pipe at least includes:
SOI substrate, described SOI substrate includes top layer silicon, oxygen buried layer and bottom silicon；
Source electrode and drain electrode, be respectively formed in described top layer silicon both sides；
Stacked structure, is formed in described SOI substrate, and described stacked structure includes intrinsic silicon, is positioned at the gate medium on described intrinsic silicon surface and is positioned at the grid on described gate medium surface；Described stacked structure and described source electrode have a crossover region in the horizontal direction, the size range of described crossover region is more than 0Lg and less than or equal to 1/2Lg, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, the size range of described predeterminable range is 1/4Lg～Lg, wherein, Lg is grid length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310574824.5A CN103560153B (en) | 2013-11-15 | 2013-11-15 | A kind of tunneling field-effect transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310574824.5A CN103560153B (en) | 2013-11-15 | 2013-11-15 | A kind of tunneling field-effect transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103560153A CN103560153A (en) | 2014-02-05 |
| CN103560153B true CN103560153B (en) | 2016-07-13 |
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| CN108447902A (en) * | 2018-01-19 | 2018-08-24 | 西安电子科技大学 | It can inhibit the tunneling field-effect transistor and preparation method of dipolar effect |
| CN109065615B (en) * | 2018-06-12 | 2021-05-07 | 西安电子科技大学 | Novel planar InAs/Si heterogeneous tunneling field effect transistor and preparation method thereof |
| CN110729355B (en) * | 2019-10-23 | 2021-04-27 | 电子科技大学 | Longitudinal tunneling field effect transistor for improving sub-threshold swing amplitude |
| CN111564498A (en) * | 2020-05-13 | 2020-08-21 | 北京大学 | Self-aligned preparation method of drain-terminal negative overlap region of tunneling transistor |
| CN112002760B (en) * | 2020-08-28 | 2023-05-23 | 河南师范大学 | MnBi-based alloy 2 Te 4 Single layer nanoscale field effect transistor |
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