CN102194884B - Field effect transistor of hybrid conduction mechanism - Google Patents
Field effect transistor of hybrid conduction mechanism Download PDFInfo
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- CN102194884B CN102194884B CN 201110105079 CN201110105079A CN102194884B CN 102194884 B CN102194884 B CN 102194884B CN 201110105079 CN201110105079 CN 201110105079 CN 201110105079 A CN201110105079 A CN 201110105079A CN 102194884 B CN102194884 B CN 102194884B
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Abstract
The invention discloses a field effect transistor with a hybrid conduction mechanism, belonging to the field of field effect transistor logic devices in CMOS (Complementary Metal-Oxide-Semiconductor) ultra-large-scale integration (ULSI) circuits. The field effect transistor of the hybrid conduction mechanism comprises a source electrode, a drain electrode, a channel region and a control grid, wherein the source electrode comprises a tunneling source electrode and a diffusion source electrode. For an N-type device, a source region comprises a P-type tunneling source electrode which is shallower in junction depth and an N-type diffusion source electrode which is deeper in junction depth. For a P-type device, a source region comprises an N-type shallow tunneling source electrode and a P-type deep diffusion source electrode. The tunneling source electrode and the diffusion source electrode are subjected to potential lead-out on the source electrode at the same time; the doping type of the drain electrode is same as that of the diffusion source electrode at the source end, and the doping type of a substrate is same as that of the tunneling source electrode. Compared with the traditional TFET (Tunneling Field Effect Transistor), the field effect transistor disclosed by the invention can be used for effectively increasing the conduction current of a device and improving the driving capability of the device.
Description
Technical field
The invention belongs to field-effect transistor logical device field in the cmos vlsi (ULSI), be specifically related to a kind of field-effect transistor that mixes conducting mechanism.
Background technology
Since the first in the world piece integrated circuit is born, integrated circuit technique develops along the track of " mole rule " always between more than 50 year, the integrated level of memory was just doubled in per 18 months, the integrated level of CPU every two years doubles, along with the growth of integrated circuit integrated level, the power density of chip internal is also more and more higher.The invention of low energy-consumption electronic device has become the focus that everybody pays close attention to design.The actuating force of following IC industry and scientific development is to reduce power consumption, is not technology node to improve integrated level, and is scale to improve performance power consumption ratio.Conventional MOS FET, because be subjected to the restriction of thermoelectric potential, the sub-threshold slope theoretical limit is 60mV/dec.Along with dwindling of device size, the device turn-off capacity is also descending, and causes that quiescent dissipation increases.TFET (Tunneling FET) can be with the position by gate electrode control raceway groove, promotes the electron tunneling of source end valence band to the conduction band (perhaps raceway groove valence band electron tunneling is to source end conduction band) of raceway groove.The charge carrier generation mechanism of this MOSFET of being different from has overcome the restriction of source end charge carrier fermi-distribution to the subthreshold value characteristic, can further reduce the device sub-threshold slope, reduces the device static leakage current and then reduces the device quiescent dissipation.But for TFET, grid mainly concentrate on device surface to the control of groove potential, and the thickness of the high electric field region of grid-control is limited, thus the device tunnelling when taking place the cross-sectional area of electric current very limited, the current driving ability deficiency that causes TFET only is the one thousandth of MOSFET.Therefore the conducting electric current that improves TFET is a very urgent problem.
Summary of the invention
The object of the present invention is to provide a kind of field-effect transistor (break-through TFET) that mixes conducting mechanism.This device has low subthreshold current, and steep sub-threshold slope has possessed advantages such as high conducting electric current simultaneously.
Mixing conducting mechanism field-effect transistor provided by the invention, as shown in Figure 1.This field-effect transistor comprises source electrode, drain electrode, and channel region and control gate, wherein source electrode comprises two parts of tunnelling source electrode and diffusion source electrode.Wherein for the N-type device, source electrode comprises the tunnelling source electrode (junction depth is more shallow) of P type, and the diffusion source electrode (junction depth is darker) of N-type.And for P type device, source electrode comprises the diffusion source electrode (junction depth is darker) of N-type tunnelling source electrode (junction depth is more shallow) and P moldeed depth.The tunnelling source electrode all carries out current potential at the source electrode simultaneously with the diffusion source electrode and draws.The doping type of drain electrode is identical with diffusion source electrode doping type, and the doping type of substrate is identical with tunnelling source dopant type.
The junction depth of described tunnelling source electrode is a key parameter, and shallow excessively junction depth causes device to shift to an earlier date break-through easily, and leakage current increases, and it is big that sub-threshold slope becomes.Cross dark junction depth and hinder the generation of break-through easily, can not improve the conducting electric current of device.Simultaneously the optimal value of junction depth also is related with the doping of raceway groove and substrate, and generally optimal value is between 10 nanometers-1 micron.
The doping content of described substrate also is a key parameter, and low excessively doping content causes device to shift to an earlier date break-through easily, and leakage current increases, and it is big that sub-threshold slope becomes.Too high doping content hinders the generation of break-through easily, can not improve the conducting electric current of device.General value is at 1E14cm
-3-1E17cm
-3Between.
Described channel region can be taked the mode of vertical two districts doping or the doping way of multi-region, the gate voltage in the time of can regulating the startup of break-through mechanism so more neatly.
What field-effect transistor of the present invention was emphasized is a kind of mixing conducting mechanism, can be applied to silicon-based semiconductor material, also can be applied to other semi-conducting materials.
Technique effect of the present invention (be example with the N-type device):
1, along with the increase of gate voltage, the channel surface electromotive force increases, and between P type tunnelling source electrode and the raceway groove band-to-band-tunneling takes place at first, for device provides electric current.
2, along with gate voltage continues to increase, raceway groove continues expansion downwards near the depletion layer of source end.Arrive to a certain degree when gate voltage is big, the depletion region edge can expand to the knot edge of break-through source electrode, impels punchthrough current to begin conducting.Device is operated in the mode of operation that tunnelling current mixes with punchthrough current then.
Compare with existing TFET, break-through TFET can improve the conducting electric current of device effectively, improves the driving force of device.
Description of drawings
Fig. 1 is the structural representation of the field-effect transistor (break-through TFET) of the present invention's mixing conducting mechanism.
Fig. 2 is the main technique step of preparation the present invention's mixing conducting mechanism field-effect transistor (break-through TFET).Wherein Fig. 2 a is for growth oxide layer, deposit polysilicon and the semiconductor chip after coating photoresist, Fig. 2 b is the technical process of injection source end shallow junction, Fig. 2 c is that photolithographic source is leaked injection window technical process, the process of the full sheet deposit of Fig. 2 d silicon dioxide, Fig. 2 e is the process that full sheet etching silicon dioxide forms side wall, and Fig. 2 f is the field-effect transistor that the mixing conducting mechanism after being completed into is leaked in the source.
Among the figure, 1---polysilicon; 2 silica; 3---the tunnelling source electrode; 4---the diffusion source electrode; 5---Semiconductor substrate; 6---drain electrode; 7---photoresist; 8---tunnelling source electrode impurity; 9---diffusion source electrode and drain junction implanted dopant.
Embodiment
Below in conjunction with accompanying drawing, be described further by the implementation method of specific embodiment to break-through TFET of the present invention
Specifically implementation step is as shown in Figure 2:
1, at substrate 5 growth gate oxides 2, between 3nm-5nm, the deposit polysilicon 3 then greatly for desired quantity, and resist coating 7 is shown in Fig. 2 a.
2, make the tunnelling source electrode by lithography and inject window, inject the tunnelling required impurity 8 of source electrode shallow junction (adopting low-yield injection), shown in Fig. 2 b.
3, remove photoresist, smear photoresist then, make diffusion source electrode and drain electrode injection window by lithography, follow etch polysilicon 2, shown in Fig. 2 c.
4, remove photoresist, deposit silicon dioxide 7 is shown in Fig. 2 d.
5, full sheet etching silicon dioxide 7 forms side wall, injects the diffusion required impurity of source electrode and the required impurity 9 that drains (adopting high-energy to inject) then, shown in Fig. 2 e.
6, thermal annealing, knot forms source region and drain region, shown in Fig. 2 f.
Though the present invention discloses as above with preferred embodiment, yet is not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. field-effect transistor that mixes conducting mechanism, comprise source electrode, drain electrode, channel region and a control gate, source electrode and drain electrode lay respectively at the control gate both sides, control gate is positioned at the channel region top, it is characterized in that, source electrode comprises tunnelling source electrode and two parts of diffusion source electrode, wherein tunnelling source electrode junction depth is more shallow, diffusion source electrode junction depth is darker, two source electrodes all are positioned at control gate one side to be done current potential simultaneously and draws, and for the N-type device, source electrode comprises the shallow tunnelling source electrode of a P type, with the dark diffusion source electrode of N-type, for P type device, source electrode comprises the shallow tunnelling source electrode of a N-type, and the diffusion source electrode of P moldeed depth, the doping type of drain electrode is identical with the diffusion source electrode, and the doping type of substrate is identical with tunnelling source dopant type.
2. the field-effect transistor of mixing conducting mechanism as claimed in claim 1 is characterized in that, the junction depth of described tunnelling source electrode is between 10 nanometers-1 micron.
3. the field-effect transistor of mixing conducting mechanism as claimed in claim 1 is characterized in that, the doping content value of described raceway groove is at 1E14cm
-3-1E17cm
-3Between.
4. the field-effect transistor of mixing conducting mechanism as claimed in claim 1 is characterized in that, described raceway groove is taked the mode of vertical two districts doping or the doping way of multi-region.
5. the field-effect transistor of mixing conducting mechanism as claimed in claim 1 is characterized in that, device application is in silicon-based semiconductor material, or is applied to other semi-conducting materials.
6. the field-effect transistor of mixing conducting mechanism as claimed in claim 5 is characterized in that, device is based on the body silicon materials or based on the SOI material.
7. the field-effect transistor of mixing conducting mechanism as claimed in claim 1 is characterized in that, the gate dielectric layer material adopts silicon dioxide, or other high K dielectric layer materials.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102364690B (en) * | 2011-11-02 | 2013-11-06 | 北京大学 | Tunneling field effect transistor (TFET) and manufacturing method thereof |
| CN102664192B (en) * | 2012-05-08 | 2015-03-11 | 北京大学 | Self-adaptive composite mechanism tunneling field effect transistor (TFET) and preparation method thereof |
| US9484423B2 (en) | 2013-11-01 | 2016-11-01 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet III-V channel FETs |
| US9570609B2 (en) | 2013-11-01 | 2017-02-14 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same |
| CN103996713B (en) * | 2014-04-22 | 2017-02-15 | 北京大学 | Vertical-channel double-mechanism conduction nano-wire tunneling transistor and preparation method |
| US9647098B2 (en) | 2014-07-21 | 2017-05-09 | Samsung Electronics Co., Ltd. | Thermionically-overdriven tunnel FETs and methods of fabricating the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5896314A (en) * | 1997-03-05 | 1999-04-20 | Macronix International Co., Ltd. | Asymmetric flash EEPROM with a pocket to focus electron injection and a manufacturing method therefor |
| CN1602544A (en) * | 2001-12-11 | 2005-03-30 | 因芬尼昂技术股份公司 | Method for making high voltage MOS transistor by ion implantation |
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| US8026509B2 (en) * | 2008-12-30 | 2011-09-27 | Intel Corporation | Tunnel field effect transistor and method of manufacturing same |
| US8405121B2 (en) * | 2009-02-12 | 2013-03-26 | Infineon Technologies Ag | Semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5896314A (en) * | 1997-03-05 | 1999-04-20 | Macronix International Co., Ltd. | Asymmetric flash EEPROM with a pocket to focus electron injection and a manufacturing method therefor |
| CN1602544A (en) * | 2001-12-11 | 2005-03-30 | 因芬尼昂技术股份公司 | Method for making high voltage MOS transistor by ion implantation |
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