CN103560153A - Tunneling field effect transistor and preparation method thereof - Google Patents
Tunneling field effect transistor and preparation method thereof Download PDFInfo
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- 230000005641 tunneling Effects 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 238000002353 field-effect transistor method Methods 0.000 title description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 80
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 80
- 239000010703 silicon Substances 0.000 claims abstract description 80
- 230000005669 field effect Effects 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 28
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000002347 injection Methods 0.000 abstract 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The invention provides a tunneling field effect transistor and a preparation method thereof. The preparation method at least comprises the following steps that an SOI substrate provided with top layer silicon, an oxygen buried layer and bottom layer silicon is provided, and ion injection is conducted on the two sides of the top layer silicon to form a source electrode and a drain electrode respectively; an intrinsic silicon layer, and a grid medium layer and a grid layer are sequentially formed on the surface of the SOI substrate from bottom to top; a stacking structure is formed by etching the intrinsic silicon layer, the grid medium layer and the grid layer through the photoetching and etching technologies, the stacking structure is partially overlapped with the source electrode and is preset distance away from the drain electrode in the horizontal direction. According to the tunneling field effect transistor and the preparation method of the tunneling field effect transistor, the stacking structure is overlapped with the source electrode so that the tunneling area can be increased, and further a driving current is increased. In addition, the stacking structure is preset distance away from the drain electrode in the horizontal direction, and the bipolar effect in the tunneling field effect transistor can be suppressed through the preset distance, and a subthreshold current is reduced.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of tunneling field-effect transistor and preparation method thereof.
Background technology
In recent years, the microelectric technique that the silicon integrated circuit of take is core has obtained development rapidly, and Moore's Law is followed in the development of integrated circuit (IC) chip substantially, and semiconductor chip integrated level is with every speed increment of doubling for 18 months.Following period of time in the past, the progress of microelectric technique is that to continue to optimize the cost benefit of material, technique and flow process be basis.Yet along with the development of microelectric technique, conventional silicon base CMOS transistor is scaled has become more and more difficult.And, there is following subject matter in the most of electronic products of utilizing now MOSFET to manufacture: the first, because causing electric leakage, MOSFET channel shortening becomes large, even also continuous power consumption in shutdown or standby.IBM quotes the report of European Union and points out, 10% family and office's electric power are all the holding states that is wasted in electronic product.The second, conventional MOS FET is subject to the restriction of physical mechanism, and its subthreshold swing is higher.
One of scheme overcoming the above problems is exactly to adopt tunneling field-effect transistor (Tunnel FET:TFET) structure, tunneling field-effect transistor (TFET) is a kind of Novel work mechanism device, can suppress short-channel effect, effectively reduce leakage current, so it has the advantage of low speed paper tape reader static power disspation.Its subthreshold slope can be broken the restriction (being 60mV/dec under normal temperature) of KT/q simultaneously, and this is conducive at operation at low power supply voltage.Yet tunneling effect transistor (TFET) is faced with the little problem of drive current galvanic areas little and low subthreshold slope.At present, in field, propose various prioritization schemes, comprise attenuate gate oxide thickness, adopt high K grid material, adopt double-gate structure etc.; Also comprise use non-silicon material, as the other materials such as Ge of small gap material, the III-V family material of Broken-gap structure etc.And when attenuate gate oxide thickness or use hafnium, or when using low-gap semiconductor, when improving device performance, also can cause bipolar electrode effect (ambipolar behavior) obvious, bipolar leakage current (ambipolar leakage) is increased, show as sub-threshold current and increase, this will make the performance degradation of device.
Summary of the invention
The shortcoming of prior art, the object of the present invention is to provide a kind of tunneling field-effect transistor and preparation method thereof in view of the above, for solving the problem that the common tunneling field-effect crystal-driven of prior art electric current is low, have bipolar electrode effect.
For achieving the above object and other relevant objects, the invention provides a kind of tunneling field-effect transistor and preparation method thereof, the preparation method of described tunneling field-effect transistor at least comprises step:
1) provide a SOI substrate with top layer silicon, oxygen buried layer and bottom silicon, in described top layer silicon both sides, carry out Implantation and form respectively source electrode and drain electrode;
2) at described SOI substrate surface, form successively intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top;
3) utilize intrinsic silicon layer described in photoetching and lithographic technique etching, gate dielectric layer and grid layer, formation by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface forms, described stacked structure and described source electrode portion be overlapping, have in the horizontal direction a predeterminable range with described drain electrode.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, the size range of described predeterminable range is 1/4Lg～Lg, and wherein, Lg is grid length.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described source electrode is P type heavily-doped semiconductor, and described drain electrode is N-type heavily-doped semiconductor.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described source electrode is N-type heavily-doped semiconductor, and described drain electrode is P type heavily-doped semiconductor.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, adopt chemical vapor deposition method to form successively intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top at described SOI substrate surface.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described oxygen buried layer is SiO
2; Described gate dielectric layer is HfO
2or SiO
2.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described grid is metal gates, monocrystalline silicon or polysilicon.
As the scheme of a kind of optimization of tunneling field-effect transistor of the present invention, described grid is TiN.
The present invention also provides a kind of tunneling field-effect transistor, and described tunneling field-effect pipe at least comprises:
SOI substrate, described SOI substrate comprises top layer silicon, oxygen buried layer and bottom silicon;
Source electrode and drain electrode, be formed at respectively described top layer silicon both sides;
Stacked structure, is formed on described SOI substrate, and described stacked structure comprises intrinsic silicon, is positioned at the gate medium on described intrinsic silicon surface and the grid that is positioned at described gate medium surface; Described stacked structure and described source electrode portion be overlapping, have in the horizontal direction a predeterminable range with described drain electrode.
As the structure of a kind of optimization of tunneling field-effect transistor of the present invention, the size range of described predeterminable range is 1/4Lg～Lg, and wherein, Lg is grid length.
As mentioned above, tunneling field-effect transistor of the present invention and preparation method thereof, there is following beneficial effect: the stacked structure that includes intrinsic silicon, gate medium and grid is formed on described SOI substrate, make the overlapping of described stacked structure and described source electrode, utilize the overlapping of described stacked structure and source electrode, can increase tunnelling area, and then increase drive current; In addition, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, by this predeterminable range, can suppress the bipolar electrode effect in tunneling field-effect transistor, reduce sub-threshold current.
Accompanying drawing explanation
Fig. 1 is tunneling field-effect transistor preparation method's of the present invention schematic flow sheet.
Fig. 2～Fig. 3 is the structural representation that tunneling field-effect transistor preparation method's of the present invention step 1) presents.
Fig. 4 is tunneling field-effect transistor preparation method's of the present invention step 2) structural representation that presents.
Fig. 5 is the structural representation that tunneling field-effect transistor preparation method's of the present invention step 3) presents.
Element numbers explanation
S1～S3 step
1 SOI substrate
11 top layer silicon
12 oxygen buried layers
13 bottom silicon
2 drain electrodes
3 source electrodes
4 top layer intrinsic silicons
5 intrinsic silicon layer
6 gate dielectric layers
7 grid layers
8 intrinsic silicons
9 gate mediums
10 grids
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment mono-
The invention provides a kind of preparation method of tunneling field-effect transistor, preparation method's flow chart as shown in Figure 1, the preparation method of described tunneling field-effect transistor at least comprises the following steps:
S1, provides a SOI substrate with top layer silicon, oxygen buried layer and bottom silicon, carries out Implantation form respectively source electrode and drain electrode in described top layer silicon both sides;
S2, forms intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top successively at described SOI substrate surface;
S3, utilize intrinsic silicon layer described in photoetching and lithographic technique etching, gate dielectric layer and grid layer, formation by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface forms, described stacked structure and described source electrode portion be overlapping, have in the horizontal direction a predeterminable range with described drain electrode.
Below in conjunction with accompanying drawing, specifically describe the preparation method of tunneling field-effect transistor provided by the invention.
First perform step S1, a SOI substrate with top layer silicon, oxygen buried layer and bottom silicon is provided, in described top layer silicon both sides, carry out Implantation and form respectively source electrode and drain electrode.
Refer to Fig. 1, in the SOI substrate 1 providing, be followed successively by bottom silicon 13, oxygen buried layer 12 and top layer silicon 11 from bottom to top.Described oxygen buried layer 12 includes but not limited to as silicon dioxide.
As a preferred version of the embodiment of the present invention, the optional 20～30nm of thickness of described top layer silicon 11, described oxygen buried layer 12 thickness are 50nm～100nm, the thickness of described bottom silicon 13 is 60nm～150nm.In the present embodiment, the thickness of described top layer silicon 11 is elected 30nm temporarily as, the thickness of described oxygen buried layer 12 is elected 100 nanometers temporarily as, the thickness of described bottom silicon 13 is elected 150nm temporarily as, but be not limited to this, at other embodiment, also can be other thickness, such as the desirable 20nm of thickness, 22nm, 25nm or the 28nm etc. of top layer silicon 11, the desirable 50nm of thickness, 70nm, 80nm or the 90nm etc. of oxygen buried layer 12, the desirable 60nm of thickness, 80nm, 100nm, 120nm or the 140nm etc. of described bottom silicon 13.
Refer to Fig. 2, adopt ion implantation technology in the both sides of described top layer silicon 11, to carry out heavy doping to form source electrode 3 and drain electrode 2.Wherein, if the source electrode 3 that doping forms is P type heavily-doped semiconductor, 2 of the drain electrodes of opposite side are N-type heavily-doped semiconductor; If the source electrode 3 that doping forms is N-type heavily-doped semiconductor, 2 of the drain electrodes of opposite side are P type heavily-doped semiconductor.In the present embodiment, take source electrode 3 as P type heavily-doped semiconductor, drain 2 as N-type heavily-doped semiconductor be example, refer to accompanying drawing 3.In described source electrode 3, P type doping ion is boron, and doping content is 1E16cm
-3～1E20cm
-3, but be not limited to this, in other embodiments, also can select other P type doping ion.In described drain electrode 2, N-type doping ion is phosphorus or arsenic, and doping content is 1E16cm
-3～1E20cm
-3, but be not limited to this, in other embodiments, also can select other N-type doping ion.
Carry out after Implantation, need to carry out annealing in process to SOI substrate 1, damage lattice being caused when reducing Implantation.The temperature of carrying out annealing in process is 900～1100 ℃.
Described top layer silicon 11 is carried out after the doping of both sides, and residue mid portion is top layer intrinsic silicon 4, is used as source electrode 3 and the raceway groove that between 2, charge carrier passes through that drains.
Then perform step S2, at described SOI substrate surface, form successively intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top.
Refer to Fig. 4, on described SOI substrate 1, adopt chemical vapour deposition technique grow successively intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7.Certainly, also can adopt the techniques such as molecular beam epitaxy to form described intrinsic silicon layer 5.Forming gate dielectric layer 6 and grid layer 7 can be also other applicable techniques.
Optional 10～the 20nm of thickness of the intrinsic silicon layer 5 forming, the thickness of described gate dielectric layer 6 is 25nm～40nm, the thickness of described grid layer 7 is 60nm～150nm.In the present embodiment, the thickness of the intrinsic silicon layer 5 of formation is 20nm, and the thickness of described gate dielectric layer is 40nm, and the thickness of described grid layer 7 is 150nm.
Finally perform step S3, utilize intrinsic silicon layer described in photoetching and lithographic technique etching, gate dielectric layer and grid layer, formation by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface forms, described stacked structure and described source electrode portion be overlapping, have in the horizontal direction a predeterminable range with described drain electrode.
According to predetermined width, etch away all side parts of described intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7, particularly, can adopt dry method or wet etching method to etch away all side parts of described intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7, to form on described top layer silicon 11 surfaces the stacked structure being formed by described intrinsic silicon 8, gate medium 9 and grid 10, as shown in Figure 5.More specifically, in the present embodiment, at intrinsic silicon layer 5, gate dielectric layer 6 and grid layer 7 described in use wet-etching technology etching.Process is: first at the surperficial spin coating photoresist layer of described grid layer 7 (diagram), graphical photoresist layer forms opening, then intrinsic silicon layer 5, gate dielectric layer 6 and the grid layer 7 of opening below are carried out to wet etching, thereby forms described stacked structure.
Wherein, described gate dielectric layer 6 is HfO
2or SiO
2, but be not limited to this.
Described grid 10 can be metal gates, monocrystalline silicon or polysilicon, and in the present embodiment, described grid 10 is metal gates.Further, described grid is TiN.
Described intrinsic silicon 8 together with aforementioned top layer intrinsic silicon 4 as the raceway groove of source electrode 3 and the circulation of charge carrier between 2 that drains.
The stacked structure forming as shown in Figure 5, described stacked structure and described source electrode 3 parts are overlapping, and described drain electrode 2 there is in the horizontal direction a predeterminable range, this horizontal direction refers to the directions X in Fig. 5.On directions X, the crossover region of described stacked structure and source electrode 3 is of a size of D1, and described stacked structure and described drain electrode 2 have a predeterminable range D2.Described crossover region is of a size of 0 < D1≤1/2Lg; The scope of described predeterminable range D2 is 1/4Lg～Lg, and wherein, Lg is that grid 10 is along the length of directions X.
Overlapping owing to existing between source electrode 3 and stacked structure, therefore can increase the area of tunnelling, the drive current of device is improved.
The bipolar electrode effect of tunneling field-effect transistor is owing to also can produce band-to-band-tunneling (band-to-band tunneling) electric current at drain terminal knot place, subthreshold leakage current is increased, transistorized performance degradation.The present invention, owing to having a predeterminable range between described stacked structure and described drain electrode 2, can suppress bipolar electrode effect, prevents that drain terminal from producing tunnelling current, and subthreshold leakage current is reduced, and improves device overall performance.
It should be noted that, form source electrode 3, drain 2 and grid 10 after, at SOI substrate surface deposit earth silicon material, form insulating barrier (diagram), then mask exposure etching insulating barrier, respectively described source electrode 3, drain 2 and grid 10 on form source electrode through hole, drain electrode through hole and gate via (diagram), also need afterwards to form interconnection wiring with metallic aluminum material filling vias.
Embodiment bis-
The present invention also provides a kind of tunneling field-effect transistor, by a kind of described preparation method who provides of embodiment, makes, and described tunneling field-effect transistor at least comprises:
SOI substrate 1, described SOI substrate 1 comprises top layer silicon 11, oxygen buried layer 12 and bottom silicon 13;
Stacked structure, is formed on described SOI substrate 1, and described stacked structure comprises intrinsic silicon 8, is positioned at the gate medium 9 on described intrinsic silicon 8 surfaces and the grid 10 that is positioned at described gate medium 9 surfaces; Described stacked structure and described source electrode 3 parts are overlapping, have in the horizontal direction a predeterminable range with described drain electrode 2.
The stacked structure forming as shown in Figure 5, described stacked structure and described source electrode 3 parts are overlapping, and described drain electrode 2 there is in the horizontal direction a predeterminable range, this horizontal direction refers to directions X in Fig. 5.On this directions X, the crossover region of described stacked structure and source electrode 3 is of a size of D1, and described stacked structure and described drain electrode 2 have a predeterminable range D2.Described crossover region is of a size of 0 < D1≤1/2Lg; The scope of described predeterminable range D2 is 1/4Lg～Lg, and wherein, Lg is that grid 10 is along the length of directions X.
Overlapping owing to existing between source electrode 3 and stacked structure, therefore can increase the area of tunnelling, the drive current of device is improved.
The bipolar electrode effect of tunneling field-effect transistor is owing to also can produce band-to-band-tunneling (band-to-band tunneling) electric current at drain terminal knot place, subthreshold leakage current is increased, transistorized performance degradation.The present invention, owing to having a predeterminable range between described stacked structure and described drain electrode 2, can suppress bipolar electrode effect, prevents that drain terminal from producing tunnelling current, and subthreshold leakage current is reduced, and improves device overall performance.
In sum, the invention provides a kind of tunneling field-effect transistor and preparation method thereof, the stacked structure that includes intrinsic silicon, gate medium and grid is formed on described SOI substrate, make the overlapping of described stacked structure and described source electrode, utilize the overlapping of described stacked structure and source electrode, increase tunnelling area, and then increase drive current; In addition, described stacked structure and described drain electrode have a predeterminable range in the horizontal direction, by this predeterminable range, can suppress the bipolar electrode effect in tunneling field-effect transistor, reduce sub-threshold current.
So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (10)
1. a preparation method for tunneling field-effect transistor, is characterized in that, the preparation method of described tunneling field-effect transistor at least comprises step:
1) provide a SOI substrate with top layer silicon, oxygen buried layer and bottom silicon, in described top layer silicon both sides, carry out Implantation and form respectively source electrode and drain electrode;
2) at described SOI substrate surface, form successively intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top;
3) utilize intrinsic silicon layer described in photoetching and lithographic technique etching, gate dielectric layer and grid layer, formation by intrinsic silicon, be positioned at the gate medium on described intrinsic silicon surface and be positioned at the stacked structure that the grid on described gate medium surface forms, described stacked structure and described source electrode portion be overlapping, have in the horizontal direction a predeterminable range with described drain electrode.
2. the preparation method of tunneling field-effect transistor according to claim 1, is characterized in that: the size range of described predeterminable range is 1/4Lg～Lg, and wherein, Lg is grid length.
3. the preparation method of tunneling field-effect transistor according to claim 1, is characterized in that: described source electrode is P type heavily-doped semiconductor, and described drain electrode is N-type heavily-doped semiconductor.
4. the preparation method of tunneling field-effect transistor according to claim 1, is characterized in that: described source electrode is N-type heavily-doped semiconductor, and described drain electrode is P type heavily-doped semiconductor.
5. the preparation method of tunneling field-effect transistor according to claim 1, is characterized in that: adopt chemical vapor deposition method to form successively intrinsic silicon layer, gate dielectric layer and grid layer from bottom to top at described SOI substrate surface.
6. the preparation method of tunneling field-effect transistor according to claim 1, is characterized in that: described oxygen buried layer is SiO
2; Described gate dielectric layer is HfO
2or SiO
2.
7. the preparation method of tunneling field-effect transistor according to claim 1, is characterized in that: described grid is metal gates, monocrystalline silicon or polysilicon.
8. the preparation method of tunneling field-effect transistor according to claim 7, is characterized in that: described grid is TiN.
9. a tunneling field-effect transistor, is characterized in that, described tunneling field-effect pipe at least comprises:
SOI substrate, described SOI substrate comprises top layer silicon, oxygen buried layer and bottom silicon;
Source electrode and drain electrode, be formed at respectively described top layer silicon both sides;
Stacked structure, is formed on described SOI substrate, and described stacked structure comprises intrinsic silicon, is positioned at the gate medium on described intrinsic silicon surface and the grid that is positioned at described gate medium surface; Described stacked structure and described source electrode portion be overlapping, have in the horizontal direction a predeterminable range with described drain electrode.
10. the preparation method of tunneling field-effect transistor according to claim 9, is characterized in that: the size range of described predeterminable range is 1/4Lg～Lg, and wherein, Lg is grid length.
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|---|---|---|---|
| CN201310574824.5A CN103560153B (en) | 2013-11-15 | 2013-11-15 | A kind of tunneling field-effect transistor and preparation method thereof |
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| CN201310574824.5A CN103560153B (en) | 2013-11-15 | 2013-11-15 | A kind of tunneling field-effect transistor and preparation method thereof |
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|---|---|
| CN103560153A true CN103560153A (en) | 2014-02-05 |
| CN103560153B CN103560153B (en) | 2016-07-13 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018090260A1 (en) * | 2016-11-16 | 2018-05-24 | 华为技术有限公司 | Tunnel field effect transistor, and manufacturing method thereof |
| WO2018094599A1 (en) * | 2016-11-23 | 2018-05-31 | 华为技术有限公司 | Method for preparing tunneling field effect transistor and tunneling field effect transistor thereof |
| CN108447902A (en) * | 2018-01-19 | 2018-08-24 | 西安电子科技大学 | It can inhibit the tunneling field-effect transistor and preparation method of dipolar effect |
| WO2018152836A1 (en) * | 2017-02-27 | 2018-08-30 | 华为技术有限公司 | Tunneling field effect transistor and manufacturing method therefor |
| CN109065615A (en) * | 2018-06-12 | 2018-12-21 | 西安电子科技大学 | A kind of heterogeneous tunneling field-effect transistor of novel planar InAs/Si and preparation method thereof |
| CN110729355A (en) * | 2019-10-23 | 2020-01-24 | 电子科技大学 | Longitudinal tunneling field effect transistor for improving sub-threshold swing amplitude |
| CN111564498A (en) * | 2020-05-13 | 2020-08-21 | 北京大学 | Self-aligned preparation method of drain-terminal negative overlap region of tunneling transistor |
| CN112002760A (en) * | 2020-08-28 | 2020-11-27 | 河南师范大学 | Based on MnBi2Te4Single layer nanoscale field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6617643B1 (en) * | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
| CN102664165A (en) * | 2012-05-18 | 2012-09-12 | 北京大学 | Method for manufacturing complementary tunneling field effect transistor (TFET) based on standard complementary metal oxide semiconductor integrated circuit (CMOS IC) process |
| WO2012152762A1 (en) * | 2011-05-06 | 2012-11-15 | Imec | Tunnel field effect transistor device |
-
2013
- 2013-11-15 CN CN201310574824.5A patent/CN103560153B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6617643B1 (en) * | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
| WO2012152762A1 (en) * | 2011-05-06 | 2012-11-15 | Imec | Tunnel field effect transistor device |
| CN102664165A (en) * | 2012-05-18 | 2012-09-12 | 北京大学 | Method for manufacturing complementary tunneling field effect transistor (TFET) based on standard complementary metal oxide semiconductor integrated circuit (CMOS IC) process |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018090260A1 (en) * | 2016-11-16 | 2018-05-24 | 华为技术有限公司 | Tunnel field effect transistor, and manufacturing method thereof |
| WO2018094599A1 (en) * | 2016-11-23 | 2018-05-31 | 华为技术有限公司 | Method for preparing tunneling field effect transistor and tunneling field effect transistor thereof |
| CN108352406A (en) * | 2016-11-23 | 2018-07-31 | 华为技术有限公司 | A kind of tunneling field-effect transistor preparation method and its tunneling field-effect transistor |
| WO2018152836A1 (en) * | 2017-02-27 | 2018-08-30 | 华为技术有限公司 | Tunneling field effect transistor and manufacturing method therefor |
| CN108447902A (en) * | 2018-01-19 | 2018-08-24 | 西安电子科技大学 | It can inhibit the tunneling field-effect transistor and preparation method of dipolar effect |
| CN109065615A (en) * | 2018-06-12 | 2018-12-21 | 西安电子科技大学 | A kind of heterogeneous tunneling field-effect transistor of novel planar InAs/Si and preparation method thereof |
| CN109065615B (en) * | 2018-06-12 | 2021-05-07 | 西安电子科技大学 | Novel planar InAs/Si heterogeneous tunneling field effect transistor and preparation method thereof |
| CN110729355A (en) * | 2019-10-23 | 2020-01-24 | 电子科技大学 | Longitudinal tunneling field effect transistor for improving sub-threshold swing amplitude |
| CN111564498A (en) * | 2020-05-13 | 2020-08-21 | 北京大学 | Self-aligned preparation method of drain-terminal negative overlap region of tunneling transistor |
| CN112002760A (en) * | 2020-08-28 | 2020-11-27 | 河南师范大学 | Based on MnBi2Te4Single layer nanoscale field effect transistor |
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