CN103311123A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN103311123A CN103311123A CN2012100674382A CN201210067438A CN103311123A CN 103311123 A CN103311123 A CN 103311123A CN 2012100674382 A CN2012100674382 A CN 2012100674382A CN 201210067438 A CN201210067438 A CN 201210067438A CN 103311123 A CN103311123 A CN 103311123A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- group
- mask layer
- lines
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000001259 photo etching Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 44
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 239000013081 microcrystal Substances 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 6
- 230000000873 masking effect Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 17
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002070 nanowire Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000002635 aromatic organic solvent Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000003049 inorganic solvent Substances 0.000 description 1
- 229910001867 inorganic solvent Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention discloses a semiconductor device manufacturing method, which comprises the following steps: forming a second group of hard mask layers on the substrate; forming a first group of hard mask layers on the second group of hard mask layers; photoetching/etching the first group of hard mask layers to form a first group of lines; photoetching/etching the second group of hard mask layers by taking the first group of lines as a mask to form a second group of lines, wherein the width of the second group of lines is smaller than that of the first group of lines; and etching the substrate by taking the second group of lines as a mask to form the fins. According to the manufacturing method of the semiconductor device, the mask with the multiple structures is adopted, and the side wall masking is used twice to etch and pattern, so that the nano-line with the size smaller than the photoetching limit size is obtained. The process is simple, the precision is high, and the compatibility is high.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to the method that twice side wall masking graphics of a kind of employing prepares the nanometer lines.
Background technology
Along with the development of time, the public is more and more higher for the performance requirement of semiconductor device that with CMOS is representative, impels that the variation of making rapid progress has taken place device architecture in the main stream of CMOS technology.For example, just adopted metal silicide to reduce source drain contact resistance during the above technology of 130nm, then introduce super shallow junction (USJ) and stressor layers during 90nm to 45nm technology to improve the channel region carrier mobility, further introduced during 45nm to 28nm technology high-k (high k) do gate insulator and adopt first grid technique or the back grid technique make metal gates, for example adopted then when 22nm to 15nm that the multiple-grid electrode structure of FinFET strengthens grid for the control of raceway groove, the WeiLai Technology below 15nm then comprises uses the III-V compounds of group to improve driving force, channel fet is to reduce gate control voltage, nano wire (NW) structure is to realize device subminaturization etc.
For example, conventional MOSFET is substrate with body silicon, and depletion region is thicker, and forming parasitic transistor easily influences device property.For this reason, develop and SOI MOSFET, do not have latch-up, have more high operation speed, have low-power consumption, anti-irradiation and can realize advantages such as 3 D stereo is integrated.Further, double gate SOI MOSFET has been proposed, by in oxygen buried layer (BOX), setting up bottom grid, thereby having reduced short-channel effect, leakage inductance answers potential barrier to reduce the ability that effect has strengthened scaled down, have lower junction capacitance, can realize the raceway groove light dope, can adjust threshold voltage by the work function of metal gate electrode, compare with SOI MOSFET and to have improved nearly one times drive current, the technological requirement for equivalent oxide thickness (EOT) is also lower in addition.Therefore, development multiple-grid device is trend of the times to improve device performance.
Existing multiple-grid device generally is divided into: a) double-gated devices, and double-deck grid device up and down such as GAA, SON for example, left and right sides double-deck grid devices such as MIGFET, and FinFET etc.; B) tri-gate devices, for example three gate MOSFETs, π type gate device, Ω type gate device etc.; C) surround gate device, for example the nano-wire fet of quadruple ring gate device, annulus gate device and many bridges/pile up.These different device architectures often need different backing materials, and for example therefore body silicon, SOI etc. have caused complex process, incompatible.
In addition, in order to control short-channel effect, need the thickness of grid less than gate length usually, for example the fin grid is generally rectangular laminar among the FinFET.Along with size constantly reduces, the requirement of equal proportion reduction is more and more higher, requires also more and more higher for the photoetching and the etching pattern technology that with FinFET are the small size device grid of representative.Characteristic size can be accomplished below the photolithography limitation size that for the extra small ultra thin device below the 15nm, prior art still faces significant challenge though utilize side wall shelter etching technology.
Summary of the invention
From the above mentioned, the object of the present invention is to provide a kind of efficient accurately, nanometer lines manufacture method that technology is simple and compatible high.
For this reason, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: form second group of hard mask layer at substrate; Form first group of hard mask layer at second group of hard mask layer; First group of hard mask layer of photoetching/etching forms first group of lines; Be mask with first group of lines, second group of hard mask layer of photoetching/etching forms second group of lines, and wherein second group of line thickness is less than first group of line thickness; Be mask with second group of lines, etched substrate forms fin.
Wherein, first group of hard mask layer comprises first hard mask layer and second hard mask layer, and second group of hard mask layer comprises the 3rd hard mask layer and the 4th hard mask layer.
Wherein, the step that forms first group of lines specifically comprises: photoetching/etching the 4th hard mask layer forms the 4th hard mask pattern at the 3rd hard mask layer; Form first side wall in the 4th hard mask pattern both sides; Remove the 4th hard mask pattern; Be mask with first side wall, etching the 3rd hard mask layer is also removed first side wall, stays independently the 3rd hard mask pattern at second hard mask layer, constitute first group of lines, wherein, the width of first group of lines equals the width of first side wall, and less than the width of the 4th hard mask pattern.
Wherein, the step that forms second group of lines specifically comprises: form second side wall first group of lines both sides; Remove first group of lines; Be mask with second side wall, etching second hard mask layer is also removed second side wall, stays the independently second hard mask pattern at first hard mask layer, constitute second group of lines, wherein, the width of second group of lines equals the width of second side wall, and less than the width of first group of lines.
Wherein, the material of substrate, first hard mask layer, second hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, first side wall and second side wall is selected according to following principle: any adjacent two-layer material difference.
Wherein, the material of substrate, first hard mask layer, second hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, first side wall and second side wall is selected from following scope: silica-base material, silica, silicon nitride, silicon oxynitride.
Wherein, silica-base material comprises monocrystalline silicon, amorphous silicon, microcrystal silicon, low temperature polycrystalline silicon, high temperature polysilicon.
Wherein, the formation method of first group of hard mask layer and/or second group of hard mask layer comprises LPCVD, PECVD, HDPCVD, ALD, the thermal decomposed deposition of cryochemistry thing, sputter, evaporation.
According to method, semi-conductor device manufacturing method of the present invention, adopt the multiplet mask, shelter etching graphical with twice side wall, thereby obtained the nanometer lines less than the photolithography limitation size.Technology is simple, the precision height, and compatible high.
Description of drawings
Followingly describe technical scheme of the present invention in detail with reference to accompanying drawing, wherein:
Fig. 1 to Figure 18 is the generalized section according to each step of manufacture method of the present invention; And
Figure 19 is according to manufacture method flow chart of the present invention.
Embodiment
Followingly describe feature and the technique effect thereof of technical solution of the present invention in detail with reference to accompanying drawing and in conjunction with schematic embodiment, disclose efficient accurately, nanometer lines manufacture method that technology is simple and compatible high.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These are modified is not space, order or the hierarchical relationship of hint institute's modification device architecture or manufacturing process unless stated otherwise.
Generalized section hereinafter with reference to Fig. 1 to Figure 18 describes in detail according to each step of manufacture method of the present invention.
At first, with reference to Fig. 1, form a plurality of hard mask layers at substrate.Substrate 1 is provided, material for example is monocrystalline silicon, silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nano-tube etc.Preferably, substrate 1 is body silicon or SOI, with the compatibility of raising with other CMOS technologies.Then, adopt conventional methods such as LPCVD, PECVD, HDPCVD, ALD, the thermal decomposed deposition of cryochemistry thing, sputter, evaporation, at substrate 1 deposition first hard mask layer 2, its material for example is silicon nitride (SiN
x, x can be 1～2, is not limited to integer) or silicon oxynitride (SiO
xN
y, x, y can rationally adjust according to needs).At first hard mask layer, 2 depositions, second hard mask layer 3, its material for example is different from the material of first hard mask layer 2 for amorphous silicon, microcrystal silicon, high temperature polysilicon or low temperature polycrystalline silicon etching characteristics such as (p-Si), and its thickness is 10～100nm for example.For example adopt LPCVD to form amorphous silicon at 580 ℃ with deposit, adopt the laser irradiation to make that amorphous silicon is local-crystalized afterwards alternatively and form low temperature polycrystalline silicon or microcrystal silicon, perhaps LPCVD forms high temperature polysilicon in deposition more than 580 ℃.At second hard mask layer, 3 depositions the 3rd hard mask layer 4, its material for example is different from the material of first hard mask layer 2 and second hard mask layer 3 for etching characteristics such as silica, deposition process is LPCVD, PECVD, HDPCVD, the thermal decomposed deposition of cryochemistry thing, sputter, evaporation etc. for example.In addition, also can in-situ doped B, P in the 3rd hard mask layer 4, C, N, impurity such as O, As form doped-glasses, to change etching characteristic.At the 3rd hard mask layer 4 depositions the 4th hard mask layer 5, its material can be identical with second hard mask layer 3, for example is p-Si.Preferably its thickness is greater than and equals second hard mask layer 3 so that the uniformity when improving the top layer etching and obtain better conformality, and for example when second hard mask layer, 3 thickness were 10～50nm, the 4th hard mask layer 5 thickness were 50～100nm.More than four layers of hard mask layer 2,3,4,5 constitute four stack structures layer by layer from the bottom to top, its layer 5 and layer 4 at the middle and upper levels is used for for the first time that therefore the side wall forming process can be called first group of hard mask layer, and the layer 3 of lower floor and layer 2 are used for for the second time that therefore the side wall forming process can be called second group of hard mask layer.Alternatively, layer 5/4/3/2 is not limited to above-mentioned concrete material and limits, as long as adjacent each layer material is different because have bigger etching selection ratio, can forms meticulous etching figure and get final product.For example, layer 5/4/3/2 can be p-Si/SiN
x/ p-Si/SiO
2, perhaps SiN
x/ p-Si/SiN
x/ SiO
2, perhaps p-Si/SiO
2/ p-Si/SiO
2, or p-Si/SiN
x/ p-Si/SiN
xEtc., and wherein p-Si can replace with amorphous silicon, microcrystal silicon or high temperature polysilicon.Spin coating photoresist PR above first group of hard mask layer 5/4 subsequently, and preferably, the top of photoresist PR can spin coating reflection coating provided (TAR, belong to a kind of of antireflecting coating ARC), and/or above first group of hard mask layer 5/4, deposit for example bottom antireflective coating of TiN (BARC, not shown) and then spin coating photoresist PR earlier.
Secondly, with reference to Fig. 2, need and first mask plate be set according to device architectures such as MOSFET, to photoresist PR and ARC thereof expose, a series of lithography steps such as development, post bake, formed a plurality of photoresist figure PRP, each PRP all has first width.It is clear in order to draw to it should be noted that in the accompanying drawing, only drawn minority figures such as, two or four, but technical solution of the present invention can be applied to more graphic structures in fact, as long as the MOSFET device architecture needs.
Again, with reference to Fig. 3, be mask with photoresist figure PRP, etching the 4th hard mask layer 5 until exposing the 3rd hard mask layer 4, forms a plurality of the 4th hard mask graph 5P.When the 4th hard mask layer 5 materials are silica-based material such as amorphous silicon, microcrystal silicon, low temperature polycrystalline silicon, can select for use alkaline wet etching liquid such as KOH, TMAH to remove; When the 4th hard mask layer 5 materials are silica, can adopt acid wet method corrosive liquid such as HF, BOE to remove; When the 4th hard mask layer 5 materials are silicon nitride or silicon oxynitride, adopt strong oxidizers such as hot phosphoric acid, the concentrated sulfuric acid, hydrogen peroxide to come wet etching to remove.Perhaps adopt dry etching to remove the 4th hard mask layer 5 of above various materials, for example adopt fluoro-gas (carbon fluorine base gas, SF
6, NF
3Deng) plasma etching.Burn into etching about similar layers of material, below repeat no more, but according to material characteristic and etching precision requirement, with reference to foregoing description and the choose reasonable technological parameter, the for example temperature of wet etching, proportioning, time, the etching gas of dry etching, flow velocity, power, carrier gas, additive, time, temperature etc.Therefore, every technology of removing a certain hard mask layer that relates to hereinafter, its concrete grammar all can be with reference to above description.
Then, with reference to Fig. 4, remove remaining photoresist figure PRP, stay independently a plurality of the 4th hard mask pattern 5P at the 3rd hard mask layer 4.The removal method for example adopts acetone and aromatic organic solvent, perhaps the inorganic solvent of sulfuric acid/hydrogen peroxide, perhaps plasma etching removal etc.The width of the 4th hard mask pattern 5P is identical with photoresist figure PRP, all has first width.
Then, with reference to Fig. 5, on entire device, also namely on the 4th hard mask pattern 5P and the 3rd hard mask layer 4, by common process such as LPCVD, PECVD, HDPCVD, ALD, the thermal decomposed deposition of cryochemistry thing, sputter, the evaporation deposition formation first spacer material layer 6.The material of the first spacer material layer 6 is all different with the 4th hard mask layer 5 and the 3rd hard mask layer 4, to obtain good etching selection, for example 6/5/4 is respectively SiN
x/ p-Si/SiO
2, perhaps p-Si/SiN
x/ SiO
2, SiN
x/ SiO
2/ p-Si, p-Si/SiO
2/ SiN
xEtc., and wherein p-Si can replace with amorphous silicon, microcrystal silicon or high temperature polysilicon.
After this, with reference to Fig. 6, photoetching/etching first spacer material layer 6 forms a plurality of first side wall 6S in the 4th hard mask pattern 5P both sides.Wherein, the spacing of the first side wall 6S is first width of the 4th hard mask pattern 5P, and the width of the first side wall 6S self is second width, and second width is less than first width.
Then, with reference to Fig. 7, remove the 4th hard mask pattern 5P, stay independently a plurality of first side wall 6S at the 3rd hard mask layer 4.
Then, with reference to Fig. 8, be mask with the first side wall 6S, photoetching/etching the 3rd hard mask layer 4 until exposing second hard mask layer 3, has formed a plurality of the 3rd hard mask pattern 4P.Wherein, the width of the 3rd hard mask pattern 4P self is second width of the first side wall 6S, and spacing is first width of the 4th hard mask pattern 5P.
Subsequently, with reference to Fig. 9, remove the first side wall 6S, stayed a plurality of independently the 3rd hard mask pattern 4P at second hard mask layer 3.More than pass through first group of hard mask layer photoetching/etching, the width of the first group of lines that obtains---the 3rd hard mask pattern 4P can tentatively improve the lines precision therefrom less than the precision of original PR photoetching/etching.
Then, with reference to Figure 10, on entire device, also namely on second hard mask layer 3 and the 3rd hard mask pattern 4P, by LPCVD, PECVD, HDPCVD, ALD, the thermal decomposed deposition of cryochemistry thing.Common process such as sputter, evaporation deposition forms the second spacer material layer 7.The material of the second spacer material layer 7 is all different with the material of the 3rd hard mask layer 4 and second hard mask layer 2, to obtain good etching selection.For example, 7/4/2 be respectively SiN
x/ SiO
2/ p-Si, perhaps SiN
x/ p-Si/SiO
2, p-Si/SiN
x/ SiO
2, p-Si/SiO
2/ SiN
xEtc., and wherein p-Si can replace with amorphous silicon, microcrystal silicon or high temperature polysilicon.
After this, with reference to Figure 11, photoetching/etching second spacer material layer 7 forms a plurality of second side wall 7S in the 3rd hard mask pattern 4P both sides.Wherein, the spacing of the first side wall 7S is second width of the 3rd hard mask pattern 4P, and the width of the second side wall 7S self is the 3rd width, and the 3rd width is less than second width.
Then, with reference to Figure 12, remove the 3rd hard mask pattern 4P, stay independently a plurality of second side wall 7S at second hard mask layer 3.
Then, with reference to Figure 13, be mask with the second side wall 7S, photoetching/etching second hard mask layer 3 until exposing first hard mask layer 2, has formed a plurality of second hard mask pattern 3P.Wherein, the width of the second hard mask pattern 3P self is the 3rd width of the second side wall 7S, and spacing is second width of the 3rd hard mask pattern 4P.
Subsequently, with reference to Figure 14, remove the second side wall 7S, stayed a plurality of independently second hard mask pattern 3P at first hard mask layer 2.
After this, with reference to Figure 15, be mask with the second hard mask pattern 3P, etching first hard mask layer 2 until exposing substrate 1, forms a plurality of first hard mask pattern 2P.Wherein, first hard mask pattern 2P self width equals the 3rd width of the second hard mask pattern 3P, and spacing equals second width of the 3rd hard mask pattern 4P.
Then, with reference to Figure 16, remove the second hard mask pattern 3P, stay a plurality of independently first hard mask pattern 2P at substrate 1.More than pass through second group of hard mask layer photoetching/etching, the width of the second group of lines that obtains---the first hard mask pattern 2P further less than the precision of original PR photoetching/etching, has improved the lines precision therefrom again.
Then, with reference to Figure 17, be mask with the first hard mask pattern 2P, etched substrate 1 forms a plurality of substrate figure 1P, constitutes the fin of device.
At last, with reference to Figure 18, remove the first hard mask pattern 2P, stay a plurality of independently substrate figure 1P.Lines self width of substrate figure 1P is the 3rd width of the first hard mask pattern 2P, the second hard mask pattern 3P, and spacing is second width of the 3rd hard mask pattern 4P.Can be seen that by Figure 18 fin also is that the thickness of substrate figure 1P is far smaller than its length, therefore constitute a plurality of vertical rectangular thin slices perpendicular to the substrate horizontal plane.These fins will be as the basis of gate stack structures such as gate insulator, grid conducting layer formation, so that the fine structure of good control grid in follow-up MOSFET manufacturing process.For example, by above-mentioned two step side wall technologies of the present invention, can control make fin thickness also be the width of substrate figure 1P less than 15nm, particularly less than 10nm, thereby form nano thread structure.
In sum, with reference to Figure 19, the flow chart of method of the present invention may further comprise the steps at least:
Form second group of hard mask layer at substrate;
Form first group of hard mask layer at second group of hard mask layer;
First group of hard mask layer of etching forms first group of lines;
Be mask with first group of lines, second group of hard mask layer of etching forms second group of lines;
Be mask with second group of lines, etched substrate forms fin.
Especially, although the present invention has only shown two step side wall technologies, in fact can implement more times side wall and form and remove technology, in order to utilize the precise decreasing that remedies width in photoetching/etching technics in the depositing operation for the accurate selection of thickness, can obtain meticulousr nano thread structure thus.
In addition, partly enumerate limited several hard mask material layers though it should be noted that the embodiment of the invention, also can select different other materials for use in actual the manufacturing, as long as any adjacent two-layer material difference is to guarantee higher etching selection ratio.Preferred p-Si is as the hard mask layer material except silicon nitride, these two kinds of conventional hard mask materials of silica in the embodiment of the invention, just for the example purpose, what should know is the material with higher etching selection ratio that can use other, and the thickness of each layer requires according to the etching pattern precision and selectes, for example 10～100nm.
According to method, semi-conductor device manufacturing method of the present invention, adopt the multiplet mask, shelter etching graphical with twice side wall, thereby obtained the nanometer lines less than the photolithography limitation size.Technology is simple, the precision height, and compatible high.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can be made by disclosed instruction and manyly may be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, purpose of the present invention does not lie in to be limited to as being used for and realizes preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.
Claims (8)
1. method, semi-conductor device manufacturing method comprises:
Form second group of hard mask layer at substrate;
Form first group of hard mask layer at second group of hard mask layer;
First group of hard mask layer of photoetching/etching forms first group of lines;
Be mask with first group of lines, second group of hard mask layer of photoetching/etching forms second group of lines, and wherein second group of line thickness is less than first group of line thickness;
Be mask with second group of lines, etched substrate forms fin.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, first group of hard mask layer comprises first hard mask layer and second hard mask layer, second group of hard mask layer comprises the 3rd hard mask layer and the 4th hard mask layer.
3. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, the step that forms first group of lines specifically comprises:
Photoetching/etching the 4th hard mask layer forms the 4th hard mask pattern at the 3rd hard mask layer;
Form first side wall in the 4th hard mask pattern both sides;
Remove the 4th hard mask pattern;
Be mask with first side wall, etching the 3rd hard mask layer is also removed first side wall, stays independently the 3rd hard mask pattern at second hard mask layer, constitutes first group of lines,
Wherein, the width of first group of lines equals the width of first side wall, and less than the width of the 4th hard mask pattern.
4. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, the step that forms second group of lines specifically comprises:
Form second side wall first group of lines both sides;
Remove first group of lines;
Be mask with second side wall, etching second hard mask layer is also removed second side wall, stays the independently second hard mask pattern at first hard mask layer, constitutes second group of lines,
Wherein, the width of second group of lines equals the width of second side wall, and less than the width of first group of lines.
5. as each method, semi-conductor device manufacturing method of claim 2 to 4, wherein, the material of substrate, first hard mask layer, second hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, first side wall and second side wall is selected according to following principle: any adjacent two-layer material difference.
6. method, semi-conductor device manufacturing method as claimed in claim 5, wherein, the material of substrate, first hard mask layer, second hard mask layer, the 3rd hard mask layer, the 4th hard mask layer, first side wall and second side wall is selected from following scope: silica-base material, silica, silicon nitride, silicon oxynitride.
7. method, semi-conductor device manufacturing method as claimed in claim 7, wherein, silica-base material comprises monocrystalline silicon, amorphous silicon, microcrystal silicon, low temperature polycrystalline silicon, high temperature polysilicon.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the formation method of first group of hard mask layer and/or second group of hard mask layer comprises LPCVD, PECVD, HDPCVD, ALD, the thermal decomposed deposition of cryochemistry thing, sputter, evaporation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210067438.2A CN103311123B (en) | 2012-03-14 | 2012-03-14 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210067438.2A CN103311123B (en) | 2012-03-14 | 2012-03-14 | Semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103311123A true CN103311123A (en) | 2013-09-18 |
| CN103311123B CN103311123B (en) | 2016-06-08 |
Family
ID=49136203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210067438.2A Active CN103311123B (en) | 2012-03-14 | 2012-03-14 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103311123B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104528634A (en) * | 2014-12-16 | 2015-04-22 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| WO2016015416A1 (en) * | 2014-07-31 | 2016-02-04 | 上海集成电路研发中心有限公司 | Method for cutting line top end of fin structure for double-pattern fin field effect transistor |
| CN105428317A (en) * | 2014-09-12 | 2016-03-23 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105470137A (en) * | 2014-09-12 | 2016-04-06 | 中国科学院微电子研究所 | Fin etching method |
| CN105762071A (en) * | 2014-12-17 | 2016-07-13 | 中国科学院微电子研究所 | Fin field effect transistor and manufacturing method of fin thereof |
| CN105762186A (en) * | 2014-12-17 | 2016-07-13 | 中国科学院微电子研究所 | Fin field effect transistor, fin structure and manufacturing method thereof |
| WO2016197766A1 (en) * | 2015-06-09 | 2016-12-15 | 华为技术有限公司 | Method for manufacturing nanowire |
| CN108807170A (en) * | 2018-06-11 | 2018-11-13 | 中国科学院微电子研究所 | Method for manufacturing nano wire |
| CN112967986A (en) * | 2020-10-19 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Transfer component, preparation method thereof and transfer head |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070065990A1 (en) * | 2005-09-16 | 2007-03-22 | Bart Degroote | Recursive spacer defined patterning |
| US20080254627A1 (en) * | 2005-06-09 | 2008-10-16 | Micron Technology, Inc. | Method for adjusting feature size and position |
| US20100167211A1 (en) * | 2008-12-30 | 2010-07-01 | Hynix Semiconductor Inc. | Method for forming fine patterns in a semiconductor device |
| US20110151668A1 (en) * | 2009-12-23 | 2011-06-23 | Tang Sanh D | Pitch division patterning techniques |
-
2012
- 2012-03-14 CN CN201210067438.2A patent/CN103311123B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080254627A1 (en) * | 2005-06-09 | 2008-10-16 | Micron Technology, Inc. | Method for adjusting feature size and position |
| US20070065990A1 (en) * | 2005-09-16 | 2007-03-22 | Bart Degroote | Recursive spacer defined patterning |
| US20100167211A1 (en) * | 2008-12-30 | 2010-07-01 | Hynix Semiconductor Inc. | Method for forming fine patterns in a semiconductor device |
| US20110151668A1 (en) * | 2009-12-23 | 2011-06-23 | Tang Sanh D | Pitch division patterning techniques |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016015416A1 (en) * | 2014-07-31 | 2016-02-04 | 上海集成电路研发中心有限公司 | Method for cutting line top end of fin structure for double-pattern fin field effect transistor |
| CN105428317A (en) * | 2014-09-12 | 2016-03-23 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105470137A (en) * | 2014-09-12 | 2016-04-06 | 中国科学院微电子研究所 | Fin etching method |
| CN105428317B (en) * | 2014-09-12 | 2018-09-18 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN104528634A (en) * | 2014-12-16 | 2015-04-22 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| CN104528634B (en) * | 2014-12-16 | 2017-01-18 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| CN105762071B (en) * | 2014-12-17 | 2019-06-21 | 中国科学院微电子研究所 | Fin field effect transistor and manufacturing method of fin thereof |
| CN105762071A (en) * | 2014-12-17 | 2016-07-13 | 中国科学院微电子研究所 | Fin field effect transistor and manufacturing method of fin thereof |
| CN105762186A (en) * | 2014-12-17 | 2016-07-13 | 中国科学院微电子研究所 | Fin field effect transistor, fin structure and manufacturing method thereof |
| WO2016197766A1 (en) * | 2015-06-09 | 2016-12-15 | 华为技术有限公司 | Method for manufacturing nanowire |
| CN108807170A (en) * | 2018-06-11 | 2018-11-13 | 中国科学院微电子研究所 | Method for manufacturing nano wire |
| CN108807170B (en) * | 2018-06-11 | 2021-10-22 | 中国科学院微电子研究所 | Method for manufacturing nano wire |
| CN112967986A (en) * | 2020-10-19 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Transfer component, preparation method thereof and transfer head |
| CN112967986B (en) * | 2020-10-19 | 2022-06-21 | 重庆康佳光电技术研究院有限公司 | Transfer component, preparation method thereof and transfer head |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103311123B (en) | 2016-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10510853B2 (en) | FinFET with two fins on STI | |
| CN103311123B (en) | Semiconductor device manufacturing method | |
| US8053299B2 (en) | Method of fabrication of a FinFET element | |
| US8716156B1 (en) | Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process | |
| US8551833B2 (en) | Double gate planar field effect transistors | |
| TWI782150B (en) | Field effect transistor, system on chip, and method of manufacturing the same | |
| TWI688044B (en) | Semiconductor device, fin field-effect transistor device and method for fabricating the same | |
| US9728602B2 (en) | Variable channel strain of nanowire transistors to improve drive current | |
| JP2011507231A (en) | Silicon-germanium nanowire structure and method for forming the same | |
| WO2012159424A1 (en) | Wet etching-based method for producing silicon nanowire field effect transistor | |
| WO2012159329A1 (en) | Method for manufacturing surround-gate silicon nanowire transistor with air as sidewall | |
| WO2019095874A1 (en) | Field effect transistor structure and preparation method therefor | |
| CN103560153A (en) | Tunneling field effect transistor and preparation method thereof | |
| CN102082096A (en) | Method for preparing Ge or SiGe nanowire field effect transistor | |
| US9620589B2 (en) | Integrated circuits and methods of fabrication thereof | |
| CN102832135A (en) | Method for preparing FinFET on germanium and III-V semiconductor material substrate | |
| CN106558489A (en) | Nanowire structure, fence nanowire device and manufacturing method thereof | |
| CN102569405B (en) | Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor | |
| CN107424994A (en) | Ring grid III-V quantum well transistors and germanium nodeless mesh body pipe and its manufacture method | |
| CN113178490A (en) | Tunneling field effect transistor and preparation method thereof | |
| CN106981422B (en) | Vertical TFET and manufacturing method thereof | |
| CN104517839A (en) | Fin-shaped field effect transistor structure and preparation method thereof | |
| CN102544105B (en) | Tunnel transistor with quasi-coaxial cable structure and forming method thereof | |
| CN103367432A (en) | Multi-grid field effect transistor and manufacturing method thereof | |
| CN106558603A (en) | Nanowire structure, fence nanowire device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |