CN105762186A - Fin field-effect transistor, fin structure and manufacturing method thereof - Google Patents
Fin field-effect transistor, fin structure and manufacturing method thereof Download PDFInfo
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- CN105762186A CN105762186A CN201410789715.XA CN201410789715A CN105762186A CN 105762186 A CN105762186 A CN 105762186A CN 201410789715 A CN201410789715 A CN 201410789715A CN 105762186 A CN105762186 A CN 105762186A
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Abstract
The invention provides a fin structure, which comprises fins arranged on a substrate. The cross sections of the upper parts of the fins are substantially rectangular, and the cross sections of the lower parts of the fins are substantially trapezoidal. According to the technical scheme of the invention, the upper parts of the fins are rectangular in morphology, and the lower parts of the fins are trapezoidal in morphology. Meanwhile, the upper parts of the fins form a channel region and the formation of other structures can be better controlled based on the rectangular morphology. The formation of an isolation structure is easier to realize based on the lower trapezoidal morphology of the fins. Therefore, the device performance is conveniently controlled and improved.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of fin formula field effect transistor, fin structure and manufacture method thereof.
Background technology
Highly integrated along with semiconductor device, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more notable, even become the leading factor affecting device performance, this phenomenon is referred to as short-channel effect.Short-channel effect can worsen the electric property of device, as caused threshold voltage of the grid decline, power consumption to increase and degradation problem under signal to noise ratio.
In order to overcome short-channel effect, propose the three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-FET is the transistor with fin channel structure, several surfaces of this kind of thin fin of devices use are as raceway groove, such that it is able to prevent the short-channel effect in conventional transistor, operating current can be increased simultaneously.
In the manufacturing process of fin formula field effect transistor, the manufacture of fin is unusual part and parcel, and the pattern of current fin is mainly trapezoidal, and this structural manufacturing process is simple and is beneficial to the filling of follow-up isolation, but is unfavorable for control and the lifting of device performance.
Summary of the invention
It is an object of the invention to overcome deficiency of the prior art, it is provided that a kind of fin formula field effect transistor, fin structure and manufacture method thereof, be beneficial to control and the lifting of device performance.
For achieving the above object, the technical scheme is that
A kind of fin structure, including: the fin on substrate, the cross section on the top of described fin is essentially rectangular, and the cross section of the bottom of described fin is substantially trapezoidal.
Optionally, the altitude range on the top of described fin is 30-40 nanometer.
Additionally, present invention also offers a kind of fin formula field effect transistor, including any of the above-described fin structure.
Additionally, present invention also offers the manufacture method of a kind of fin structure, including:
Semiconductor substrate is provided；
Substrate is formed mask layer；
Under the sheltering of mask layer, carrying out the first etching of substrate, to form the top of fin, the cross section on the top of described fin is essentially rectangular；
Under the sheltering of mask layer, carrying out the second etching of substrate, to form the bottom of fin, the cross section of the bottom of described fin is substantially trapezoidal.
Optionally, the step forming the first mask on substrate includes:
Substrate deposits the first hard mask layer and amorphous silicon layer successively；
Patterning amorphous silicon layer；
With amorphous silicon layer for sheltering, pattern the first hard mask layer；
Remove amorphous silicon layer.
Optionally, substrate is silicon substrate, and the step carrying out the first etching includes:: adopt the lithographic method of RIE, adopt SF6As main etching gas, carrying out the etching of substrate, to form the top of fin, the cross section on the top of described fin is essentially rectangular.
Optionally, substrate is silicon substrate, and the step carrying out the second etching includes: adopt the lithographic method of RIE, adopts HBr and O2As main etching gas, proceeding the etching of substrate, to form the bottom of fin, the cross section of the bottom of described fin is substantially trapezoidal.
Optionally, the altitude range on the top of described fin is 30-40 nanometer.
Additionally, present invention also offers the manufacture method of a kind of fin formula field effect transistor, adopt the fin structure that any of the above-described method is formed.
The fin formula field effect transistor of the present invention and the manufacture method of fin structure thereof, the top of fin adopts the pattern of rectangle, bottom adopts trapezoidal pattern, top is channel region, the pattern adopting rectangle is more easily controlled the formation of other structures of device, and the trapezoidal pattern of bottom is easier to be formed isolation structure, it is beneficial to control and the lifting of device performance.
Accompanying drawing explanation
In order to be illustrated more clearly that technical scheme of the invention process, the accompanying drawing used required in embodiment will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the manufacture method flow chart of fin structure according to embodiments of the present invention；
Fig. 2-Fig. 9 manufactures the device cross section structure schematic diagram in each manufacture process of fin formula field effect transistor according to embodiments of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization when without prejudice to intension of the present invention, and therefore the present invention is not by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; representing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
The present invention proposes a kind of fin structure, and with reference to shown in Fig. 9, including the fin 140 on substrate 100, the cross section of the top 140-1 of described fin 140 is essentially rectangular, and the cross section of the bottom 140-2 of described fin 140 is substantially trapezoidal.
In an embodiment of the present invention, the altitude range of the top 140-1 of this fin can be 30-40 nanometer, the altitude range of the bottom of this fin can be 60-70 nanometer, and the top of fin connects with bottom the structure being integrated, and the end face equidimension of the bottom surface on top and bottom coincides together.
Additionally, the present invention also proposes the fin formula field effect transistor based on above-mentioned fin structure, above-mentioned fin structure forms other structures of device.
In the present invention, the top of fin adopts the pattern of rectangle, and bottom adopts trapezoidal pattern, top is channel region, the pattern adopting rectangle is more easily controlled the formation of other structures of device, and the trapezoidal pattern of bottom is easier to be formed isolation structure, is beneficial to control and the lifting of device performance.
Above the fin structure of the present invention is described, in addition, the invention allows for the manufacture method of above-mentioned fin structure, in order to be better understood from technical scheme and technique effect, be described in detail below with reference to flow chart Fig. 1 with to the manufacture method of specific embodiment.
First, in step S01, it is provided that Semiconductor substrate 100, with reference to shown in Fig. 2.
In embodiments of the present invention, described Semiconductor substrate 100 can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator) etc..Described Semiconductor substrate can also be the substrate including other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it is also possible to for laminated construction, for instance Si/SiGe etc., can also be other epitaxial structures, for instance SGOI (silicon germanium on insulator) etc..In the present embodiment, described Semiconductor substrate is body silicon substrate.
Then, in step S02, substrate forms mask layer 110, with reference to shown in Fig. 7.
In an embodiment of the present invention, this mask layer 110 can be the mask materials such as hard mask or photoresist, in the present embodiment, amorphous silicon layer is adopted to be transferred to by etching pattern in hard mask, to improve the roughness (LER of pattern line, LineEdgeRoughens), to guarantee the stability of the performance of device and the duty being subsequently formed.
In the present embodiment, concrete, first, substrate deposits the first hard mask 110, as in figure 2 it is shown, this first hard mask 110 can be silicon dioxide, silicon nitride, silicon oxynitride etc. or their lamination, thickness can beIn a specific embodiment, the first hard mask 110 is silicon dioxide.
Then, deposition of amorphous silicon layer (a-Si) 120 on the first hard mask 110, as it is shown on figure 3, the thickness of amorphous silicon layer 120 can be
Then, carry out the patterning of amorphous silicon layer 120, concrete, on amorphous silicon layer 120, first form photoresist layer 130, as shown in Figure 4, then, with photoresist layer 130 for sheltering, adopting the method patterning amorphous silicon layer 120 of RIE (reactive ion etching), etching stopping is on the first hard mask layer 110.Then, photoresist layer 130 is removed.
Then, with amorphous silicon layer 120 for sheltering, the method patterning first hard mask 110 of RIE (reactive ion etching) can be adopted, as shown in Figure 6, the pattern of amorphous silicon layer 120 is transferred to the first hard mask layer 110, etching stopping is on a silicon substrate, experiment proves, by adding amorphous silicon layer 120, then, shift pattern to the first hard mask layer of its lower floor by amorphous silicon layer, the roughness (LER of lower pattern lines can be effectively improved, LineEdgeRoughens), to guarantee the stability of the performance of device and the duty being subsequently formed.After patterning, amorphous silicon layer 120 is removed.
Then, in step S03, under the sheltering of mask layer 110, carrying out the first etching of substrate, to form the top 140-1 of fin, the cross section of the top 140-1 of described fin is essentially rectangular, with reference to shown in Fig. 7.
In an embodiment of the present invention, it is possible to adopt the lithographic method of RIE (reactive ion etching), the first etching of substrate is carried out, the top 140-1 of the fin that Formation cross-section is essentially rectangular, cross section is essentially rectangular, and namely etched surface is substantially vertical, in the particular embodiment, it is possible to adopt SF6As main etching gas, etching depth can be 30-40 nanometer.
Then, in step S04, under the sheltering of mask layer 110, carrying out the second etching of substrate, to form the bottom 140-2 of fin, the cross section of the bottom 140-2 of described fin is substantially trapezoidal, with reference to shown in Fig. 9.
In an embodiment of the present invention, it is possible to adopt the lithographic method of RIE, the second etching of substrate is carried out, the bottom 140-2 of the fin that Formation cross-section is substantially trapezoidal, the substantially trapezoidal inclined-plane that namely etched surface is essentially up-narrow and down-wide, cross section, in the particular embodiment, it is possible to adopt HBr and O2As main etching gas, etching depth can be 60-70 nanometer.
So far, the fin 140 of the embodiment of the present invention is defined, then, it is possible to complete the processing of subsequent device.
In the particular embodiment, after above-mentioned formation fin, it is possible to form isolation structure between fin, fin is formed gate dielectric layer and grid, and forms source-drain area at the two ends of fin, and be subsequently formed interlayer dielectric layer and contact and interconnection structure etc..
The above, be only presently preferred embodiments of the present invention, and the present invention not does any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Any those of ordinary skill in the art, without departing from, under technical solution of the present invention ambit, may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (9)
1. a fin structure, it is characterised in that including: the fin on substrate, the cross section on the top of described fin is essentially rectangular, and the cross section of the bottom of described fin is substantially trapezoidal.
2. fin structure according to claim 1, it is characterised in that the altitude range on the top of described fin is 30-40 nanometer.
3. a fin formula field effect transistor, it is characterised in that include fin structure as claimed in claim 1 or 2.
4. the manufacture method of a fin structure, it is characterised in that including:
Semiconductor substrate is provided；
Substrate is formed mask layer；
Under the sheltering of mask layer, carrying out the first etching of substrate, to form the top of fin, the cross section on the top of described fin is essentially rectangular；
Under the sheltering of mask layer, carrying out the second etching of substrate, to form the bottom of fin, the cross section of the bottom of described fin is substantially trapezoidal.
5. manufacture method according to claim 4, it is characterised in that the step forming the first mask on substrate includes:
Substrate deposits the first hard mask layer and amorphous silicon layer successively；
Patterning amorphous silicon layer；
With amorphous silicon layer for sheltering, pattern the first hard mask layer；
Remove amorphous silicon layer.
6. manufacture method according to claim 4, it is characterised in that substrate is silicon substrate, and the step carrying out the first etching includes: adopt the lithographic method of RIE, adopts SF6As main etching gas, carrying out the etching of substrate, to form the top of fin, the cross section on the top of described fin is essentially rectangular.
7. manufacture method according to claim 4, it is characterised in that substrate is silicon substrate, and the step carrying out the second etching includes: adopt the lithographic method of RIE, adopts HBr and O2As main etching gas, proceeding the etching of substrate, to form the bottom of fin, the cross section of the bottom of described fin is substantially trapezoidal.
8. manufacture method according to claim 4, it is characterised in that the altitude range on the top of described fin is 30-40 nanometer.
9. the manufacture method of a fin formula field effect transistor, it is characterised in that adopt the fin structure that the method as according to any one of claim 4-8 is formed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410789715.XA CN105762186A (en) | 2014-12-17 | 2014-12-17 | Fin field-effect transistor, fin structure and manufacturing method thereof |
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| CN201410789715.XA CN105762186A (en) | 2014-12-17 | 2014-12-17 | Fin field-effect transistor, fin structure and manufacturing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070066018A1 (en) * | 2003-02-19 | 2007-03-22 | Samsung Electronics Co., Ltd. | Methods of fabricating vertical channel field effect transistors having insulating layers thereon |
| CN103296085A (en) * | 2012-02-29 | 2013-09-11 | 台湾积体电路制造股份有限公司 | Fin profile structure and method of making same |
| CN103311123A (en) * | 2012-03-14 | 2013-09-18 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103515282A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field-effect transistor and forming method thereof |
| CN104517839A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Fin-shaped field effect transistor structure and preparation method thereof |
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- 2014-12-17 CN CN201410789715.XA patent/CN105762186A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070066018A1 (en) * | 2003-02-19 | 2007-03-22 | Samsung Electronics Co., Ltd. | Methods of fabricating vertical channel field effect transistors having insulating layers thereon |
| CN103296085A (en) * | 2012-02-29 | 2013-09-11 | 台湾积体电路制造股份有限公司 | Fin profile structure and method of making same |
| CN103311123A (en) * | 2012-03-14 | 2013-09-18 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103515282A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field-effect transistor and forming method thereof |
| CN104517839A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Fin-shaped field effect transistor structure and preparation method thereof |
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Application publication date: 20160713 |
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