CN106252228A - Composite fin, semiconductor device and forming method thereof - Google Patents
Composite fin, semiconductor device and forming method thereof Download PDFInfo
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- CN106252228A CN106252228A CN201510320225.XA CN201510320225A CN106252228A CN 106252228 A CN106252228 A CN 106252228A CN 201510320225 A CN201510320225 A CN 201510320225A CN 106252228 A CN106252228 A CN 106252228A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000002131 composite material Substances 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 239000000463 material Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 24
- 150000001875 compounds Chemical class 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 119
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000011435 rock Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for forming a composite fin, which comprises the following steps: providing a substrate; forming a first side wall mask on the substrate through side wall pattern transfer; forming a second side wall mask on the side wall of the first side wall mask through side wall pattern transfer; etching the substrate by taking the first side wall mask and the second side wall mask as masks to form fins, removing the first side wall mask, and etching the fins below the first side wall mask to form openings; and selectively growing a second semiconductor layer and a third semiconductor layer in sequence in the opening to form a composite fin, wherein the second semiconductor layer has a higher carrier mobility than the fin and the third semiconductor layer. The method improves the carrier mobility of the composite fin, avoids the problems of interface states and defects between the second semiconductor layer and the material of the gate dielectric layer, and improves the performance of the device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly to one be combined fin, semiconductor device and
Forming method.
Background technology
Highly integrated along with semiconductor device, MOSFET channel length constantly shortens, a series of
In MOSFET long raceway groove model, negligible effect becomes more notable, even becomes and affects device
The leading factor of energy, this phenomenon is referred to as short-channel effect.Short-channel effect can deteriorate the electrical property of device
Can, as caused threshold voltage of the grid decline, power consumption to increase and degradation problem under signal to noise ratio.
In order to overcome short-channel effect, it is proposed that the three-dimensional device of fin formula field effect transistor (Fin-FET)
Structure, Fin-FET is the transistor with fin channel structure, several tables of this kind of thin fin of devices use
Face is as raceway groove, such that it is able to prevent the short-channel effect in conventional transistor, can increase work electricity simultaneously
Stream.
In the manufacturing process of fin formula field effect transistor, the manufacture of fin is unusual part and parcel, along with right
What integrated level required improves constantly, it is desirable to fin raceway groove can use the material of high mobility, but, current height
The fin channel material of mobility, such as Presence of an interface defect and the problem of interfacial state between Ge, and gate dielectric material.
Summary of the invention
The purpose of the present invention is intended at least solve above-mentioned technological deficiency, it is provided that a kind of compound fin, quasiconductor
Device and forming method thereof, promotes the carrier mobility of fin raceway groove, and improves fin and gate dielectric layer
Interfacial state and boundary defect.
The invention provides the forming method of a kind of compound fin, including step:
Substrate is provided；
Shifted by side wall pattern, substrate is formed the first side wall mask；
Shifted by side wall pattern, the sidewall of the first side wall mask is formed the second side wall mask；
With the first side wall mask and the second side wall mask for sheltering, carry out the etching of substrate, to form fin,
And remove the first side wall mask, and etch the fin under the first side wall mask, to form opening；
Selective growth the second semiconductor layer and the 3rd semiconductor layer the most successively, compound to be formed
Fin, wherein, compared to fin and the 3rd semiconductor layer, described second semiconductor layer has higher current-carrying
Transport factor.
Optionally, the step forming fin and opening includes:
With the first side wall mask and the second side wall mask for sheltering, carry out the etching of substrate, to form fin；
Carry out thermal oxidation technology, then remove the first side wall mask
Etch the fin under the first side wall masked areas, to form opening.
Optionally, the bottom surface of described opening is higher than the bottom surface of fin.
Optionally, described fin and the 3rd semiconductor layer are silicon, and described second semiconductor layer is Ge or III-V
Race's semi-conducting material.
Additionally, present invention also offers the forming method of compound fin, including:
Substrate is provided；
Shifted by side wall pattern, substrate is formed the first side wall mask；
Shifted by side wall pattern, the sidewall of the first side wall mask is formed the second side wall mask；
Remove the first side wall mask, with the second side wall mask for sheltering, carry out the etching of substrate, with shape
Become the opening in fin and fin；
Selective growth the second semiconductor layer and the 3rd semiconductor layer the most successively, compound to be formed
Fin, wherein, compared to fin and the 3rd semiconductor layer, described second semiconductor layer has higher current-carrying
Transport factor.
Optionally, selective growth the second semiconductor layer and the step of the 3rd semiconductor layer the most successively
Suddenly include:
Form the first packed layer in the opening；
Cover the substrate outside fin, to form the second packed layer；
Remove the first packed layer；
Epitaxial growth the second semiconductor layer and the 3rd semiconductor layer successively.
Optionally, described fin and the 3rd semiconductor layer are silicon, and described second semiconductor layer is Ge or III-V
Race's semi-conducting material.
Additionally, present invention also offers the forming method of a kind of semiconductor device, use any of the above-described side
The compound fin that method is formed forms semiconductor device.
Additionally, present invention also offers a kind of compound fin, including:
Substrate；
Fin on substrate, is formed with opening in described fin；
The second semiconductor layer in described opening and the 3rd semiconductor layer on the second semiconductor layer, wherein,
Compared to fin and the 3rd semiconductor layer, the second semiconductor layer has higher carrier mobility.
Optionally, the bottom surface of described opening flushes with the bottom surface of fin.
Optionally, the bottom surface of described opening is higher than the bottom surface of fin.
Optionally, described fin and the 3rd semiconductor layer are silicon, and described second semiconductor layer is Ge or III-V
Race's semi-conducting material.
Additionally, present invention also offers a kind of semiconductor device, including any of the above-described compound fin.
The compound fin of embodiment of the present invention offer, semiconductor device and forming method thereof, by twice side
Wall Pattern transfer techniques, forms the first side wall mask and the second side wall mask respectively, by these two sides
Wall mask forms the opening in fin and fin, and then, selective growth the second half is led the most successively
Body layer and the 3rd semiconductor layer, thus in defining fin, it is formed with the second semiconductor layer and the 3rd quasiconductor
The compound fin of layer, wherein, second semiconductor layer with more high carrier mobility is besieged,
Improve the carrier mobility of compound fin, simultaneously, it is to avoid the second semiconductor layer and gate dielectric layer material
Interfacial state between material and the problem of defect, improve the performance of device.
Accompanying drawing explanation
Present invention aspect that is above-mentioned and/or that add and advantage are from retouching embodiment below in conjunction with the accompanying drawings
Will be apparent from easy to understand in stating, wherein:
Fig. 1 shows the schematic flow sheet of the forming method of the compound fin of according to embodiments of the present invention；
Fig. 2-9A shows that the method for according to embodiments of the present invention forms each of compound fin and manufactured
Device architecture schematic diagram in journey, including plan structure schematic diagram and plan structure schematic diagram AA to
Cross-sectional view；
Figure 10 shows the schematic flow sheet of the forming method of the compound fin of according to embodiments of the present invention two；
Figure 11-19A shows that the method for according to embodiments of the present invention two forms each manufacture of compound fin
During device architecture schematic diagram, including plan structure schematic diagram and the AA of plan structure schematic diagram
To cross-sectional view.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, the most right
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention
Other can also be used to be different from alternate manner described here implement, those skilled in the art can be not
Doing similar popularization in the case of running counter to intension of the present invention, therefore the present invention is not by following public specific embodiment
Restriction.
Secondly, the present invention combines schematic diagram and is described in detail, when describing the embodiment of the present invention in detail, for ease of
Illustrate, represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is only
Being example, it should not limit the scope of protection of the invention at this.Additionally, should comprise in actual fabrication length,
Width and the three-dimensional space of the degree of depth.
In the present invention, it is proposed that the forming method of a kind of compound fin, in the method, both sides are passed through
Side wall pattern shifts, and forms the first and second side wall masks respectively, utilizes the two side wall mask to be formed
Opening in fin and fin, then, selective epitaxial has higher carrier than fin the most successively
Second semiconductor layer of mobility and there is the of lower carrier mobility than the second semiconductor layer
Three semiconductor layers, thus formed and surround the compound fin having more high carrier mobility, on the one hand improve
The carrier mobility that fin is overall, simultaneously, it is to avoid and interfacial state between gate dielectric layer material and scarce
The problem fallen into, thus improve the performance of device.
In order to be better understood from technical scheme and technique effect, below with reference to flow chart pair
Specific embodiment is described in detail.
Embodiment one
With reference to shown in Fig. 1, in this embodiment, in step S101, it is provided that substrate 100, with reference to figure
Shown in 1 (top view) and Figure 1A (AA of Fig. 1 is to sectional view).
In an embodiment of the present invention, described substrate 100 can select tool between gate dielectric layer material
There is the material of preferable interfacial state and fewer defect, can be single-layer substrate or laminated substrate, preferably
In embodiment, described substrate 100 can be Si substrate or SOI (silicon-on-insulator, Silicon On
Insulator), it has relatively low cost and is prone to integrated with existing manufacturing process.In other embodiments,
Described substrate 100 can also be the substrate including other elemental semiconductors or compound semiconductor, such as
GaAs, InP or SiC etc., it is also possible to for laminated construction, such as Si/SiGe etc., it is also possible to outside other
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, described substrate 100 is
Body silicon substrate.
In step S102, shifted by side wall pattern, form the first side wall mask 106 on the substrate 100,
With reference to shown in Fig. 2 (top view) and Fig. 2 A (AA of Fig. 2 is to sectional view).
In the present embodiment, concrete, first, form cap rock 102, described lid on the substrate 100
Layer 102 can be such as silicon oxide, plays protection substrate 100 and the etching stopping as subsequent technique
The effect of layer.
Then, carrying out side wall pattern transfer for the first time, concrete, first on cap rock 102, deposit is removed
Layer, this removal layer is for forming the first side wall mask, and removing layer can be such as polysilicon, then,
Perform etching, form the removal layer 104 of patterning.Then, deposit the first spacer material, such as may be used
Think silicon nitride, and perform etching, such as RIE (reactive ion etching), thus, removing layer 104
Sidewall on form the first side wall mask 106, as best seen in figs. 2 and 2, then, it is possible to use wet
Method etches, and removes this removal layer 104, thus, complete side wall pattern transfer for the first time, form first
Side wall mask 106.
In step S103, shifted by side wall pattern, the sidewall of the first side wall mask 106 is formed
Second side wall mask 108, with reference to Fig. 3 (top view) and Fig. 3 A (AA of Fig. 3 is to sectional view)
Shown in.
In this step, second time side wall pattern transfer is carried out, in this pattern transfer, with first
Side wall mask 106 is substrate, carries out side wall pattern transfer, concrete, first deposits the second spacer material,
Can be such as silicon oxide, and perform etching, such as RIE (reactive ion etching), thus,
The second side wall mask 108 is formed, as shown in Fig. 3 and Fig. 3 A on the sidewall of one side wall mask 106.The
The width sum of the width of one side wall mask 106 and the first side wall mask 108 of its both sides determines
The width of fin to be formed.
In step S104, with the first side wall mask 106 and the second side wall mask 108 for sheltering, carry out
The etching of substrate 100, to form fin 110, and removes the first side wall mask 106, and etches first
Fin 110 under side wall mask, to form opening 114, with reference to Fig. 7 (top view) and Fig. 7 A (Fig. 7
AA to sectional view) shown in.
In this step, defining the opening in fin and fin, opening is used for the higher current-carrying of selective epitaxial
The semi-conducting material of transport factor, to improve the performance of fin raceway groove.
Concrete, first, with the first side wall mask 106 and the second side wall mask 108 for sheltering, enter
Row cap rock 102 and the etching of substrate 100, after being etched to the substrate 100 of predetermined thickness, at substrate
Fin 110 is defined, such as Fig. 4 (top view) and Fig. 4 A (AA of Fig. 4 is to sectional view) institute in 100
Show, under the first side wall mask 106 and the second side wall mask 108 of a cincture, define ring
Around the pattern of fin, in the pattern of the fin of a cincture, there are two adjacent fins, in follow-up shape
When becoming device, the fin of cincture is cut out, forms two adjacent fins.
Then, carrying out thermal oxidation technology, so, at the sidewall of fin 110, and fin 110 both sides are sudden and violent
Oxide layer 112 is defined, such as Fig. 5 (top view) and Fig. 5 A (AA of Fig. 5 on the substrate 100 of dew
To sectional view) shown in, this oxide layer 112 is at the etching of follow-up opening and selective growth semiconductor layer
Processing step in, play the effect of mask.
Then, the first side wall mask 106 is removed, wet etching can be used, remove this first side
Wall mask, as shown in Fig. 6 (top view) and Fig. 6 A (AA of Fig. 6 is to sectional view).
Then, with the second side wall mask 108 and oxide layer 112 for sheltering, carry out cap rock 102 and
The etching of fin 110, forms opening 114, such as Fig. 7 (top view) and Fig. 7 A (Fig. 7 in fin 100
AA to sectional view) shown in, the degree of depth of etching can be determined as required, i.e. opening 114 is deep
Degree, in the present embodiment, the bottom surface of described opening 114 is formed higher than the bottom surface of fin 110, i.e. opening
Top at fin.
In step S105, selective growth the second semiconductor layer 120 and the 3rd successively in opening 114
Semiconductor layer 130, to form compound fin, wherein, compared to fin 110 and the 3rd semiconductor layer 130,
Described second semiconductor layer 120 has a higher carrier mobility, with reference to Fig. 8 (top view) and
Shown in Fig. 8 A (AA of Fig. 8 is to sectional view).
In the present embodiment, the lateral wall of fin 110 is coated with oxide layer 112 and fin 110 overlying
It is stamped the second side wall mask 108, when carrying out epitaxial growth (epi) technique, only selective along opening
Inwall grow.Concrete, first, epitaxial growth the second semiconductor layer 120, these are the second half years old
Conductor layer 120 selects the semi-conducting material than fin 110 with higher carrier mobility, this enforcement
In example, the second semiconductor layer 120 is Ge or III-V group semi-conductor material.Then, extension is continued raw
Long 3rd semiconductor layer 130, the 3rd semiconductor layer 130 selects to be had relatively between gate dielectric layer material
Good interfacial state and the material of fewer defect, can select the material identical with fin, in the present embodiment, the
Three semiconductor layers 130 are silicon, so, define the second semiconductor layer and second included in fin, fin
The compound fin of the 3rd semiconductor layer composition on semiconductor layer, in this compound fin, has high current-carrying
Second semiconductor layer of transport factor is surrounded by fin and the 3rd semiconductor layer, so, improves fin overall
Carrier mobility while, it is to avoid and the asking of interfacial state between gate dielectric layer material and defect
Topic, thus improve the performance of device.
Then, oxide layer 112, cap rock 102 and the second side wall mask 108 are all removed, so far,
Define the compound fin of the embodiment of the present invention on the substrate 100, such as Fig. 9 (top view) and Fig. 9 A (figure
The AA of 9 is to sectional view) shown in, this compound fin includes: substrate 100；Fin 110 on substrate 100,
Described fin 100 is formed with opening；The second semiconductor layer 120 and the second quasiconductor in described opening
The 3rd semiconductor layer 130 on layer 120, wherein, compared to fin 110 and the 3rd semiconductor layer 130,
Second quasiconductor 120 layers has higher carrier mobility.In this embodiment, the end of described opening
Face is higher than the bottom surface of fin, and the bottom surface of the i.e. second semiconductor layer 120 is higher than the bottom surface of fin 110.
Then, can carry out the processing of subsequent device on this compound fin, formation comprises this and is combined
The semiconductor device of fin, this device has higher carrier mobility and more preferable interfacial characteristics, carries
The high performance of device.
Embodiment two
With reference to shown in Figure 10, in this embodiment, in step S201, it is provided that substrate 100, with reference to figure
Shown in 11 (top views) and Figure 11 A (AA of Figure 11 is to sectional view).
In an embodiment of the present invention, described substrate 100 can select tool between gate dielectric layer material
There is the material of preferable interfacial state and fewer defect, can be single-layer substrate or laminated substrate, preferably
In embodiment, described substrate 100 can be Si substrate or SOI (silicon-on-insulator, Silicon On
Insulator), it has relatively low cost and is prone to integrated with existing manufacturing process.In other embodiments,
Described substrate 100 can also be the substrate including other elemental semiconductors or compound semiconductor, such as
GaAs, InP or SiC etc., it is also possible to for laminated construction, such as Si/SiGe etc., it is also possible to outside other
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, described substrate 100 is
Body silicon substrate.
In step S202, shifted by side wall pattern, form the first side wall mask 106 on the substrate 100,
With reference to shown in Figure 12 (top view) and Figure 12 A (AA of Figure 12 is to sectional view).
In the present embodiment, concrete, first, form cap rock 102, described lid on the substrate 100
Layer 102 can be such as silicon oxide, plays protection substrate 100 and the etching stopping as subsequent technique
The effect of layer.
Then, carrying out side wall pattern transfer for the first time, concrete, first on cap rock 102, deposit is removed
Layer, this removal layer is for forming the first side wall mask, and removing layer can be such as polysilicon, then,
Perform etching, form the removal layer 104 of patterning.Then, deposit the first spacer material, such as may be used
Think silicon nitride, and perform etching, such as RIE (reactive ion etching), thus, removing layer 104
Sidewall on form the first side wall mask 106, as shown in Figure 12 and Figure 12 A, then, it is possible to use
Wet etching, removes this removal layer 104, thus, complete for the first time side wall pattern transfer, form the
One side wall mask 106.
In step S203, shifted by side wall pattern, the sidewall of the first side wall mask 106 is formed
Second side wall mask 108, with reference to Figure 12 (top view) and Figure 12 A (AA of Figure 12 is to sectional view)
Shown in.
In this step, second time side wall pattern transfer is carried out, in this pattern transfer, with first
Side wall mask 106 is substrate, carries out side wall pattern transfer, concrete, first deposits the second spacer material,
Can be such as silicon oxide, and perform etching, such as RIE (reactive ion etching), thus,
The second side wall mask 108 is formed, as shown in Figure 12 and Figure 12 A on the sidewall of one side wall mask 106.
The width sum of the width of the first side wall mask 106 and the first side wall mask 108 of its both sides determines
The width of fin to be formed.
In step S204, remove the first side wall mask 106, with the second side wall mask 108 for sheltering,
Carry out the etching of substrate 100, to form the opening 114 in fin 110 and fin 110, with reference to Figure 14
Shown in (top view) and Figure 14 A (AA of Figure 14 is to sectional view).
Concrete, first, remove the first side wall mask 106, wet etching can be used to remove first
Side wall mask 106, as shown in Figure 13 (top view) and Figure 13 A (AA of Figure 13 is to sectional view).
Then, the second side wall mask 108, for sheltering, carries out cap rock 102 and the etching of substrate 100, etching
To the substrate 100 of part predetermined thickness, define fin 110 in the substrate, meanwhile, define fin
Opening 114 between 110, this fin 110 is the fin of part, and this opening 114 concurrently forms with fin 110,
Opening 114 flushes bottom fin 110 substantially, has substantially the same height, such as Figure 14 and Tu
Shown in 14A.With embodiment one, under the second side wall mask 108, define the pattern of the fin of cincture,
In the pattern of the fin of a cincture, there are two adjacent fins, when being subsequently formed device, by ring
Around fin be cut out, form two adjacent fins.
In step S205, selective growth the second semiconductor layer 120 and the 3rd successively in opening 114
Semiconductor layer 130, to form compound fin, wherein, compared to fin 110 and the 3rd semiconductor layer 130,
Described second semiconductor layer 120 has a higher carrier mobility, with reference to Figure 18 (top view) and
Shown in Figure 18 A (AA of Figure 18 is to sectional view).
In this example, concrete, first, opening 114 is filled the first packed layer 107, should
First packed layer 107 can be such as silicon nitride, such as Figure 15 (top view) and Figure 15 A (Figure 15
AA to sectional view) shown in.Then, carrying out the filling of the second packed layer, the second packed layer is such as
Can be silicon oxide, and planarize, thus cover the substrate 100 outside fin, to form second
Packed layer 112, as shown in Figure 16 (top view) and Figure 16 A (AA of Figure 16 is to sectional view).
Then, remove the first packed layer 107, wet etching can be used to remove this first packed layer 107, as
Shown in Figure 17 (top view) and Figure 17 A (AA of Figure 17 is to sectional view), remove the first packed layer
After 107, opening 114 is discharged again, and exposes outside the lateral wall of fin 110 and fin 110
Substrate 100 be covered with the second packed layer 107, it is thereby possible to select property in opening 114
Semi-conducting material needed for epitaxial growth.First, epitaxial growth the second semiconductor layer 120, this is second years old
Semiconductor layer 120 selects the semi-conducting material than fin 110 with higher carrier mobility, this reality
Executing in example, the second semiconductor layer 120 is Ge or III-V group semi-conductor material.Then, extension is continued
Growth regulation three semiconductor layer 130, the 3rd semiconductor layer 130 selects to be had between gate dielectric layer material
Preferably interfacial state and the material of fewer defect, can select the material identical with fin, in the present embodiment,
3rd semiconductor layer 130 is silicon, so, defines the second semiconductor layer included in fin, fin and
The compound fin of the 3rd semiconductor layer composition on two semiconductor layers, in this compound fin, has high load
Second semiconductor layer of stream transport factor is surrounded by fin and the 3rd semiconductor layer, so, improves fin whole
While the carrier mobility of body, it is to avoid and interfacial state between gate dielectric layer material and defect
Problem, thus improve the performance of device.
Then, cap rock 102 and the second side wall mask 108 are all removed, meanwhile, remove part thick
Second packed layer 112 of degree, remaining second packed layer is the isolation structure 116 between fin, such as figure
Shown in 19 (top views) and Figure 19 A (AA of Figure 19 is to sectional view).
So far, the compound fin of the embodiment of the present invention is defined on the substrate 100, such as Figure 19 and Figure 19 A
Shown in, this compound fin includes: substrate 100；Fin 110 on substrate 100, is formed in described fin 100
There is opening；The second semiconductor layer 120 in described opening and the 3rd half on the second semiconductor layer 120
Conductor layer 130, wherein, compared to fin 110 and the 3rd semiconductor layer 130, the second quasiconductor 120 layers
There is higher carrier mobility.In this embodiment, the bottom surface of described opening flushes with the bottom surface of fin,
The bottom surface of the i.e. second semiconductor layer 120 flushes with the bottom surface of fin 110.
Then, can carry out the processing of subsequent device on this compound fin, formation comprises this and is combined
The semiconductor device of fin, this device has higher carrier mobility and more preferable interfacial characteristics, carries
The high performance of device.
The above, be only presently preferred embodiments of the present invention, and the present invention not makees any form
On restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Appoint
What those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all can profit
With the method for the disclosure above and technology contents, technical solution of the present invention made many possible variations and repair
Decorations, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from technical solution of the present invention
Content, according to the technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent
Change and modification, all still fall within the range of technical solution of the present invention protection.
Claims (13)
1. the forming method of a compound fin, it is characterised in that including:
Substrate is provided；
Shifted by side wall pattern, substrate is formed the first side wall mask；
Shifted by side wall pattern, the sidewall of the first side wall mask is formed the second side wall mask；
With the first side wall mask and the second side wall mask for sheltering, carry out the etching of substrate, to form fin,
And remove the first side wall mask, and etch the fin under the first side wall mask, to form opening；
Selective growth the second semiconductor layer and the 3rd semiconductor layer the most successively, compound to be formed
Fin, wherein, compared to fin and the 3rd semiconductor layer, described second semiconductor layer has higher current-carrying
Transport factor.
Forming method the most according to claim 1, it is characterised in that form fin and the step of opening
Suddenly include:
With the first side wall mask and the second side wall mask for sheltering, carry out the etching of substrate, to form fin；
Carry out thermal oxidation technology, and remove the first side wall mask；
Etch the fin under the first side wall masked areas, to form opening.
Forming method the most according to claim 1, it is characterised in that the bottom surface of described opening is high
Bottom surface in fin.
4. according to the forming method according to any one of claim 1-3, it is characterised in that described fin
Being silicon with the 3rd semiconductor layer, described second semiconductor layer is Ge or III-V group semi-conductor material.
5. the forming method of a compound fin, it is characterised in that including:
Substrate is provided；
Shifted by side wall pattern, substrate is formed the first side wall mask；
Shifted by side wall pattern, the sidewall of the first side wall mask is formed the second side wall mask；
Remove the first side wall mask, with the second side wall mask for sheltering, carry out the etching of substrate, with shape
Become the opening in fin and fin；
Selective growth the second semiconductor layer and the 3rd semiconductor layer the most successively, compound to be formed
Fin, wherein, compared to fin and the 3rd semiconductor layer, described second semiconductor layer has higher current-carrying
Transport factor.
Forming method the most according to claim 5, it is characterised in that select the most successively
Property grows the step of the second semiconductor layer and the 3rd semiconductor layer and includes:
Form the first packed layer in the opening；
Cover the substrate outside fin, to form the second packed layer；
Remove the first packed layer；
Epitaxial growth the second semiconductor layer and the 3rd semiconductor layer successively.
7., according to the forming method described in claim 5 or 6, described fin and the 3rd semiconductor layer are silicon,
Described second semiconductor layer is Ge or III-V group semi-conductor material.
8. the forming method of a semiconductor device, it is characterised in that use as in claim 1-7
The compound fin that forming method described in any one is formed.
9. a compound fin, it is characterised in that including:
Substrate；
Fin on substrate, is formed with opening in described fin；
The second semiconductor layer in described opening and the 3rd semiconductor layer on the second semiconductor layer, wherein,
Compared to fin and the 3rd semiconductor layer, the second semiconductor layer has higher carrier mobility.
Compound fin the most according to claim 9, it is characterised in that the bottom surface of described opening with
The bottom surface of fin flushes.
11. compound fins according to claim 9, it is characterised in that the bottom surface of described opening is high
Bottom surface in fin.
12. according to the compound fin according to any one of claim 9-11, it is characterised in that described fin
Being silicon with the 3rd semiconductor layer, described second semiconductor layer is Ge or III-V group semi-conductor material.
13. 1 kinds of semiconductor device, it is characterised in that include institute as any one of claim 9-12
The compound fin stated.
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| CN201510320225.XA CN106252228B (en) | 2015-06-11 | 2015-06-11 | Forming method of composite fin |
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| CN109087863A (en) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN113823553A (en) * | 2020-06-19 | 2021-12-21 | 中国科学院微电子研究所 | Double-pattern mask and manufacturing method thereof, semiconductor device and electronic equipment |
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| US20050218427A1 (en) * | 2003-07-21 | 2005-10-06 | International Business Machines Corporation | Method for making a FET channel |
| CN103515420A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method thereof |
| CN103515209A (en) * | 2012-06-19 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and formation method thereof |
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| US20050218427A1 (en) * | 2003-07-21 | 2005-10-06 | International Business Machines Corporation | Method for making a FET channel |
| CN103515209A (en) * | 2012-06-19 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and formation method thereof |
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| CN109087863A (en) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN109087863B (en) * | 2017-06-14 | 2022-02-15 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN113823553A (en) * | 2020-06-19 | 2021-12-21 | 中国科学院微电子研究所 | Double-pattern mask and manufacturing method thereof, semiconductor device and electronic equipment |
| CN113823553B (en) * | 2020-06-19 | 2024-05-31 | 中国科学院微电子研究所 | Double-pattern mask, manufacturing method thereof, semiconductor device and electronic equipment |
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