CN105575806A - Fin field-effect transistor and manufacturing method thereof - Google Patents
Fin field-effect transistor and manufacturing method thereof Download PDFInfo
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- CN105575806A CN105575806A CN201410525729.0A CN201410525729A CN105575806A CN 105575806 A CN105575806 A CN 105575806A CN 201410525729 A CN201410525729 A CN 201410525729A CN 105575806 A CN105575806 A CN 105575806A
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Abstract
The invention discloses a manufacturing method of a fin field-effect transistor, comprising the following steps: providing a substrate, wherein fins are formed on the substrate, and an isolation is formed between every two fins; forming a gate on the fins; removing part of the fins in the thickness direction at the two ends of the gate to form sag regions between the isolations; and performing selective epitaxial growth and performing doping to form source and drain regions on the sag regions. According to the invention, larger source and drain regions are formed, the stress action of the source and drain regions is enhanced, and the carrier mobility of the device is increased.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of fin formula field effect transistor and manufacture method thereof.
Background technology
Along with the height of semiconductor device is integrated, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more remarkable, even become the leading factor affecting device performance, this phenomenon is referred to as short-channel effect.The electric property of short-channel effect meeting deterioration of device, as caused, threshold voltage of the grid declines, power consumption increases and degradation problem under signal to noise ratio.
At present, in order to solve the problem of short-channel effect, propose the three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-FET is the transistor with fin channel structure, it utilizes several surfaces of thin fin as raceway groove, thus the short-channel effect in conventional transistor can be prevented, can operating current be increased simultaneously.
For semiconductor device, the mechanical stress in semiconductor device substrates can be used for the performance of adjusting means, by strengthening the stress of source-drain area or raceway groove, improving the mobility of charge carrier, improving the performance of device.For Fin-FET, the carrier mobility how improving device by stress engineering is also one of focus of research.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of manufacture method of fin formula field effect transistor is provided, to improve the carrier mobility of device.
For achieving the above object, technical scheme of the present invention is:
A manufacture method for fin formula field effect transistor, comprises step:
Substrate is provided, described substrate is formed with fin, between fin, is formed with isolation;
Fin forms grid;
Remove the fin of the segment thickness at grid two ends, to form depressed area between isolation;
Carry out selective epitaxial growth and adulterate, to form source-drain area on depressed area.
Optionally, described fin is formed in body silicon substrate, and the step forming isolation comprises: the deposit carrying out isolated material; Carry out planarization; Remove the isolated material of segment thickness, to form isolation.
Optionally, carrying out, between planarization and the isolated material removing segment thickness, also comprising step: carry out ion implantation, to form break-through stop-layer in fin.
Optionally, break-through stop-layer is formed in the fin of the segment thickness of removal.
Optionally, described source-drain area is formed with contact etching stop layer.
Optionally, the step forming source-drain area specifically comprises: carrying out selective epitaxial growth and carrying out in-situ doped, to form source-drain area on depressed area.
Optionally, before formation depressed area, also step is comprised: form source and drain extension area.
In addition, present invention also offers the fin formula field effect transistor formed by said method, comprising:
Substrate;
Fin on substrate;
Isolation between fin;
Grid on fin;
The fin at grid two ends has depressed area, and the bottom of depressed area is lower than the upper surface of isolating;
The source-drain area that on depressed area, extension is formed.
Optionally, also comprise: be formed at the break-through stop-layer in fin.
Optionally, the contact etching stop layer be formed on source-drain area is also comprised.
Fin formula field effect transistor of the present invention and manufacture method thereof, source and drain areas on fin defines the depressed area lower than isolation, then, source-drain area is gone out at this depressed area selective epitaxial growth, like this, form the source-drain area that volume is larger, thus strengthen the effect of stress of source-drain area, improve the carrier mobility of device.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the invention process, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 shows the flow chart of the manufacture method of fin formula field effect transistor of the present invention;
Fig. 2-Figure 11 B is the cross section structure schematic diagram manufactured according to the embodiment of the present invention in each manufacture process of fin formula field effect transistor, wherein, Fig. 2-Figure 11 is the cross section structure schematic diagram of the transistor along grid length direction, Fig. 2 A-11A is the cross section structure schematic diagram of the transistor along fin bearing of trend, and Fig. 6 B-11B is the cross section structure schematic diagram of the transistor along source-drain area direction.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
It should be noted that, in accompanying drawing of the present invention, the accompanying drawing of same sequence number, as Fig. 2 and Fig. 2 A, Fig. 6 and Fig. 6 A, Fig. 6 B, it is the schematic cross-section of the different directions of transistor in same manufacture process, wherein, Fig. 2-Figure 11 is the cross section structure schematic diagram of the transistor along grid length direction, and Fig. 2 A-11A is the cross section structure schematic diagram of the transistor along fin bearing of trend, and Fig. 6 B-11B is the cross section structure schematic diagram of the transistor along source-drain area direction.
The present invention proposes a kind of manufacture method of fin formula field effect transistor, comprising: substrate is provided, described substrate is formed with fin, between fin, is formed with isolation; Fin forms grid; Remove the fin of the segment thickness at grid two ends, to form depressed area between isolation; Carry out selective epitaxial growth and adulterate, to form source-drain area on depressed area.
The source and drain areas of manufacture method of the present invention on fin defines the depressed area lower than isolation, then, goes out source-drain area at this depressed area selective epitaxial growth, like this, form the source-drain area that volume is larger, thus strengthen the effect of stress of source-drain area, improve the carrier mobility of device.
Technical scheme for a better understanding of the present invention and technique effect, the schematic flow sheet Fig. 1 below with reference to manufacture method is described in detail specific embodiment.
In step S01, provide substrate 100, described substrate is formed with fin 102, between fin, be formed with isolation 110, shown in figure 5 and Fig. 5 A.
In embodiments of the present invention, described substrate is Semiconductor substrate, can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator) etc.In other embodiments, described Semiconductor substrate can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., can also other epitaxial structures, such as SGOI (silicon germanium on insulator) etc.
In the present embodiment, described substrate 100 is body silicon substrate.
In a specific embodiment, fin 102 and isolation 110 can be provided as follows.
First, the substrate 100 of body silicon is formed the first hard mask 104 of silicon nitride; Then, adopt lithographic technique, the such as method of RIE (reactive ion etching), etched substrate 100 forms fin 102, thus defines the fin 102 on substrate 100, as best seen in figs. 2 and 2.
Then, the isolated material 106 of filling silicon dioxide is carried out, as shown in Fig. 3 and Fig. 3 A; And carry out flatening process, as carried out chemical-mechanical planarization, until expose the first hard mask 104, as illustrated in figures 4 and 4; At this moment, can carry out ion implantation, protect fin by the first hard mask 104, in fin 102, form the doped region of break-through stop-layer 108, this doped region is positioned at the below of fin raceway groove, for preventing the break-through of fin raceway groove.
Then, wet etching can be used, as high temperature phosphoric acid removes the first hard mask 104 of silicon nitride, use the certain thickness isolated material of hydrofluoric acid erosion removal, the isolated material of reserve part between fin 102, thus defines isolation 110, as shown in figs. 5 and 5.
In step S02, fin forms grid 114, shown in figure 6, Fig. 6 A and 6B.
In the present invention, this grid 114 can be the grid in front grid technique, also can be the dummy grid in rear grid technique.In the present embodiment, be the dummy grid in rear grid technique.
Concrete, deposit gate dielectric material, pseudo-gate dielectric material and the second hard mask material first respectively, gate dielectric material can be thermal oxide layer or high K medium material etc., can be silicon dioxide in the present embodiment, can be formed by the method for thermal oxidation.Dummy grid material can be amorphous silicon, polysilicon etc., in the present embodiment, is amorphous silicon.Then, form the second hard mask 116 of patterning, under the covering of the second hard mask 116, continue etching, form the gate dielectric layer 112 and the dummy grid 114 that stride across fin 102, then, side wall 118 is formed at the sidewall of described dummy grid, can deposit silicon nitride be passed through, then carry out RIE (reactive ion etching) and form this side wall 118, as shown in Fig. 6, Fig. 6 A and 6B.
In step S03, remove the fin 102 of the segment thickness at grid 114 two ends, to form depressed area 101 between isolation 101, shown in figure 7, Fig. 7 A and 7B.
In the present embodiment, selective etch can be adopted, as the method for reactive ion etching (RIE), by grid two ends, namely the end sections of fin carries out etching removal, until be etched to below isolation upper surface, like this, between isolation 110, define depressed area 101, this depressed area and on part be the forming region of source-drain area, making the forming region of source-drain area have larger space, when removing, the break-through stop-layer of this part being removed in the lump.
Before formation depressed area 110, first can carry out the injection of the LDD (lightly doped drain) of wide-angle, can by according to the transistor arrangement expected, implanted with p-type or N-shaped alloy or impurity in the fin 102 at dummy grid two ends, to form source and drain extension area.
In step S04, carry out selective epitaxial growth and adulterate, to form source-drain area 122 on depressed area, shown in figure 8, Fig. 8 A and 8B.
Can, by the end epitaxial growth source-drain area of selective epitaxial process at fin, carry out in-situ doped simultaneously, thus form source-drain area 122, as shown in Fig. 8, Fig. 8 A and 8B.Then, the deposit of the second side wall can be carried out and carry out the activation of source-drain area doping.
In addition, the formation of contact etching stop layer (CESL, ContactEtchingStopLayer) can further be carried out, can the material of the contact etching stop layer such as first deposit silicon nitride or silicon oxynitride; Then the material of interlayer dielectric layer is covered, such as unadulterated silica (SiO
2), doping silica (as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si
3n
4) or other low k dielectric materials; Then, carry out planarization, such as cmp, until expose grid 114, as shown in Fig. 9, Fig. 9 A and 9B, like this, source-drain area 122 defines contact etching stop layer 124, and the interlayer dielectric layer 126 of cover gate both sides.
So far, defining the transistor device with the source-drain area of stronger effect of stress of the present invention, then, can adopt traditional handicraft, complete the subsequent technique of device, is the description that example carries out subsequent technique by later grid technique below.
In step S05, remove grid 114, to form opening 130, shown in Figure 10, Figure 10 A and Figure 10 B.
Lithographic technique can be used, such as use wet etching removal as the grid 114 of pseudo-grid, in a preferred embodiment, further gate dielectric layer 112 can be removed, to form opening 130, as shown in Figure 10, Figure 10 A and Figure 10 B, again to form alternative gate dielectric layer, to improve the quality of gate dielectric layer.
In step S06, fill up opening to form replacement gate 134, shown in Figure 11, Figure 11 A and Figure 11 B.
In the present embodiment, first, again gate dielectric layer 132 is formed, the alternative gate dielectric layer 132 of silica or silicon oxynitride can be formed by oxidizing process, and carry out the deposit of polysilicon, and carry out planarization, thus fill up polysilicon in the opening, form the replacement gate 134 of polysilicon, as shown in Figure 11, Figure 11 A and Figure 11 B.
So far, the fin formula field effect transistor of the embodiment of the present invention is defined.
Then, the subsequent technique of device can be completed as required, as formed contact and interconnection structure etc.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
In addition, present invention also offers the fin formula field effect transistor utilizing said method to be formed, shown in Figure 11, Figure 11 A and Figure 11 B, comprising: substrate 100; Fin 102 on substrate 100; Isolation 110 between fin 102; Grid 134 on fin; The fin at grid 134 two ends has depressed area 101, and the bottom of depressed area 101 is lower than the upper surface of isolation 110; The source-drain area 122 that on depressed area 101, extension is formed.
In a preferred embodiment, also comprise: be formed at the break-through stop-layer 108 in fin, for preventing the break-through of fin raceway groove.
Also comprise: be formed at the contact etching stop layer 124 on source-drain area, to strengthen the effect of stress of source-drain area.
Fin formula field effect transistor device of the present invention, by the depressed area lower than isolation on fin being formed the source-drain area of the extension of more volume, strengthening the effect of stress of source-drain area, thus improving the carrier mobility of device.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a manufacture method for fin formula field effect transistor, is characterized in that, comprises step:
Substrate is provided, described substrate is formed with fin, between fin, is formed with isolation;
Fin forms grid;
Remove the fin of the segment thickness at grid two ends, to form depressed area between isolation;
Carry out selective epitaxial growth and adulterate, to form source-drain area on depressed area.
2. manufacture method according to claim 1, is characterized in that, described fin is formed in body silicon substrate, and the step forming isolation comprises: the deposit carrying out isolated material; Carry out planarization; Remove the isolated material of segment thickness, to form isolation.
3. manufacture method according to claim 2, is characterized in that, is carrying out, between planarization and the isolated material removing segment thickness, also comprising step: carry out ion implantation, to form break-through stop-layer in fin.
4. manufacture method according to claim 3, is characterized in that, is formed with break-through stop-layer in the fin of the segment thickness of removal.
5. manufacture method according to claim 1, is characterized in that, described source-drain area is formed with contact etching stop layer.
6. manufacture method according to claim 1, is characterized in that, the step forming source-drain area specifically comprises: carrying out selective epitaxial growth and carrying out in-situ doped, to form source-drain area on depressed area.
7. manufacture method according to claim 1, is characterized in that, before formation depressed area, also comprises step: form source and drain extension area.
8. a fin formula field effect transistor, is characterized in that, comprising:
Substrate;
Fin on substrate;
Isolation between fin;
Grid on fin;
The fin at grid two ends has depressed area, and the bottom of depressed area is lower than the upper surface of isolating;
The source-drain area that on depressed area, extension is formed.
9. fin formula field effect transistor according to claim 8, is characterized in that, also comprises: be formed at the break-through stop-layer in fin.
10. fin formula field effect transistor according to claim 8, is characterized in that, also comprises the contact etching stop layer be formed on source-drain area.
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| CN201410525729.0A CN105575806A (en) | 2014-10-08 | 2014-10-08 | Fin field-effect transistor and manufacturing method thereof |
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| CN201410525729.0A CN105575806A (en) | 2014-10-08 | 2014-10-08 | Fin field-effect transistor and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807161A (en) * | 2017-04-28 | 2018-11-13 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| CN109980003A (en) * | 2017-12-27 | 2019-07-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| US20070145487A1 (en) * | 2005-12-27 | 2007-06-28 | Intel Corporation | Multigate device with recessed strain regions |
| US20110147812A1 (en) * | 2009-12-23 | 2011-06-23 | Steigerwald Joseph M | Polish to remove topography in sacrificial gate layer prior to gate patterning |
| CN103928335A (en) * | 2013-01-15 | 2014-07-16 | 中国科学院微电子研究所 | Semiconductor device and fabrication method thereof |
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2014
- 2014-10-08 CN CN201410525729.0A patent/CN105575806A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070145487A1 (en) * | 2005-12-27 | 2007-06-28 | Intel Corporation | Multigate device with recessed strain regions |
| US20110147812A1 (en) * | 2009-12-23 | 2011-06-23 | Steigerwald Joseph M | Polish to remove topography in sacrificial gate layer prior to gate patterning |
| CN103928335A (en) * | 2013-01-15 | 2014-07-16 | 中国科学院微电子研究所 | Semiconductor device and fabrication method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807161A (en) * | 2017-04-28 | 2018-11-13 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| CN109980003A (en) * | 2017-12-27 | 2019-07-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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Application publication date: 20160511 |