CN105097938A - Fin FET (field effect transistor) and formation method thereof - Google Patents
Fin FET (field effect transistor) and formation method thereof Download PDFInfo
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- CN105097938A CN105097938A CN201510488903.3A CN201510488903A CN105097938A CN 105097938 A CN105097938 A CN 105097938A CN 201510488903 A CN201510488903 A CN 201510488903A CN 105097938 A CN105097938 A CN 105097938A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000005669 field effect Effects 0.000 title claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000005516 engineering process Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims description 25
- 238000000576 coating method Methods 0.000 claims description 25
- 150000004767 nitrides Chemical class 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a Fin FET (field effect transistor) and a formation method thereof, and belongs to the technical field of semiconductor integrated circuit manufacturing. The Fin FET is realized by using width difference between an upper layer and a lower layer of a fin-shaped structure on a semiconductor substrate. When the width difference between the upper layer and the lower layer of the fin-shaped structure is great enough, the bottom part of the fin-shaped structure can be completely oxidized, an expanded part of the fin-shaped structure is reserved, and then an oxidation layer is formed on the semiconductor substrate, thereby forming a punch-through resisting layer with consistency at the bottom part of the fin-shaped structure. A method for forming the punch-through resisting layer at the bottom part of a fin by adopting a mode of ion implantation in the prior art is abandoned, and the performance of a Fin FET device is optimized. Meanwhile, the Fin FET and the formation method thereof can have good compatibility with existing technologies.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more specifically, relate to a kind of fin field effect pipe and forming method thereof.
Background technology
Along with the more considerations to cost and reliability, to the semiconductor device with more high integration (i.e. the higher packaging density of transistor and other devices), there is lasting demand.In order to improve integrated level, more and more general in FinFET (fin formula field effect transistor) device semiconductor integrated circuit in various applications and other semiconductor device.FinFET utilizes the semiconductor fin of side's extension on the surface of a substrate as the transistor of the channel region of transistor.
Current fin field effect pipe is widely used in small size field, and along with the propelling of high integration, the channel length of transistor is also in continuous reduction.If channel length is reduced to be less than operation limit, less desirable result will be produced, such as short-channel effect and break-through.
In prior art, usually adopt the mode of ion implantation bottom fin, form anti-break-through layer (APT), and form anti-break-through layer and be difficulty relative to the position of fin and challenging.When implementing the ion implantation operation through fin, the Random Dopant Fluctuation of APT layer may be produced, and this Random Dopant Fluctuation makes not mate between fin.The performance of FinFET transistor is also closely related relative to the position of fin with APT.If the APT formed in the substrate is positioned at position too dark below fin, produce less desirable short-channel effect.Injection through fin also can destroy fin self.When APT layer is formed more shallow in the substrate, the dopant impurities of APT layer occupies the bottom of fin, and after using high heat treatment especially in semiconductor fabrication, these high heat treatments cause from APT layer diffuse in reverse direction in fin.
Therefore, industry is needed badly provides a kind of fin field effect pipe and forming method thereof, this FinFET be included in whole device there is consistency, the fin of the anti-break-through layer do not expanded in fin.
Summary of the invention
The object of the invention is, for there is above-mentioned defect in prior art, to provide a kind of fin field effect pipe and forming method thereof, this FinFET be included in whole device there is consistency, the fin of the anti-break-through layer do not expanded in fin.
For solving the problem, the invention provides a kind of formation method of fin field effect pipe, comprising the following steps:
Step S01: semiconductor matrix is provided, and patterning etching is carried out to described semiconductor substrate, to form the semiconductor substrate with fin structure;
Step S02: form oxide skin(coating) and nitride layer successively on the semiconductor substrate with fin structure;
Step S03: described nitride layer is polished, and expose the top of described fin structure;
Step S04: the oxide skin(coating) removing fin structure both sides, and epitaxial growth is carried out to the fin structure exposing partial sidewall;
Step S05: remove nitride layer and oxide skin(coating), expose fin structure simultaneously; Wherein, described fin structure has expansion section and bottom, and the width of described expansion section is greater than the width of described bottom;
Step S06: carry out oxidation processes to semiconductor substrate, makes the bottom of described fin structure be fully oxidized simultaneously;
Step S07: form oxide layer on semiconductor substrate, described oxide layer covers the expansion section of described fin structure;
Step S08: etch described oxide layer, until expose the partial sidewall of described fin structure, is finally forming grid perpendicular on the direction of fin structure.
Preferably, the material of described semiconductor substrate is monocrystalline silicon, germanium silicon or carbon silicon.
Preferably, in described step S02, semiconductor substrate forms oxide skin(coating) and nitride layer by ald or chemical meteorology deposition.
Preferably, the material of described oxide skin(coating) is silica, and the material of described nitride layer is silicon nitride.
Preferably, in described step S03, CMP (Chemical Mechanical Polishing) process is adopted to polish described nitride layer.
Preferably, in described step S04, the width removing the oxide skin(coating) of fin structure both sides is 5 ~ 20 nanometers.
Preferably, in described step S05, dry plasma etch technique or wet-etching technology is adopted to remove nitride layer and oxide skin(coating).
Preferably, described grid is polysilicon, amorphous silicon or metal gate material.
The present invention also provides a kind of fin field effect pipe, comprising:
Semiconductor substrate;
Oxide layer, is formed on described semiconductor substrate, and has preset thickness;
Fin structure, the bottom of described fin structure is embedded in described oxide layer, and meanwhile, partial sidewall is exposed to outside described oxide layer; And
Grid, is formed at the vertical direction of described fin structure.
Preferably, described fin field effect pipe also comprises source electrode and drain electrode, and described source electrode and drain electrode lay respectively at the both sides of described fin structure.
As can be seen from technique scheme, in fin field effect pipe provided by the invention and forming method thereof, the width difference of fin structure levels on semiconductor substrate is utilized to realize, when the width difference of the levels of fin structure is enough large, the bottom of fin structure can be made to be fully oxidized, and retain the expansion section of fin structure, then on semiconductor substrate, oxide layer is formed, thus the bottom achieving fin structure defines consistent anti-break-through layer, abandon in prior art the method adopting the mode of ion implantation to form anti-break-through layer bottom fin, optimize FinFET performance, good compatibility can be had with existing technique simultaneously.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 is the flow chart of the formation method of fin field effect pipe of the present invention;
Fig. 2 ~ Figure 11 is the structural representation making fin formula field effect transistor in one embodiment of the invention according to the formation method of Fig. 1.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
It should be noted that, in following embodiment, utilize the schematic diagram of Fig. 1 ~ Figure 11 to carry out detailed statement to the formation method by fin field effect pipe of the present invention.Describe in detail embodiments of the present invention time, for convenience of explanation, each schematic diagram not according to general scale and carried out partial enlargement and omit process, therefore, should avoid in this, as limitation of the invention.
Refer to Fig. 1, Fig. 1 is the flow chart of the formation method of fin field effect pipe of the present invention; Meanwhile, please control reference Fig. 2 ~ Figure 11, Fig. 2 ~ Figure 11 be the structural representation making fin formula field effect transistor in one embodiment of the invention according to the formation method of Fig. 1.The structure of the fin formula field effect transistor illustrated in Fig. 2 ~ Figure 11 is corresponding with each step in Fig. 1 respectively, so that the understanding to the inventive method.
As shown in Figure 1, the invention provides a kind of formation method of fin field effect pipe, comprise the following steps:
Step S01: semiconductor matrix 10 is provided, and patterning etching is carried out to described semiconductor substrate 10, to form the semiconductor substrate 10 (as shown in Figure 2) with fin structure 20.
Wherein, the material of semiconductor substrate 10 is the silicon materials that monocrystalline silicon, silicon nitride or amorphous silicon are formed, or insulator material (Silicononinsulator is called for short SOI), can also be other semi-conducting material or other structure, not repeat them here.The material of the semiconductor substrate 10 in the present embodiment is preferably monocrystalline silicon, germanium silicon or carbon silicon.
In this step, the cross section of fin structure 20 is rectangular configuration, is formed at the upper surface of semiconductor substrate 10.
Step S02: form oxide skin(coating) 30 and nitride layer 40 (as shown in Figure 3) on the semiconductor substrate 10 with fin structure successively.
In this step, the material of oxide skin(coating) 30 is preferably silica, and the material of described nitride layer 40 is preferably silicon nitride.Semiconductor substrate 10 forms oxide skin(coating) 30 and nitride layer 40 by ald or chemical meteorology deposition.Wherein, oxide skin(coating) 30 covers semiconductor substrate 10 and fin structure 20 uniformly, and nitride layer 40 covers the upper surface of oxide skin(coating) 30.
Step S03: nitride layer 40 is polished, and the top (as shown in Figure 4) exposing described fin structure 20.
In this step, preferably adopt CMP (Chemical Mechanical Polishing) process to polish nitride layer 40, and namely the top exposing fin structure 20 stop.
Step S04: the oxide skin(coating) 30 (as shown in Figure 5) removing fin structure both sides, and epitaxial growth (as shown in Figure 6) is carried out to the fin structure 20 exposing partial sidewall.
Wherein, dry plasma etch technique or wet-etching technology can be adopted to remove oxide skin(coating) 30, and the width of oxide skin(coating) 30 is preferably 5 ~ 20 nanometers, and concrete width is decided according to the actual requirements.
Then carry out epitaxial growth to the fin structure 20 exposing partial sidewall, the epitaxially grown height of fin structure 20 can higher than the upper surface of nitride layer 40.
Step S05: remove nitride layer 40 and oxide skin(coating) 30, expose fin structure 20 simultaneously; Wherein, fin structure 20 has expansion section 21 and bottom 22, and the width of expansion section 21 is greater than the width (as shown in Figure 7) of described bottom 22.
In this step, dry plasma etch technique or wet-etching technology can be adopted to remove nitride layer 40 and oxide skin(coating) 30, after removing nitride layer 40 and oxide skin(coating) 30, namely expose fin structure 20 wide at the top and narrow at the bottom.
Step S06: carry out oxidation processes to semiconductor substrate 10, makes the bottom 22 of fin structure be fully oxidized (as shown in Figure 8) simultaneously.
In this step, oxidation processes is carried out to semiconductor substrate 10, not removing only the upper surface of semiconductor substrate 10, simultaneously by bottom 22 complete oxidation of fin structure, only remain the expansion section 21 of fin structure, define new fin.
Step S07: form oxide layer 50 on semiconductor substrate 10, oxide layer 50 covers the expansion section 21 (as shown in Figure 9) of fin structure.
In this step, form new oxide layer 50 by ald or chemical meteorology deposition, simultaneous oxidation layer 50 covers the expansion section 21 of fin structure.
Step S08: etch oxide layer 50, until the partial sidewall (as shown in Figure 10) exposing fin structure 20, finally forms grid 60 (as shown in figure 11) on the direction perpendicular to fin structure 20.
In this step, dry plasma etch technique or wet-etching technology can be adopted to etch oxide layer 50, and expose the partial sidewall of fin structure 20 (expansion section 22 after namely retaining), finally, form grid 60, grid 60 is preferably polysilicon, amorphous silicon or metal gate material.
The present invention also provides a kind of fin field effect pipe, comprising: semiconductor substrate 10, oxide layer 50, fin structure 20 and grid 60; Wherein, oxide layer 50 is formed on semiconductor substrate 10, and has preset thickness; The bottom of fin structure 20 is embedded in oxide layer 50, and meanwhile, partial sidewall is exposed to outside oxide layer 50; Grid 60 is formed at the vertical direction of fin structure 20.In addition, fin field effect pipe also comprises source electrode and drain electrode, and source electrode and drain electrode lay respectively at the both sides of fin structure 20.
In sum, in fin field effect pipe provided by the invention and forming method thereof, the width difference of fin structure levels on semiconductor substrate is utilized to realize, when the width difference of the levels of fin structure is enough large, the bottom of fin structure can be made to be fully oxidized, and retain the expansion section of fin structure, then on semiconductor substrate, oxide layer is formed, thus the bottom achieving fin structure defines consistent anti-break-through layer, abandon in prior art the method adopting the mode of ion implantation to form anti-break-through layer bottom fin, optimize FinFET performance, good compatibility can be had with existing technique simultaneously.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a formation method for fin field effect pipe, is characterized in that, comprise the following steps:
Step S01: semiconductor matrix is provided, and patterning etching is carried out to described semiconductor substrate, to form the semiconductor substrate with fin structure;
Step S02: form oxide skin(coating) and nitride layer successively on the semiconductor substrate with fin structure;
Step S03: described nitride layer is polished, and expose the top of described fin structure;
Step S04: the oxide skin(coating) removing fin structure both sides, and epitaxial growth is carried out to the fin structure exposing partial sidewall;
Step S05: remove nitride layer and oxide skin(coating), expose fin structure simultaneously; Wherein, described fin structure has expansion section and bottom, and the width of described expansion section is greater than the width of described bottom;
Step S06: carry out oxidation processes to semiconductor substrate, makes the bottom of described fin structure completely oxidized simultaneously;
Step S07: form oxide layer on semiconductor substrate, described oxide layer covers the expansion section of described fin structure;
Step S08: etch described oxide layer, until expose the partial sidewall of described fin structure, is finally forming grid perpendicular on the direction of fin structure.
2. the formation method of fin field effect pipe according to claim 1, is characterized in that, the material of described semiconductor substrate is monocrystalline silicon, germanium silicon or carbon silicon.
3. the formation method of fin field effect pipe according to claim 1, is characterized in that, in described step S02, semiconductor substrate forms oxide skin(coating) and nitride layer by ald or chemical meteorology deposition.
4. the formation method of fin field effect pipe according to claim 3, is characterized in that, the material of described oxide skin(coating) is silica, and the material of described nitride layer is silicon nitride.
5. the formation method of fin field effect pipe according to claim 1, is characterized in that, in described step S03, adopts CMP (Chemical Mechanical Polishing) process to polish described nitride layer.
6. the formation method of fin field effect pipe according to claim 1, is characterized in that, in described step S04, the width removing the oxide skin(coating) of fin structure both sides is 5 ~ 20 nanometers.
7. the formation method of fin field effect pipe according to claim 1, is characterized in that, in described step S05, adopts dry plasma etch technique or wet-etching technology to remove nitride layer and oxide skin(coating).
8. the formation method of fin field effect pipe according to claim 1, is characterized in that, described grid is polysilicon, amorphous silicon or metal gate material.
9. a fin field effect pipe, is characterized in that, comprising:
Semiconductor substrate;
Oxide layer, is formed on described semiconductor substrate, and has preset thickness;
Fin structure, the bottom of described fin structure is embedded in described oxide layer, and meanwhile, partial sidewall is exposed to outside described oxide layer; And
Grid, is formed at the vertical direction of described fin structure.
10. fin field effect pipe according to claim 9, is characterized in that, described fin field effect pipe also comprises source electrode and drain electrode, and described source electrode and drain electrode lay respectively at the both sides of described fin structure.
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| CN201510488903.3A CN105097938B (en) | 2015-08-11 | 2015-08-11 | A kind of fin field effect pipe and forming method thereof |
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| CN201510488903.3A CN105097938B (en) | 2015-08-11 | 2015-08-11 | A kind of fin field effect pipe and forming method thereof |
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| CN105097938B CN105097938B (en) | 2018-10-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113948396A (en) * | 2021-09-18 | 2022-01-18 | 上海华力集成电路制造有限公司 | Method for manufacturing fin field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7122871B2 (en) * | 2003-06-20 | 2006-10-17 | Samsung Electronics Co., Ltd. | Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations |
| US20080191271A1 (en) * | 2007-01-12 | 2008-08-14 | Atsushi Yagishita | Semiconductor device having fins fet and manufacturing method thereof |
| CN101752258A (en) * | 2008-12-05 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
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2015
- 2015-08-11 CN CN201510488903.3A patent/CN105097938B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7122871B2 (en) * | 2003-06-20 | 2006-10-17 | Samsung Electronics Co., Ltd. | Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations |
| US20080191271A1 (en) * | 2007-01-12 | 2008-08-14 | Atsushi Yagishita | Semiconductor device having fins fet and manufacturing method thereof |
| CN101752258A (en) * | 2008-12-05 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113948396A (en) * | 2021-09-18 | 2022-01-18 | 上海华力集成电路制造有限公司 | Method for manufacturing fin field effect transistor |
| CN113948396B (en) * | 2021-09-18 | 2024-09-10 | 上海华力集成电路制造有限公司 | Manufacturing method of fin field effect transistor |
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| CN105097938B (en) | 2018-10-16 |
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