CN113948396A - Method for manufacturing fin field effect transistor - Google Patents

Method for manufacturing fin field effect transistor Download PDF

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Publication number
CN113948396A
CN113948396A CN202111097921.0A CN202111097921A CN113948396A CN 113948396 A CN113948396 A CN 113948396A CN 202111097921 A CN202111097921 A CN 202111097921A CN 113948396 A CN113948396 A CN 113948396A
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fin
layer
oxide layer
fin body
effect transistor
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a method for manufacturing a fin field effect transistor, which comprises the following steps: step one, etching a semiconductor substrate to form a fin body; depositing an FCVD oxide layer to completely fill the interval region between the fin bodies; thirdly, carrying out first annealing to enable the FCVD oxide layer to be solidified for the first time; and fourthly, etching back the FCVD oxide layer to expose the top part of the fin body. Depositing a sacrificial medium layer to surround the top part of the fin body; sixthly, performing second annealing to completely solidify the FCVD oxide layer, wherein oxygen of the FCVD oxide layer in the second annealing consumes the material of the fin body, so that the width of the bottom part of the fin body is reduced, and the anti-punch-through capability of the fin field effect transistor is improved; and seventhly, removing the sacrificial dielectric layer. The invention can improve the anti-punch-through capability of the device, improve the mobility of channel carriers and improve the performance of the device.

Description

Method for manufacturing fin field effect transistor
Technical Field
The present invention relates to the Field of semiconductor integrated circuit fabrication, and more particularly, to a method for fabricating a Fin Field Effect Transistor (FinFET).
Background
As semiconductor process technology advances and gate widths continue to shrink, conventional planar CMOS devices have been unable to meet device requirements, such as short channel control. For technology nodes below 20nm, the FinFET structure has better electrical performance. Fig. 1 is a plan view of a first prior art finfet; FIG. 2 is a cross-sectional view taken along dashed line AA in FIG. 1; FIG. 3 is a cross-sectional view taken along the dashed line BB in FIG. 1; a first conventional finfet includes:
the fin body 2 is formed on a semiconductor substrate such as a silicon substrate 1, the bottom of the fin body 2 is isolated by an insulating layer 3, and the insulating layer 3 usually adopts shallow trench field oxide (STI).
The top surface and the side surfaces of the fin body 2 are covered with Metal Grids (MG). Typically, a gate dielectric layer employing a high dielectric constant (HK) layer 2042 is isolated between the metal gate and the material of the fin 2, and the entire gate structure 204 is HKMG. As can be seen from the plan view of fig. 1, the fin 2 includes a plurality of parallel metal grids, and the metal grids are also disposed in parallel, and the length direction of each metal grid is perpendicular to the length direction of the fin 2. As shown in fig. 3, the gate structure is shown as a dashed line 204, and a gate dielectric layer of the gate structure 204 includes an interfacial layer 2041, a high-k layer 2042, and a bottom barrier layer 2043, which are sequentially stacked. The metal gate of the gate structure 204 includes a work function layer 2044, a top barrier layer 2045, and a metal conductive material layer 4 stacked in sequence. The metallic conductive material layer 4 is shown in a top view configuration in fig. 1. A side wall 203 is formed on the side surface of the gate structure 204, a Contact Etch Stop Layer (CESL)201 covers the side surface of the side wall 203 and the surfaces of the silicon substrate 1 and the insulating layer 3 outside the gate structure 204, and a zero-layer interlayer film 202 is formed in an interval area of the gate structure 204.
An N-type finfet 101 and a P-type finfet 102 are shown in fig. 1. A source region and a drain region are formed on two sides of the metal gate of the N-type fin field effect transistor 101, and an embedded SiP epitaxial layer 5 is formed in the source region and the drain region. A source region and a drain region are formed on two sides of the metal gate of the P-type fin field effect transistor 102, and an embedded SiGe epitaxial layer 6 is formed in the source region and the drain region. The embedded SiGe epitaxial layer 6 and the embedded SiP epitaxial layer 5 are epitaxially formed after etching the fin body 2.
The work function layer 1024 of the N-type finfet 101 is an N-type work function layer. The work function layer 1024 of the P-type finfet 102 is a P-type work function layer.
As can be seen from fig. 2, the fin 2 includes a bottom portion 2a and a top portion 2b, and the bottom portion 2a is located in the insulating layer 3. The metal grid covers the top surface and the sides of the top portion 2b of the fin 2. As shown in fig. 3, the top portion 2b of the fin 2 covered by the metal gate serves as a channel region 2 c. The top portion 2b of the fin 2 is shown as having a height h1 in fig. 2, h1 is also the height of the channel region 2c, and the height h1 of the channel region 2c is also shown in fig. 3.
Fig. 3 shows a cross-sectional structure diagram of the N-type fin field effect transistor 101, and it can be seen that a source region 5a and a drain region 5b are formed on both sides of a gate structure 204, and an embedded SiP epitaxial layer 5 is formed in the source region 5a and the drain region 5 b.
In fig. 3, a dashed line CC indicates the bottom surface position of the top portion 2b of the fin 2, and a dashed line DD indicates the bottom surface position of the bottom portion 2a of the fin 2. It can be seen that the control of the gate structure 204 on the bottom region of the dotted line CC corresponding to the mark 205 is weakened, the source region 5a and the drain region 5b easily deplete the bottom region of the dotted line CC corresponding to the mark 205, so that the source region 5a and the drain region 5b connect the depletion regions of the bottom region of the dotted line CC corresponding to the mark 205 to form punch-through (punchthregh), and the source region 5a and the drain region 5b may generate leakage current through the punch-through of the depletion regions. It is generally necessary to form an anti-punch through (APT) layer to prevent punch through.
Fig. 4 is a schematic view of a fin structure of a conventional second finfet having a punch-through prevention layer; in fig. 4, a fin 302 and an insulating layer 303 consisting of STI are shown. The area between the dotted lines EE and FF is the top area of the fin body 302, and the height h301 of the top area of the fin body 302 is the height of the channel region. A through-preventing layer 304 is formed at the bottom of the top region of the fin 303. In the prior art, the anti-punch-through layer 304 is usually formed by an ion implantation process. It is found that the anti-punch-through layer 304 formed by the prior art method has the following defects:
first, ion implantation can cause ion implantation damage that can reduce the carrier mobility of the channel region, thereby reducing device performance.
Next, the doping profile of the punch-through prevention layer 304 formed by ion implantation is as shown by reference numeral 304a, and it can be seen that the doping of the punch-through prevention layer 304 gradually decreases from the peak (peak) position upwards and downwards, a tail (tail) formed in the process of the upward decrease enters the top region of the fin 302, the tail doping of the punch-through prevention layer 304 affects the doping of the channel region because the channel region is formed in the top region of the fin 302, and finally the performance of the channel region such as the threshold voltage and the carrier mobility is formed, thereby reducing the device performance.
Disclosure of Invention
The invention aims to provide a method for manufacturing a fin field effect transistor, which can improve the punch-through prevention capability of a device, improve the mobility of a channel carrier and improve the performance of the device.
In order to solve the above technical problems, the method for manufacturing a fin field effect transistor according to the present invention includes the steps of:
step one, providing a semiconductor substrate, defining a forming area of fin bodies, and etching the semiconductor substrate to form the fin bodies, wherein interval areas are arranged among the fin bodies;
depositing an FCVD oxide layer by adopting an FCVD process to completely fill the interval region between the fin bodies;
thirdly, annealing the FCVD oxide layer for the first time to enable the FCVD oxide layer to be solidified for the first time;
fourthly, etching back the FCVD oxide layer, wherein the top surface of the FCVD oxide layer is lower than the top surface of the fin body after etching back, the fin body is divided into a top part located above the top surface of the FCVD oxide layer and a bottom part located below the top surface of the FCVD oxide layer, and the bottom part of the fin body is surrounded by the FCVD oxide layer;
depositing a sacrificial medium layer to surround the top part of the fin body;
sixthly, performing second annealing on the FCVD oxide layer to completely solidify the FCVD oxide layer, wherein oxygen of the FCVD oxide layer in the second annealing consumes the material of the fin body so that the width of the bottom part of the fin body is reduced, and the anti-punch-through capability of the fin field effect transistor is improved by utilizing the reduction of the width of the bottom part of the fin body;
and seventhly, removing the sacrificial dielectric layer.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the step one comprises the following sub-steps:
step 11, forming a hard mask layer on the surface of the semiconductor substrate;
step 12, forming a photoresist pattern, wherein the photoresist pattern covers a forming area of the fin body and opens the forming area of the fin body;
step 13, etching the hard mask layer to transfer the pattern structure of the photoresist pattern into the hard mask layer;
and step 14, etching the semiconductor substrate by taking the hard mask layer as a mask to form the fin body.
In the second step, the top surface of the FCVD oxide layer is level with the top surface of the hard mask layer;
in the fourth step, before or after the back etching of the FCVD oxide layer, a step of removing the hard mask layer is further included.
In a further improvement, in step five, the sacrificial dielectric layer covers at least a side surface of the top portion of the fin body.
In a further improvement, in step five, the sacrificial dielectric layer covers the top surface and the side surfaces of the top portion of the fin body and the top surface of the FCVD oxide layer outside the fin body.
In a further improvement, in step five, the material of the sacrificial dielectric layer includes silicon oxide or silicon nitride.
In a further improvement, in the sixth step, after the second annealing, the two sides of the bottom portion of the fin body respectively lose 2nm of width.
In a further improvement, after the seventh step, the method further comprises the steps of:
and forming a pseudo gate structure formed by overlapping the pseudo gate dielectric layer and the polycrystalline silicon pseudo gate by adopting a deposition and graphical etching process.
The further improvement is that the method also comprises the following steps:
forming a source region and a drain region in the top parts of the fin bodies of the two layers of the pseudo gate structure;
forming a zero-layer interlayer film and flattening the zero-layer interlayer film to enable the top surface of the zero-layer interlayer film to be level to the top surface of the pseudo gate structure;
and removing the pseudo gate structure by a gate replacement process, and forming a gate structure formed by overlapping a gate dielectric layer and a metal gate in the pseudo gate structure removal region.
The further improvement is that the bottom part of the fin body with the reduced width in the step six is directly used as a penetration-preventing layer of the fin field effect transistor;
or, after the sixth step, adding a punch-through prevention implantation process, wherein the punch-through prevention implantation injects punch-through prevention impurities into the bottom part of the fin body with the reduced width, and the impurity dosage of the punch-through prevention implantation is reduced in combination with the reduction of the width of the bottom part of the fin body, so as to reduce the doping influence on the top part of the fin body.
In a further improvement, the dummy gate dielectric layer is an oxide layer.
In a further improvement, the method further comprises the step of forming a side wall on the side surface of the pseudo gate dielectric layer after the pseudo gate dielectric layer is formed.
The further improvement is that the step of forming the source region and the drain region comprises a step of forming an embedded epitaxial layer and a step of performing source and drain implantation.
In a further improvement, the gate dielectric layer comprises a high dielectric constant layer.
According to the method, the annealing process required for curing the FCVD oxide layer is divided into two times by utilizing the characteristic that the FCVD oxide layer can generate loss on the material of the fin body during annealing, the first annealing enables the FCVD oxide layer to be cured for the first time, and the hardness of the FCVD oxide layer after the first curing can ensure that the etching back can be well carried out; after the FCVD oxide layer is etched back, the FCVD oxide layer only covers the bottom part of the fin body, then the FCVD oxide layer is annealed for the second time, the FCVD oxide layer can be completely cured by annealing for the second time, meanwhile, because the FCVD oxide layer only covers the bottom part of the fin body in annealing for the second time, the second annealing only can generate loss on the bottom part of the fin body, the width of the bottom part of the fin body is reduced, namely the width of the bottom part of the fin body is smaller than that of the top part, and the anti-punch-through capability of the fin field effect transistor can be improved after the width of the bottom part of the fin body is reduced; this is because, after the width of the bottom portion of the fin is reduced, the depletion control capability of the gate structure covering the top surface and the side surfaces of the top portion of the fin on the bottom portion of the fin is enhanced, which considerably weakens the control of the source and drain regions on the depletion of the bottom portion of the fin, thereby improving the punch-through prevention capability of the finfet.
According to the invention, the width of the bottom part of the fin body is reduced, the requirement of the device on the anti-punch-through capability can be met without carrying out anti-punch-through injection or only carrying out anti-punch-through injection with small dosage, impurities of the anti-punch-through injection can be reduced or eliminated from being diffused into the top part of the fin body without carrying out the anti-punch-through injection or reducing the dosage of the anti-punch-through injection, and the channel region is formed in the top part of the fin body, so that the mobility of channel carriers can be improved, and the performance of the device can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a plan view of a first prior art finfet;
FIG. 2 is a cross-sectional view taken along dashed line AA in FIG. 1;
FIG. 3 is a cross-sectional view taken along the dashed line BB in FIG. 1;
FIG. 4 is a schematic diagram of a fin structure with a punch-through prevention layer in a second prior art FinFET;
FIG. 5 is a flow chart of a method of fabricating a FinFET transistor according to an embodiment of the present invention;
fig. 6A-6F are schematic device structures at various steps of a method for fabricating a finfet in accordance with an embodiment of the present invention.
Detailed Description
Fig. 5 is a flow chart illustrating a method of fabricating a finfet in accordance with an embodiment of the present invention; fig. 6A to 6F are schematic device structures in the steps of the method for manufacturing a finfet device according to the embodiment of the present invention. The manufacturing method of the fin field effect transistor comprises the following steps:
step one, as shown in fig. 6A, providing a semiconductor substrate 401, defining a formation region of a fin body 402, and etching the semiconductor substrate 401 to form the fin body 402, wherein a spacing region is formed between the fin bodies 402.
The semiconductor substrate 401 includes a silicon substrate.
The first step comprises the following sub-steps:
and 11, forming a hard mask layer 403 on the surface of the semiconductor substrate 401. The hard mask layer 403 is formed by stacking an oxide layer 403a and a nitride layer 403 b.
And step 12, forming a photoresist pattern, wherein the photoresist pattern covers the forming area of the fin body 402 and opens the forming area of the fin body 402.
And step 13, etching the hard mask layer 403 to transfer the pattern structure of the photoresist pattern into the hard mask layer 403.
Step 14, etching the semiconductor substrate 401 with the hard mask layer 403 as a mask to form the fin body 402.
Step two, as shown in fig. 6B, depositing an FCVD oxide layer 404 by an FCVD process to completely fill the spaced regions between the fins 402.
In the embodiment of the present invention, the top surface of the FCVD oxide layer 404 is flush with the top surface of the hard mask layer 403.
And step three, performing first annealing on the FCVD oxide layer 404 to perform first curing on the FCVD oxide layer 404.
Step four, as shown in fig. 6C, the FCVD oxide layer 404 is etched back, after the etching back, the top surface of the FCVD oxide layer 404 is lower than the top surface of the fin body 402, the fin body 402 is divided into a top portion 402b located above the top surface of the FCVD oxide layer 404 and a bottom portion 402a located below the top surface of the FCVD oxide layer 404, and the bottom portion 402a of the fin body 402 is surrounded by the FCVD oxide layer 404.
In the embodiment of the present invention, before or after the back etching of the FCVD oxide layer 404, a step of removing the hard mask layer 403 is further included.
Step five, as shown in fig. 6D, a sacrificial dielectric layer 405 is deposited to surround the top portion 402b of the fin body 402.
In the embodiment of the present invention, the sacrificial dielectric layer 405 covers at least the side surface of the top portion 402b of the fin body 402. Preferably, the sacrificial dielectric layer 405 covers the top surface and the side surfaces of the top portion 402b of the fin body 402 and the top surface of the FCVD oxide layer 404 outside the fin body 402.
The material of the sacrificial dielectric layer 405 includes silicon oxide or silicon nitride.
Sixthly, as shown in fig. 6E, performing a second annealing on the FCVD oxide layer 404 to completely solidify the FCVD oxide layer 404, wherein oxygen of the FCVD oxide layer 404 consumes the material of the fin body 402 during the second annealing, so that the width of the bottom portion 402a of the fin body 402 is reduced, and the reduction of the width of the bottom portion 402a of the fin body 402 is utilized to improve the punch-through prevention capability of the finfet.
In the embodiment of the present invention, after the second annealing, two sides of the bottom portion 402a of the fin body 402 respectively lose a width of 2 nm.
And directly adopting the bottom part 402a of the fin body 402 with the reduced width in the step six as a penetration preventing layer of the fin field effect transistor. Alternatively, after step six, a one-step punch-through prevention implantation process is added, which implants punch-through prevention impurities into the bottom portion 402a of the fin body 402 with the reduced width, in combination with the reduction of the width of the bottom portion 402a of the fin body 402 to reduce the impurity dose of the punch-through prevention implantation to reduce the doping impact on the top portion 402b of the fin body 402.
Step seven, as shown in fig. 6F, the sacrificial dielectric layer 405 is removed.
After the seventh step, the method also comprises the following steps:
and forming a pseudo gate structure formed by overlapping the pseudo gate dielectric layer and the polycrystalline silicon pseudo gate by adopting a deposition and graphical etching process. And the pseudo gate dielectric layer adopts an oxide layer. And forming a side wall on the side surface of the pseudo gate dielectric layer after the pseudo gate dielectric layer is formed.
And forming a source region and a drain region in the top part 402b of the fin body 402 of the two layers of the dummy gate structure. The step of forming the source region and the drain region comprises a step of forming an embedded epitaxial layer and a step of performing source and drain injection.
Forming a zero-layer interlayer film and flattening the zero-layer interlayer film to enable the top surface of the zero-layer interlayer film to be level to the top surface of the pseudo gate structure;
and removing the pseudo gate structure by a gate replacement process, and forming a gate structure formed by overlapping a gate dielectric layer and a metal gate in the pseudo gate structure removal region. The gate dielectric layer includes a high dielectric constant layer.
The method also comprises a step of forming a metal interconnection structure. These steps can be achieved using conventional process steps known in the art and will not be described in detail herein.
According to the embodiment of the invention, by utilizing the characteristic that the FCVD oxide layer 404 generates loss on the material of the fin body 402 during annealing, the annealing process required for curing the FCVD oxide layer 404 is divided into two times, the first annealing enables the FCVD oxide layer 404 to be cured for the first time, and the hardness of the FCVD oxide layer 404 after the first curing can ensure that the back etching can be well performed; after the FCVD oxide layer 404 is etched back, the FCVD oxide layer 404 covers only the bottom portion 402a of the fin body 402, and then the FCVD oxide layer 404 is annealed for the second time, which can complete the complete curing of the FCVD oxide layer 404, and meanwhile, since the FCVD oxide layer 404 covers only the bottom portion 402a of the fin body 402 in the second annealing, the second annealing only generates a loss to the bottom portion 402a of the fin body 402, so that the width of the bottom portion 402a of the fin body 402 is reduced, i.e., the width of the bottom portion 402a of the fin body 402 is smaller than the width of the top portion 402b, and the punch-through prevention capability of the fin field effect transistor can be improved after the width of the bottom portion 402a of the fin body 402 is reduced; this is because, after the width of the bottom portion 402a of the fin 402 is reduced, the depletion control capability of the gate structure covering the top surface and the side surfaces of the top portion 402b of the fin 402 on the bottom portion 402a of the fin 402 is enhanced, which considerably weakens the control of the source and drain regions on the depletion of the bottom portion 402a of the fin 402, thereby improving the punch-through prevention capability of the finfet.
By reducing the width of the bottom portion 402a of the fin 402, the embodiment of the invention can meet the requirement of the device on the anti-punch-through capability without performing the anti-punch-through implantation or performing the anti-punch-through implantation with a small dose, and the impurity of the anti-punch-through implantation can be reduced or eliminated from diffusing into the top portion 402b of the fin 402 without performing the anti-punch-through implantation or reducing the dose of the anti-punch-through implantation, and the channel region is formed in the top portion 402b of the fin 402, so that the mobility of channel carriers can be improved, and the performance of the device can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A method for manufacturing a fin field effect transistor is characterized by comprising the following steps:
step one, providing a semiconductor substrate, defining a forming area of fin bodies, and etching the semiconductor substrate to form the fin bodies, wherein interval areas are arranged among the fin bodies;
depositing an FCVD oxide layer by adopting an FCVD process to completely fill the interval region between the fin bodies;
thirdly, annealing the FCVD oxide layer for the first time to enable the FCVD oxide layer to be solidified for the first time;
fourthly, etching back the FCVD oxide layer, wherein the top surface of the FCVD oxide layer is lower than the top surface of the fin body after etching back, the fin body is divided into a top part located above the top surface of the FCVD oxide layer and a bottom part located below the top surface of the FCVD oxide layer, and the bottom part of the fin body is surrounded by the FCVD oxide layer;
depositing a sacrificial medium layer to surround the top part of the fin body;
sixthly, performing second annealing on the FCVD oxide layer to completely solidify the FCVD oxide layer, wherein oxygen of the FCVD oxide layer in the second annealing consumes the material of the fin body so that the width of the bottom part of the fin body is reduced, and the anti-punch-through capability of the fin field effect transistor is improved by utilizing the reduction of the width of the bottom part of the fin body;
and seventhly, removing the sacrificial dielectric layer.
2. The method of manufacturing a fin field effect transistor of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The method of manufacturing a fin field effect transistor of claim 1, wherein:
the first step comprises the following sub-steps:
step 11, forming a hard mask layer on the surface of the semiconductor substrate;
step 12, forming a photoresist pattern, wherein the photoresist pattern covers a forming area of the fin body and opens the forming area of the fin body;
step 13, etching the hard mask layer to transfer the pattern structure of the photoresist pattern into the hard mask layer;
and step 14, etching the semiconductor substrate by taking the hard mask layer as a mask to form the fin body.
4. The method of manufacturing a fin field effect transistor of claim 3, wherein: in the second step, the top surface of the FCVD oxide layer is level with the top surface of the hard mask layer;
in the fourth step, before or after the back etching of the FCVD oxide layer, a step of removing the hard mask layer is further included.
5. The method of manufacturing a fin field effect transistor according to claim 1 or 2, wherein: in step five, the sacrificial medium layer at least covers the side surface of the top part of the fin body.
6. The method of manufacturing a fin field effect transistor of claim 5, wherein: in the fifth step, the sacrificial medium layer covers the top surface and the side surface of the top part of the fin body and the top surface of the FCVD oxide layer outside the fin body.
7. The method of manufacturing a fin field effect transistor according to claim 1 or 2, wherein: in the fifth step, the material of the sacrificial dielectric layer comprises silicon oxide or silicon nitride.
8. The method of manufacturing a fin field effect transistor according to claim 1 or 2, wherein: and sixthly, after the second annealing, respectively losing 2nm of width at two sides of the bottom part of the fin body.
9. The method of manufacturing a fin field effect transistor according to claim 1 or 2, wherein: after the seventh step, the method also comprises the following steps:
and forming a pseudo gate structure formed by overlapping the pseudo gate dielectric layer and the polycrystalline silicon pseudo gate by adopting a deposition and graphical etching process.
10. The method of manufacturing a fin field effect transistor of claim 9, further comprising:
forming a source region and a drain region in the top parts of the fin bodies of the two layers of the pseudo gate structure;
forming a zero-layer interlayer film and flattening the zero-layer interlayer film to enable the top surface of the zero-layer interlayer film to be level to the top surface of the pseudo gate structure;
and removing the pseudo gate structure by a gate replacement process, and forming a gate structure formed by overlapping a gate dielectric layer and a metal gate in the pseudo gate structure removal region.
11. The method of manufacturing a fin field effect transistor according to claim 1 or 2, wherein: directly adopting the bottom part of the fin body with the reduced width in the step six as a penetration-preventing layer of the fin field effect transistor;
or, after the sixth step, adding a punch-through prevention implantation process, wherein the punch-through prevention implantation injects punch-through prevention impurities into the bottom part of the fin body with the reduced width, and the impurity dosage of the punch-through prevention implantation is reduced in combination with the reduction of the width of the bottom part of the fin body, so as to reduce the doping influence on the top part of the fin body.
12. The method of manufacturing a fin field effect transistor of claim 9, wherein: and the pseudo gate dielectric layer adopts an oxide layer.
13. The method of manufacturing a fin field effect transistor of claim 9, wherein: and forming a side wall on the side surface of the pseudo gate dielectric layer after the pseudo gate dielectric layer is formed.
14. The method of claim 10, wherein: the step of forming the source region and the drain region comprises a step of forming an embedded epitaxial layer and a step of performing source and drain injection.
15. The method of claim 10, wherein: the gate dielectric layer includes a high dielectric constant layer.
CN202111097921.0A 2021-09-18 2021-09-18 Method for manufacturing fin field effect transistor Pending CN113948396A (en)

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