KR20100074503A - Trench gate mosfet and method for fabricating of the same - Google Patents

Trench gate mosfet and method for fabricating of the same Download PDF

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Publication number
KR20100074503A
KR20100074503A KR1020080132961A KR20080132961A KR20100074503A KR 20100074503 A KR20100074503 A KR 20100074503A KR 1020080132961 A KR1020080132961 A KR 1020080132961A KR 20080132961 A KR20080132961 A KR 20080132961A KR 20100074503 A KR20100074503 A KR 20100074503A
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KR
South Korea
Prior art keywords
trench
region
gate
conductivity type
forming
Prior art date
Application number
KR1020080132961A
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Korean (ko)
Inventor
강순경
Original Assignee
주식회사 동부하이텍
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Priority to KR1020080132961A priority Critical patent/KR20100074503A/en
Publication of KR20100074503A publication Critical patent/KR20100074503A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A trench gate metal-oxide-semiconductor field-effect transistor(MOSFET) and a method for manufacturing the same are provided to form a gate oxide film on the sidewall of a trench adjacent to a source region to be thicker than a gate oxide film on a channel formation region. CONSTITUTION: A first conductive type first dopant region is formed on a first conductive semiconductor substrate(100). A second conductive body region is formed on the first conductive type first dopant region. A first conductive type dopant is implanted into a part of the second conductive body region in order to form a source region with a pre-set depth. The second conductive type body region, the source region, and the first conductive type first dopant region are selectively etched to form a trench. A gate oxide film(220) is formed through a gate oxidation process with respect to the bottom side and both sidewalls of the trench. Poly silicon is deposited to gap-fill a trench in order to form a gate(300).

Description

Trench gate MOSFET and method for fabricating of the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, and more particularly, to a method of manufacturing a trench gate type MOS transistor capable of enhancing insulation between a gate and a source.

In order to increase the density of semiconductor devices, as the size of a cell design decreases, the gap between cell pitches decreases, and the contact size also needs to be linearly reduced. However, the reduced contact size has a negative factor that increases the contact resistance, thereby increasing the power consumption of the device or slowing down the device speed.

In order to improve the device's characteristics without compromising the design aspects, it is necessary to improve the contact resistance, and one method is to use a trench gate type transistor.

The trench gate type MOS transistor allows the reduced contact size to etch the silicon substrate below the surface of the silicon substrate to form a contact, thereby increasing the overall contact surface area in contact with the silicon region to further increase the resistance.

Such a conventional trench gate type morph transistor will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing a conventional trench gate type MOS transistor.

As shown in FIG. 1, a low concentration N-type impurity region 12 is formed on a semiconductor substrate 10 made of high concentration N-type impurity. On the low concentration N-type impurity region 12, a plurality of low concentration P-type body regions 14 are formed to be electrically separated from each other by trench isolation regions. Here, the low concentration P-type body region 12 is formed shallower than the depth of the trench isolation region.

A gate oxide film 16 is formed on the bottom and sidewalls of the trench isolation region, and polysilicon is gap-filled in the trench isolation region to form the polysilicon gate electrode 18. A source or drain region 20 made of a high concentration N-type impurity is formed at a portion of the trench isolation region in contact with both sidewalls.

However, in the conventional trench gate type MOS transistor, the leakage current characteristic between the gate and the source becomes weak due to the possibility of damaging the gate oxide layer in the upper portion A during the polysilicon deposition and etch back process to make the gate electrode, thereby lowering the yield. There is a problem that causes.

Accordingly, an object of the present invention is to provide a method for manufacturing a trench gate type MOS transistor which can enhance the insulation between the gate and the source.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

A method of manufacturing a trench gate type MOS transistor according to the present invention includes forming a first conductivity type first impurity region on a first conductivity type semiconductor substrate and a second conductivity type on the first conductivity type first impurity region. Forming a body region, forming a source region to a predetermined depth by implanting a first conductivity type impurity into a predetermined portion of the second conductivity type body region, and forming the second conductivity type body region, the source region and the first region; Forming a trench by selectively etching the first conductivity type impurity region, forming a gate oxide layer on the bottom surface and both sidewalls of the trench through a gate oxidation process, and depositing polysilicon to gapfill the trench To form a gate.

As described above, in the method of manufacturing the trench gate type MOS transistor according to the present invention, a gate oxide film having a relatively thicker thickness than the gate oxide film of a portion where a source region is formed before the gate oxide film is formed and a channel is formed during the thermal gate oxide film formation process is performed. The insulation between the gate and the source can be strengthened. In addition, since the thickly formed gate oxide film does not act as a channel but simply acts as an insulating film between the gate and the source, the performance of the conventional transistor can be maintained as it is.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in certain cases, the term is arbitrarily selected by the applicant. In this case, since the meaning is described in detail in the description of the present invention, It is to be understood that the present invention is to be understood as the meaning of the term rather than the name.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments.

Hereinafter, a method of manufacturing a trench gate type MOS transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of manufacturing a trench gate type MOS transistor according to the present invention.

First, as shown in FIG. 2A, the low concentration N-type impurity region 120 is formed on the semiconductor substrate 100 made of the high concentration N-type impurity using an epitaxial growth method. Subsequently, low concentration P-type impurities are ion-implanted on the surface of the low concentration N-type impurity region 120 and the implanted impurities are activated to form the low concentration P-type body region 140.

Thereafter, a high concentration N-type impurity is implanted into the trench region to be formed in a subsequent process of the low concentration P-type body region 140 to form a source region 160 made of high concentration N-type impurity to a predetermined depth.

Next, as shown in FIG. 2B, a photoresist is applied on the low concentration P-type body region 140 including the source region 160, and then patterned through an exposure and development process to form a trench to be formed in a subsequent process. A photoresist pattern 180 is formed to expose a portion corresponding to the photoresist pattern 180. Next, the trench 200 may be selectively etched by selectively etching the low concentration P-type body region 140, the source region 160, and the low concentration N-type impurity region 120 through an etching process using the photoresist pattern 180 as an etching mask. Form. At this time, the trench 200 is formed deeper than the depth of the low-concentration P-type body region 140, and the source region 160 of a portion adjacent to both side walls of the trench 200 is formed to remain at a predetermined portion.

Subsequently, as illustrated in FIG. 2C, a thermal gate oxidation process is performed on the trench 200 to form the gate oxide layer 220 on the bottom surface and both side walls of the trench 200. In this case, the gate oxide film 220 formed on the sidewall portion of the trench adjacent to the source region 160 is formed thicker than other portions as the source region 160 is high in concentration.

Thereafter, as shown in FIG. 2D, after the photoresist pattern 180 is removed through the strip process, polysilicon is formed on the front surface of the low concentration P-type body region 140 including the trench 200 to be gap-filled in the trench 200. After the deposition, the planarization is performed through an etchback or chemical mechanical polishing process (CMP) to form the gate 300 embedded in the trench 200.

Accordingly, the present invention can enhance the insulation between the gate and the source by forming a source region prior to forming the gate oxide layer to form a gate oxide layer that is relatively thicker than the gate oxide layer of the region where the channel is formed during the thermal gate oxide layer forming process. In addition, since the thickly formed gate oxide film does not act as a channel but simply acts as an insulating film between the gate and the source, the performance of the conventional transistor can be maintained as it is.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view showing a conventional trench gate type MOS transistor.

2A to 2D are cross-sectional views illustrating a method of manufacturing a trench gate type MOS transistor according to the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 120 low concentration N-type impurity region

140: low concentration P-type body region 160: source region

180: photoresist pattern 200: trench

220: gate oxide film 300: gate

Claims (5)

Forming a first conductivity type first impurity region on the first conductivity type semiconductor substrate, Forming a second conductivity type body region on the first conductivity type first impurity region; Forming a source region to a predetermined depth by implanting a first conductivity type impurity into a predetermined portion of the second conductivity type body region; Selectively etching the second conductivity type body region, the source region and the first conductivity type first impurity region to form a trench; Forming a gate oxide film on the bottom surface and both sidewalls of the trench through a gate oxidation process; And forming a gate by depositing polysilicon to gap fill the trench. The method of claim 1, Forming the trench And forming the trench deeper than a depth of the second conductive body region. The method of claim 1, Forming the trench And the source region is formed at a portion adjacent to both sidewalls of the trench so that a predetermined portion remains. The method of claim 1, And the gate oxide film formed on the sidewalls of the trench adjacent to the source region is thicker than the gate oxide film formed on the other portion. The method of claim 1, And the source region is formed by implanting a high concentration of a first conductivity type impurity.
KR1020080132961A 2008-12-24 2008-12-24 Trench gate mosfet and method for fabricating of the same KR20100074503A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613965B2 (en) 2011-10-13 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor
US9634134B2 (en) 2011-10-13 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor
US11315931B2 (en) 2011-10-13 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613965B2 (en) 2011-10-13 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor
US9634134B2 (en) 2011-10-13 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor
US10103151B2 (en) 2011-10-13 2018-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor
US10700070B2 (en) 2011-10-13 2020-06-30 Taiwan Semiconductor Manufacturing Company Embedded transistor
US10748907B2 (en) 2011-10-13 2020-08-18 Taiwan Semiconductor Manufacturing Company Embedded transistor
US11315931B2 (en) 2011-10-13 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded transistor

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